JPH11194713A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device capable of making a control reduction in the substrate small in size, short in manufacturing processes and low in cost, and further capable of improving display performance. SOLUTION: This liquid crystal display device has a control substrate 1, a glass substrate 2, and FPC 3 (flexible printed circuit) whose both ends are connected with both of the substrates 1, 2. On the glass substrate 2, a source driver 14 and a gate driver 8 are packaged and also a TFT panel 9 driven by both of these drivers 8, 14 are arranged. A timing generation circuit(TG) 15 is incorporated in the source driver 14, and the source driver 14 is connected to a color processing and inverting circuit 4, a clock generating circuit 13 and a counter electrode driving circuit 6. Moreover, the source driver 14 and the gate driver 8 are connected to each other through a 3rd wiring 20, and a control signal from the timing generation circuit 15 is supplied to the gate driver 8 through the 3rd wiring 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a display device for displaying an image or the like.

[0002]

2. Description of the Related Art As a conventional display device, a liquid crystal display device shown in FIGS. As shown in FIG. 3, the liquid crystal display device includes a control substrate 1 and a glass substrate 2,
And an FPC (flc) having both ends connected to the substrates 1 and 2
exible printed circuit) 3. On the control board 1, a color processing / inversion circuit 4, a timing generation circuit 5, and a counter electrode driving circuit 6 connected to the timing generation circuit 5 are arranged.

On the glass substrate 2, a source driver 7 and a gate driver 8 are mounted on a chip-on-glass (COG), and a TFT panel 9 driven by the drivers 7 and 8 is arranged. The source driver 7 is connected to the color processing / inversion circuit 4 and the timing generation circuit 5 via the FPC 3, and the gate driver 8
Are connected to the timing generation circuit 5 via the FPC 3.

[0004] As shown in FIG. 4, the TFT panel 9 has a lower transistor generating substrate 10 and an opposing glass substrate 11 facing the transistor generating substrate 10. VCOM arranged on the opposite glass substrate 11 side
The (counter electrode drive signal) wiring 16 and the CS (capacitor drive signal) wiring 17 arranged on the transistor generation substrate 10 side are connected at the connection cross point 12 and
3 is connected to the opposing electrode driving circuit 6.

That is, one pixel in the TFT panel 9 needs a wiring CS to a storage capacitor and a wiring VCOM to a counter electrode as shown in FIG. 5 in addition to the wiring from the drivers 7 and 8. And one wiring CS is provided on the upper surface of the transistor generation substrate 10 and the other wiring VC
The OM is provided on the lower surface of the opposite glass substrate 11. Also,
Normally, the same signal is used for VCOM and CS. Therefore, as described above with reference to FIG. 4, the CS wiring 17 and the VCOM wiring 16 are connected by the connection cross point 12.

In such a configuration, the color processing / inversion circuit 4
Converts the input video signal into RGB video data, inverts the video signal and converts it into AC, and the timing generation circuit 5 operates in synchronization with the synchronization signal C-SYNC to generate and output a control signal. Thereby, the source driver 7
Is supplied with a source driver control signal a composed of an RGB signal from the color processing / inversion circuit 4 and a control signal from the timing generation circuit 5, and a gate driver 8 is supplied with a gate driver control signal b from the timing generation circuit. You.
The counter electrode drive circuit 6 includes a timing generation circuit 5.
Supplies the VCOM creation signal d, and in response to this, the counter electrode drive circuit 6 generates and outputs a counter electrode drive signal c. This counter electrode drive signal c is connected to the connection cross point 1
2 are supplied to the CS wiring 17 and the VCOM wiring 16 via the capacitor driving signal CS and the common electrode driving signal V.
Functions as COM.

[0007]

However, in such a conventional liquid crystal display device, as shown in FIG.
Both drivers 7 and 8 and the timing generation circuit 5 are separate LS
I, the timing generation circuit 5 is disposed on the control substrate 1, and both drivers 7, 8 are disposed on the glass substrate 2. Therefore, the control board 1 requires a mounting area for a timing generation LSI or the like that forms the timing generation circuit 5, and as a result, the size of the board is increased.

A control substrate 1 and a glass substrate 2
, A large number of control signal lines must be connected via the FPC 3. That is, from the control board 1 to the FP
A signal input to the glass substrate 2 via C3 includes at least a clock signal MCLK, a start signal SRT, and a clear signal CL as the source driver control signal a.
R, output enable OE, and each of the video signals R, G, and B. First, seven signal lines are required. Also,
As the gate driver control signal b, the gate clock GP
CK, a gate start signal GSRT, and a gate output enable GRES, which require three signal lines. Further, since a signal line for the counter electrode drive signal (VCOM) d is also required, at least a total of 11 signal lines are required. Therefore, since the wiring of such a large number of signal lines becomes indispensable, the manufacturing process becomes longer and the cost increases.

Further, since a large number of control signals from the control board 1 are routed through the wiring on the control board 1, the FPC 3 and the glass board 2, the amount of delay varies between the signals. In addition, the display performance of the liquid crystal display device is deteriorated, and a malfunction may occur in some cases.

The present invention has been made in view of such conventional problems, and can reduce the size of the control board, shorten the manufacturing process and reduce the cost, and further improve the display performance. It is an object of the present invention to provide a display device which can be improved.

[0011]

According to the first aspect of the present invention, there is provided a drive circuit operating at a predetermined timing, and a display panel driven by the drive circuit to perform a display operation. , A control means for controlling the operation timing of the drive circuit is provided in the drive circuit. Therefore,
It is not necessary to supply a control signal for controlling the operation timing from another circuit to the drive circuit, so that wiring for supplying the control signal is not required, and the scale of the other circuit can be reduced.

According to a second aspect of the present invention, there is provided a drive circuit which operates at a predetermined timing, and a display panel which is driven by the drive circuit and performs a display operation, wherein the drive circuit is provided on the display panel. In the display device disposed on the component, the component of the display panel is provided with control means for controlling the operation timing of the drive circuit. Therefore, there is no need to supply a control signal for controlling the operation timing of the drive circuit from another circuit to the constituent members of the display panel, and wiring for supplying the control signal is not required, and other circuits are not required. Can be scaled down.

According to a third aspect of the present invention, the drive circuit includes a gate driver for driving a scan line of the display panel and a source driver for driving a signal line. Is provided with the control means, and a control signal from the control means is supplied to the other driver. Therefore, both drivers can be operated at a predetermined operation timing without supplying a control signal for controlling the operation timing of both drivers from another circuit.

Further, in the invention according to claim 4, a connection wiring for connecting a gate driver for driving a scanning line of the display panel and a source driver for driving a signal line is provided, wherein the connection wiring provided with the two drivers is provided. A signal to be supplied to one of the substrates is formed on one of the opposite substrates of the display panel, and a signal to be supplied to the one of the substrates is routed to the other of the opposite substrates, and supplied from the other substrate. Therefore, it is possible to arrange the connection wiring and the signal wiring to be supplied to the one substrate so as not to intersect on the same plane on the one substrate. Therefore, it is not necessary to make one of the substrates a multilayer, and the occurrence of crosstalk is also avoided.

Further, in the invention according to claim 5, the source driver is provided with control means for controlling operation timings of the two drivers, and a control signal of the control means is transmitted to the gate driver via the connection wiring. It is made to supply. Therefore, as described above, the occurrence of the crosstalk is prevented while eliminating the need for wiring for supplying a control signal from another circuit and reducing the scale of the other circuit.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. That is, as shown in FIG. 1, the liquid crystal display device according to the present embodiment has a control substrate 1, a glass substrate 2, and an FPC 3 having both ends connected to both substrates 1, 2. The control board 1 includes a color processing / inversion circuit 4 for converting a video signal into video data and inverting the video data, a clock generation circuit 13 for generating and outputting a clock signal of a predetermined frequency, and a counter electrode driving circuit 6.

A source driver 14 and a gate driver 8 are mounted on the glass substrate 2 by COG.
A TFT panel 9 driven by these drivers 8 and 14 is arranged. The source driver 14 includes a timing generation circuit (TG) 15. The source driver 14 is connected to the color processing / inversion circuit 4 and the clock generation circuit 13 via the first wiring 18 via the FPC 3 and the second wiring 1.
At 9, it is connected to the counter electrode drive circuit 6.

As shown in FIG. 2, the TFT panel 9 has a lower transistor generating substrate 10 and an upper opposing glass substrate 11 facing the transistor generating substrate 10. On the lower surface of the opposite glass substrate 11, V
A COM (counter electrode driving signal) wiring 16 is provided, and a CS (capacitor driving signal) wiring 17, a third wiring 20, and a fourth wiring 21 are provided on the upper surface of the transistor generation substrate 10.

One end 16a of the VCOM wiring 16 is connected to the fourth wiring 21 and the FPC 3 at a first connection cross point 22 rising from the upper surface of the transistor generation substrate 10.
Is connected to the counter electrode drive circuit 6 via Also,
The other end 16b of the VCOM wiring 16 is
At the second connection cross point 21 that falls from the lower surface of the first wiring 1, it is connected to the corresponding other end 17 b of the CS wiring 17. Further, the third wiring 22 has one end connected to the source driver 14 and the other end connected to the gate driver 8.

In such a configuration, the color processing / inversion circuit 4
Converts the input video signal into RGB video data, and inverts it to convert it into AC. The converted video data RGB, the synchronization signal C-SYNC, and the clock signal generated by the clock generation circuit 13 are supplied to the source driver 14 from the first wiring 18 as a source driver control signal a.

Then, the source driver 7 operates based on the source driver control signal a, the built-in timing generation circuit 15 operates, and the counter electrode driving circuit is transmitted from the source driver 14 via the second wiring 19. 6 is supplied with the VCOM creation signal d, and the third wiring 2
0, a gate driver control signal b is supplied to the gate driver 8.

When the VCOM creation signal d is supplied, the counter electrode drive circuit 6 generates and outputs a counter electrode drive signal c in response. This counter electrode drive signal c is
After being supplied to the CS wiring 17 via the first connection cross point 22, the VCO is supplied via the second connection cross point 23.
It is supplied to the M wiring 16 and functions as a capacitor drive signal CS and a counter electrode drive signal VCOM.

Here, since the timing generation circuit 15 is built in the source driver 14 on the glass substrate 2 side, there is no need to arrange a timing generation LSI on the control substrate 1 as in the conventional case. Therefore, it is not necessary to secure these mounting areas in the control board 1, and as a result, the board can be downsized, and the downsizing of the imaging device can be promoted.

Since the timing generation circuit 15 is disposed on the glass substrate 2 side, the number of control signal lines required between the control substrate 1 and the glass substrate 2 is reduced. That is, the signals input from the control substrate 1 to the glass substrate 2 via the FPC 3 include the video signals R, G, B from the color processing / inversion circuit 4 and the clock generation circuit 13.
Input CK, synchronization signal C-SYNC, VC
It is only necessary to have a total of seven signal lines, including seven types of the OM creation signal FRP (signal d) and the counter electrode drive signal VCOM (signal c). Therefore, the control substrate 1 and the glass substrate 2
The required number of control signal lines is reduced during this period, so that the manufacturing process can be shortened and the cost can be reduced.

Further, as clearly shown in FIG. 2B, the fourth wiring 21 connected to the counter electrode driving circuit 6 is connected to one end 1 of the VCOM wiring 16 at the first connection cross point 22.
6 a, and the other end 16 b of the VCOM wiring 16 is connected to the corresponding other end 17 b of the CS wiring 17 at the second connection cross point 23. Therefore, even if the third wiring 20 that connects the source driver 14 and the gate driver 8 is provided, the third wiring 20 is
It does not cross the wiring 17.

That is, if the third wiring 20 connecting the source driver 14 and the gate driver 8 is provided in the conventional structure shown in FIG.
Crosses the CS wiring 17 on the transistor generation substrate 10 in a plane. Therefore, both cannot be wired in a single layer, and it is necessary to form a multilayer. In the case of the multilayer, display performance is degraded due to crosstalk between signals, and a malfunction may occur in some cases.

However, according to the present embodiment, as described above, even if the third wiring 20 for connecting the source driver 14 and the gate driver 8 is provided, the third wiring 20 is located on the same plane as the CS wiring 17. Therefore, it is not necessary to form a multilayer structure, and therefore, there is no possibility that the display performance is degraded or a malfunction occurs due to the crosstalk. Therefore,
While providing the third wiring 20 for connecting the source driver 14 and the gate driver 8 on the transistor generation substrate 10,
It is possible to prevent display performance degradation and malfunction due to crosstalk.

[0028]

As described above, according to the present invention, a control means for controlling the operation timing of a drive circuit for driving a display panel is provided in the drive circuit, or a constituent member of the display panel in which the drive circuit is arranged is provided. Control means for controlling the operation timing of the drive circuit is provided. Therefore, it is possible to reduce the size and size of the components mounted on the control board for controlling the display panel and reduce the number of signal lines connected between the control board and the display panel. . Therefore, not only the manufacturing process can be shortened and the cost can be reduced, but also the control signal of the drive circuit is not delayed and the amount of delay does not vary among the signals, and the display performance of the display device is improved. Can be done.

Further, a control means is provided in one of the gate driver and the source driver, and a control signal from the control means is supplied to the other driver. Therefore, both drivers can be accurately operated at a predetermined operation timing without supplying a control signal for controlling the operation timing of both drivers from the control board, thereby shortening the manufacturing process and reducing the cost. In addition, the display performance of the display device can be improved.

Further, a connection wiring for connecting the gate driver and the source driver is formed on one of the opposite substrates of the display panel provided with both drivers, and the signals to be supplied to the one substrate are mutually opposed. To be supplied to the other substrate side. Therefore, it is possible to arrange the connection wiring and the signal wiring to be supplied to the one substrate in a state where they do not intersect on the same plane on the one substrate. Therefore, it is not necessary to form one substrate in a multilayer, and it is possible to prevent the occurrence of crosstalk. A display having a circuit connecting both drivers without using a substrate in a multilayer and preventing the occurrence of crosstalk is also possible. A device can be obtained.

Further, since the source driver is provided with control means for controlling the operation timing of the two drivers, and the control signal of the control means is supplied to the gate driver via the connection wiring, as described above, Wiring for supplying a control signal from another circuit is not required, and the scale of the other circuit can be reduced, and the occurrence of crosstalk can be prevented.

[0032]

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing one embodiment of the present invention.

FIG. 2A is a plan view of a TFT panel, and FIG. 2B is a view indicated by an arrow B in FIG.

FIG. 3 is a block diagram showing a conventional display device.

FIG. 4A is a plan view of a TFT panel in the display device, and FIG. 4B is a view shown by an arrow B in FIG.

FIG. 5 is a circuit diagram of one pixel in the display device.

[Explanation of symbols]

 8 gate driver 9 TFT panel 14 source driver 15 timing generator

Claims (5)

[Claims] 1. A display device comprising: a drive circuit that operates at a predetermined timing; and a display panel that is driven by the drive circuit to perform a display operation. A display device provided in a circuit. 2. A display device comprising: a drive circuit that operates at a predetermined timing; and a display panel that is driven by the drive circuit and performs a display operation, wherein the drive circuit is disposed on a component of the display panel. A display device, comprising: a control member for controlling operation timing of the drive circuit provided on a component of the display panel. 3. The drive circuit comprises a gate driver for driving a scan line of the display panel and a source driver for driving a signal line. One of the drivers is provided with the control means and the other driver is provided. 3. The display device according to claim 1, wherein a control signal from said control means is supplied to said display device. 4. A connection line for connecting a gate driver for driving a scan line of a display panel and a source driver for driving a signal line is formed on one of the opposite substrates of the display panel provided with the both drivers. A display device, wherein a signal to be supplied to one of the substrates is routed to the other substrate facing the other substrate and supplied from the other substrate. 5. The control circuit according to claim 1, wherein said source driver is provided with control means for controlling operation timings of said two drivers, and a control signal of said control means is supplied to said gate driver via said connection wiring. Item 5. The display device according to Item 4.