JPH11177843A - Phase locked loop - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restore a synchronous state in a short time even in the case that the phase of input signals is suddenly changed. SOLUTION: This phase locked loop is provided with an excessive phase difference detection means 18 for detecting an excessive phase difference whose phase comparison point of the input signals is not in a phase range capable of maintaining the synchronous state, and at the time of detecting it, resetting a frequency divider means 17 with the phase comparison point of the input signals as a reference and forcibly shifting the phase of frequency division signals so as to eliminate the phase difference of the input signals and the frequency division signals. Also, the phase locked loop is provided with a holding means 14 provided on a signal route from a phase comparison means 12 to a voltage controlled oscillation means 16 for holding an output voltage level immediately before when the excessive phase difference detection means performs a detection operation and a gate means 13 for obstructing voltage input to the holding means so as to suppress the change of a holding voltage by the holding means 14 when the excessive phase difference detection means 18 performs the detection operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit, and is applicable to, for example, a phase locked loop circuit for generating a reference clock signal phase-locked to a horizontal sync signal of a television signal.

[0002]

2. Description of the Related Art As a conventional phase synchronization circuit for generating a reference clock signal phase-synchronized with a horizontal synchronization signal, for example, there is one shown in FIG. Hereinafter, an outline of a conventional phase locked loop circuit will be described with reference to FIG.

A horizontal synchronizing signal applied to an input terminal 1 is applied to a phase comparator 2 where the horizontal synchronizing signal from the input terminal 1 and the frequency-divided horizontal synchronizing signal from the frequency divider 5 are compared. The phases are compared and a phase difference signal (eg,
Low-pass filter (LP)
F) given to 3). In the low-pass filter 3, the control signal (signal) is formed by smoothing the phase difference signal, and the control voltage is supplied to the voltage-controlled oscillation circuit (VCO) 4. In the voltage controlled oscillation circuit 4, a reference clock signal having a frequency according to the control voltage from the low-pass filter 3 is oscillated, and the reference clock signal is supplied to the frequency dividing circuit 5 and the output terminal 6. In the frequency dividing circuit 5, a frequency-divided horizontal synchronizing signal is generated by dividing the frequency of the reference clock signal from the voltage controlled oscillator circuit 4.
Given to.

[0004] By such an operation, the conventional phase synchronization circuit generates a reference clock signal phase-synchronized with the horizontal synchronization signal applied to the input terminal 1 and outputs the reference clock signal to the output terminal 6.

[0005]

As the voltage controlled oscillation circuit in the phase locked loop circuit, there are a circuit to which an LC oscillation circuit is applied and a circuit to which a crystal oscillation circuit is applied.

However, both of these two types of phase locked loop circuits have advantages and disadvantages, and there is room for improvement.

That is, a circuit to which an LC oscillation circuit is applied has a good tracking characteristic with respect to a phase change of an input signal, but maintains a synchronized state due to a small fluctuation of the input signal because the tracking characteristic is good. However, there is a problem that the frequency of the output signal (reference clock signal) changes, frequency stability is inferior, and much jitter occurs.

[0008] From this point, it is preferable to apply a crystal oscillation circuit. However, when a large phase change occurs, such as when the input signal is switched or suddenly changed, the crystal oscillator circuit returns to a stable state (synchronous pull-in state) due to the slow tracking characteristic. There is a problem that it takes a long time to complete.

For example, in the case of a television receiver, when a channel is switched, a horizontal synchronizing signal (input signal)
In the case of a video signal processing device, a large phase change occurs in the horizontal synchronizing signal (input signal) when the signal source (such as a storage device) of the video signal to be processed is switched.

As described above, in the case where the crystal oscillation circuit is applied, in such a case, it takes a long time to return to a stable state (synchronous pull-in state).

For this reason, there is a need for a phase locked loop circuit that can reduce the time required to re-lock to the synchronized state even if the input signal loses synchronization due to a large phase change of the input signal, while ensuring the stability of the output frequency in the synchronized state. .

[0012]

In order to solve the above-mentioned problems, the present invention provides a phase comparing means for detecting a phase difference between an input signal and a frequency-divided signal, and a control voltage corresponding to the detected phase difference. In a phase-locked loop comprising: a voltage-controlled oscillating means for generating a high-frequency signal having a frequency corresponding to the control voltage; and a frequency-dividing means for dividing the high-frequency signal to generate the frequency-divided signal, Is provided.

That is, (1) an excessive phase difference in which the phase comparison point of the input signal is not within the phase range in which the synchronized state can be maintained, and when the phase difference is detected, the frequency dividing means based on the phase comparison point of the input signal. Resetting, and excessive phase difference detecting means for forcibly shifting the phase of the frequency-divided signal so as to eliminate the phase difference between the input signal and the frequency-divided signal; and (2) the excessive phase difference detecting means performs a detecting operation. A holding means provided on a signal path from the phase comparing means to the voltage controlled oscillating means for holding the immediately preceding output voltage level; and (3) when the excessive phase difference detecting means performs a detecting operation. And a gate means for preventing a voltage input to the hold means so as to suppress a change in a holding voltage by the hold means.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which a phase locked loop according to the present invention is applied to a phase locked loop that generates a reference clock signal phase-locked to a horizontal sync signal of a television signal will be described below with reference to the drawings. It will be described in detail.

FIG. 1 is a block diagram showing the configuration of this embodiment, and FIG. 3 is a signal waveform diagram of each part.

In FIG. 1, the phase locked loop circuit of this embodiment includes an input terminal 11, a phase comparison circuit 12, a gate circuit 13, a voltage hold circuit 14, a low-pass filter 15, a voltage controlled oscillation circuit 16, It has a frequency dividing circuit 17, an excessive phase difference detecting circuit 18, and an output terminal 19.

The horizontal synchronizing signal REFH of the television signal supplied to the input terminal 11 is supplied to the phase comparison circuit 12 and the excessive phase difference detection circuit 18.

The phase comparator 12 compares the phase of the horizontal synchronizing signal REFH from the input terminal 11 with the frequency of the divided horizontal synchronizing signal H from the frequency divider 17.
It outputs a phase difference signal corresponding to the phase difference between FH and H. In the case of this embodiment, the phase comparison circuit 12 outputs a voltage level corresponding to the phase difference as a phase difference signal.

When a gate signal G1 from an excessive phase difference detecting circuit 18 to be described later is at an open level (for example, L), the gate circuit 13 holds a phase difference signal (voltage level) from the phase comparing circuit 12 as a voltage hold circuit 14. Block input to
When the gate signal G1 is at a closed level (for example, H), the phase difference signal (voltage level) from the phase comparison circuit 12 is directly supplied to the voltage hold circuit 14.

When the hold signal HOLD from the excessive phase difference detecting circuit 18 described later changes to a hold level (for example, L), the voltage hold circuit 14
3, the voltage of the phase difference signal (voltage level) that has passed through is taken in, and the voltage is held as an output signal level during a period in which the hold signal HOLD indicates the hold level. For example, in the case of H), the phase difference signal (voltage level) from the gate circuit 13 is passed. An output signal (hold voltage signal or phase difference signal) from the voltage hold circuit 14 is provided to a low-pass filter 15.

As will be described later, the hold signal HOLD changes to the hold level (for example, L) slightly earlier than the gate signal G1 changes to the open level.

The low-pass filter 15 smoothes an output signal (voltage level) from the voltage hold circuit 14 and forms a control voltage (signal) to be applied to the voltage control oscillation circuit 16.

The voltage controlled oscillation circuit 16 oscillates a reference clock signal having a frequency corresponding to the control voltage from the low pass filter 15, and supplies the reference clock signal to the frequency dividing circuit 17 and the output terminal 19.

In the case of this embodiment, the voltage controlled oscillation circuit 1
6, it is assumed that a device having a crystal oscillation circuit is applied in consideration of frequency stability in a synchronized state. Even in such a case, the above-described gate circuit 13 and voltage hold circuit 14, and an excessive phase difference detection circuit 18, which will be described later, are provided so as to shorten the re-locking time from the out-of-synchronization state to the synchronization state.

The frequency dividing circuit 17 is constituted by using, for example, a counter.
From the reference clock signal to generate a horizontal synchronization signal (referred to as a divided horizontal synchronization signal) H. The divided horizontal synchronization signal H is supplied to the phase comparison circuit 12 as described above. Is to give.

In the case of this embodiment, the frequency dividing circuit 17 outputs a window pulse signal (for example, the logical level as the window period is L) H to be supplied to the excessive phase difference detecting circuit 18.
2 is also responsible for the generation function. The frequency divider 17 also forms the window pulse signal H2 by dividing the frequency of the reference clock signal from the voltage controlled oscillator 16.

The window period of the window pulse signal H2 (periods t1 to t4 in FIG. 3) corresponds to the input horizontal synchronization signal RE.
It is better to process the phase change of FH as maintaining the synchronization state, or it is better to process the phase change of the input horizontal synchronization signal REFH from the synchronization state to the out-of-synchronization state. Are selected so that they can be distinguished.

In the case of this embodiment, the frequency dividing circuit 17 takes a significant level, for example, about one horizontal scanning period after the phase comparison point (eg, falling edge) of the frequency-divided horizontal synchronizing signal. Window pulse signal H
2 shall be formed.

The frequency dividing circuit 17 outputs a reset signal R of a significant level (for example, L) from an excessive phase difference detecting circuit 18 described later.
When ES is input, it is reset. The reset may reset both the generation configuration of the frequency-divided horizontal synchronization signal H and the window pulse signal H2. Alternatively, only the generation configuration of the frequency-divided horizontal synchronization signal H may be reset, and the window pulse signal H2 may be reset. May be affected through the frequency-divided horizontal synchronizing signal H whose phase has been changed by the reset.

The excessive phase difference detection circuit 18 determines that the phase comparison point of the input horizontal synchronizing signal REFH is the window pulse signal H
The logic levels of the gate signal G1, the hold signal HOLD, and the reset signal RES described above are controlled depending on whether or not the second window period has entered.

The contents of the control over these signals by the excessive phase difference detecting circuit 18 will be described in detail in the operation description which will be described later.

The excessive phase difference detecting circuit 18 determines that the phase comparison point of the input horizontal synchronizing signal REFH is the window pulse signal H
In the case of entering the second window period, the gate signal G1 is set to the closed level, the hold signal HOLD is set to the passing level, and the reset signal RES is set to the insignificant level.

On the other hand, when the phase comparison point of the input horizontal synchronization signal REFH is not within the window period of the window pulse signal H2, the excessive phase difference detection circuit 18 first changes the hold signal HOLD to the hold level. The gate signal G1 is changed to an open level with a slight delay (it is sufficient to secure a minimum time sufficient to hold data reliably), the reset signal RES is set to a significant level, and the frequency dividing circuit 17 is reset.

Hereinafter, the operation of the phase locked loop circuit of this embodiment will be described with reference to the signal waveform diagrams of the respective parts shown in FIG.

In a situation where the phase of the input horizontal synchronizing signal REFH from the input terminal 11 shown in FIG. 3A is small and the synchronization state continues, the input horizontal synchronizing signal REFH and FIG. ) Is small, and the phase comparison point t2 of the input horizontal synchronization signal REFH is in the window period (t1) of the window pulse signal shown in FIG. To t4). At this time, the excessive phase difference detection circuit 18
The closing level of the gate signal G1 shown in (D) is continued,
The pass level of the hold signal HOLD shown in FIG. 3E is continued, and no reset pulse is generated in the reset signal RES shown in FIG.

Therefore, in this case, the operation becomes equivalent to a conventional phase locked loop circuit without the gate circuit 13 and the voltage hold circuit 14, and the phase locked loop processing in a synchronized state is executed.

In the case of this embodiment, the frequency dividing circuit 17 counts the reference clock signal with reference to the phase comparison point of the frequency-divided pulse signal H, and determines when the phase comparison point is delayed by approximately one horizontal scanning period. Are formed to form a window period (window pulse). For example, on the basis of the phase comparison point t3 of the frequency-divided pulse signal H, window periods t7 to t8 are formed.

If there is no large phase change in the input horizontal synchronizing signal REFH, the next phase comparison point of the input horizontal synchronizing signal REFH is also determined by (T
1) Enter the window period.

However, in practice, a large phase change may occur in the input horizontal synchronization signal REFH. For example, when the phase synchronization circuit is applied to a television receiver, when the channel is switched, a large phase change occurs in the input horizontal synchronization signal REFH. Further, for example, when the phase synchronization circuit is applied to a television signal editing device, when the television signal (source) to be processed is switched, a large phase change occurs in the input horizontal synchronization signal REFH.

In FIG. 3, after the time point t4, a large phase change (leading phase) occurs in the input horizontal synchronization signal REFH due to channel switching or the like, and the input horizontal synchronization signal RE
It is assumed that the next phase comparison point occurs at a time point t5 where the period from the previous phase comparison point t2 of FH is considerably shorter than one horizontal scanning period.

The phase comparison point t5 after such a large phase change of the input horizontal synchronizing signal REFH corresponds to the window period t
It does not fall between 7 and t8.

At this time, the excessive phase difference detecting circuit 18 immediately changes the hold signal HOLD to the hold level, and at a slightly later time t6, reset signal RE.
A reset pulse is generated in S, and the gate signal G1 is changed to an open level.

Accordingly, first, the output voltage is held by the voltage hold circuit 14, and thereafter, the input of the voltage to the voltage hold circuit 14 is prevented and the frequency divider 17 is reset.

By resetting the frequency dividing circuit 17, the phase of the frequency-divided horizontal synchronizing signal H is forcibly shifted, and is substantially synchronized with the phase of the input horizontal synchronizing signal REFH that has undergone a large phase change (the phase difference is t5- t6). Note that the symbol T2
Shows the phase comparison point of the frequency-divided horizontal synchronization signal H when the forced phase shift is not performed for reference.

The reason why the hold by the voltage hold circuit 14 is performed before the forced phase shift of the phase of the frequency-divided horizontal synchronizing signal H is as follows.

When only the phase of the divided horizontal synchronization signal H is forcibly shifted, the divided horizontal synchronization signal H and the input horizontal synchronization signal REFH are substantially synchronized by the forced phase shift. Immediately after a large phase change (leading phase) occurs in the input horizontal synchronization signal REFH, the phase difference signal from the phase comparison circuit 12 indicates a large phase difference.
In other words, the phase difference signal is large even though it is almost synchronized, and if the phase locked loop processing is performed as it is, the operation is performed in a direction to destroy the synchronized phase relationship. Therefore, in an extreme case, the synchronization pull-in due to the reset (forced phase shift) and the subsequent loss of synchronization due to the destruction of the phase relationship may oscillate.

Therefore, it is necessary to input to the voltage control oscillation circuit 16 a control voltage which can maintain the relationship between the divided horizontal synchronization signal H synchronized by the forced phase shift and the input horizontal synchronization signal REFH. Therefore, the voltage of the voltage hold circuit 14 immediately before resetting is held.
Although it depends on the internal configuration of the phase comparison circuit 12, most of the cases where the phase comparison point of only one input signal occurs do not immediately change the phase difference signal, and it is effective to hold the immediately preceding level. In addition, the gate circuit 13 is opened to prevent an adverse effect on the hold voltage.

As described above, the frequency dividing circuit 17 counts the reference clock signal with reference to the phase comparison point of the frequency-divided pulse signal H, and determines a point in time that is delayed by about one horizontal scanning period from the phase comparison point. A window period (window pulse) having a center is formed, and a phase comparison point t6 of the frequency-divided pulse signal H generated by the reset operation is generated.
, A window period (window pulse) is formed (not shown) centered on the point delayed by about one horizontal scanning period from the phase comparison point t6.

In the window period formed based on the phase comparison point t6 of the frequency-divided pulse signal H synchronized with the input horizontal synchronization signal REFH by the reset operation (forced phase shift), the input horizontal synchronization signal REFH and frequency division are performed. Since the pulse signal H is synchronized, a phase comparison point (not shown) next to the phase comparison point t5 of the input horizontal synchronization signal REFH enters.

At this time, the gate circuit 13 and the voltage hold circuit 14 return to the operation state in the synchronous state by the control signal from the excessive phase difference detecting circuit 18, and the normal synchronous follow-up operation is performed.

As described above, according to this embodiment, when the phase of the input horizontal synchronizing signal changes suddenly, the control voltage to the voltage controlled oscillation circuit is stabilized through the voltage hold operation, and Since the frequency-divided horizontal synchronizing signal is forcibly phase-shifted so as to be synchronized with the input horizontal synchronizing signal through the reset, even if the phase of the input horizontal synchronizing signal changes suddenly, it is possible to return to the synchronized state in a short time.

In particular, in the case where a voltage controlled oscillation circuit using a crystal oscillation circuit is specified, the above effect is large because the tracking ability is slow.

In the above embodiment, the present invention is applied to the phase synchronization circuit for generating the reference clock signal phase-synchronized with the horizontal synchronization signal of the television signal. Of course, the present invention can be applied to a synchronous circuit.

In the above embodiment, the present invention is applied to a phase locked loop having a low-pass filter. However, the present invention can be applied to a phase locked loop having no low-pass filter.

Further, the present invention can be applied to a phase synchronization circuit in which a phase comparison circuit outputs a phase difference signal representing a phase difference by a pulse width, and a low-pass filter converts the signal into a control voltage. In this case, the gate circuit and the voltage hold circuit may be provided after the low-pass filter.

Further, in the above embodiment, the crystal oscillation circuit is applied as the voltage controlled oscillation circuit.
The present invention can be similarly applied to a case where another oscillation circuit such as an LC oscillation circuit is applied as the voltage controlled oscillation circuit.

In the above embodiment, the window pulse signal is formed based on the divided horizontal synchronization signal. However, the window pulse signal may be formed based on the input horizontal synchronization signal. For example, the reference clock signal may be counted based on the phase comparison point of the input horizontal synchronization signal, and a window period approximately one horizontal scanning period after the phase comparison point may be formed.

Further, in the above embodiment, the phase locked loop having the frequency divider is shown, but the present invention can be applied to a phase locked loop having no frequency divider. Even in this case, a circuit for forming a window pulse signal is required. The expression in the claims is a frequency dividing circuit (frequency dividing means)
However, the expression includes a device without a frequency dividing circuit.

[0059]

As described above, according to the present invention, a large phase change in an input signal is detected. At the time of this detection, the control voltage to the voltage control oscillating means is stabilized through the voltage hold operation, and the frequency division is performed. Since the frequency division signal is forcibly phase-shifted so as to be synchronized with the input signal through resetting of the means, even when the phase of the input signal suddenly changes, it is possible to return to the synchronization state in a short time.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an embodiment.

FIG. 2 is a block diagram for explaining a conventional phase locked loop circuit.

FIG. 3 is a signal waveform diagram of each part of the embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... Input terminal, 12 ... Phase comparison circuit, 12 ... Gate circuit, 14 ... Voltage hold circuit, 15 ... Low pass filter, 16 ... Voltage control oscillation circuit, 17 ... Division circuit, 18 ...
Phase jump detection circuit, 19 ... output terminal.

Claims (3)

[Claims] 1. A phase comparison means for detecting a phase difference between an input signal and a frequency-divided signal, and a voltage which receives a control voltage corresponding to the detected phase difference and generates a high-frequency signal having a frequency corresponding to the control voltage. In a phase synchronization circuit including a control oscillator and a frequency divider for dividing the high-frequency signal to generate the frequency-divided signal, the phase comparison point of the input signal may not be in a phase range where the synchronization state can be maintained. When the phase difference is detected, the frequency divider is reset based on the phase comparison point of the input signal, and the phase of the frequency-divided signal is changed so that the phase difference between the input signal and the frequency-divided signal is eliminated. Excessive phase difference detecting means for forcibly shifting the phase, provided on a signal path from the phase comparing means to the voltage controlled oscillating means for holding the immediately preceding output voltage level when the excessive phase difference detecting means performs a detecting operation. Hold hands And a gate means for preventing a voltage input to the hold means so as to suppress a change in a holding voltage by the hold means when the excessive phase difference detection means performs a detection operation. circuit. 2. The method according to claim 1, wherein the excessive phase difference detecting means includes a window pulse generating section for generating a window pulse having a predetermined pulse width and including a phase comparison point of the frequency-divided signal at a center portion, and a phase comparison point of the input signal. 2. The phase-locked loop according to claim 1, wherein the phase-locked loop includes a phase difference monitoring unit that detects that the pulse width is not included in the pulse width of the window pulse as an excessive phase difference. 3. The phase-locked loop according to claim 2, wherein said frequency dividing means and said window pulse generator are integrated.