JPH1117775A - Serial interface circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To smoothly transmit/receive the data of a large capacitance by generating a request packet from a present node to the other node, sending it to a serial interface, receiving the packet of a response to the request packet and performing retry operation for sending the generated request packet when the received response packet requests the resending of the request packet. SOLUTION: An interval register 1263 receives a resending request and arbitrarily set time to the retry operation and a cycle counter 1262 measures time while being started by ack busy reception. When the time of the cycle counter 1262 reaches the setting time of the interval register 1263, a comparator circuit 1265 generates a resending signal SR. A retry control register 1264 sets the number of times of retry and a busy counter 1267 counts how many times the resending signal SR is outputted from the comparator circuit 1265. When the value of the busy counter 1267 reaches the set value of the retry control register 1264, the comparator circuit 1266 is turned into timeout.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital serial interface circuit, and more particularly to a hard disk drive (HDD).
Drive), DVD (Digital Video Disk) -ROM, CD
(Compact Disk)-ROM, Tape Streamer
The present invention relates to a serial interface circuit connected to a storage device such as an amer) and a signal processing method thereof.

[0002]

2. Description of the Related Art In recent years, as an interface for multimedia data transfer, the IEEE (The Institute of Elect) has realized high-speed data transfer and real-time transfer.
ricaland Electronic Engineers) 1394, High
Performance Serial Bus has been standardized.

In the data transfer of the IEEE 1394 serial interface, a transfer operation performed in a network is called a subaction, and two subactions are defined. One is conventional Request, Acknow
Asynchronous (Asynchr) for requesting and confirming receipt of ledge
onous) forwarding, and the other is 125
Isochronous (Isoch) where data is always sent once every μs
ronous) Transfer.

As described above, an I having two transfer modes
The data in the EEE1394 serial interface is
Although transfer is performed in packet units, in the IEEE 1394 standard, the minimum data unit handled is one quadlet (q
uadlet) (= 4 bytes = 32 bits).

[0005] In the IEEE 1394 standard, computer data is normally transmitted using asynchronous transfer as shown in FIG. Asynchronous transfer is shown in FIG.
As shown in (a), there are three transition states: arbitration (arb) for acquiring a bus, packet transmission for transferring data, and acknowledgment (ack).

The execution of packet transmission is performed in a format as shown in FIG. The first quadlet of the transfer packet includes a 16-bit destination ID (destination ID) area and a 6-bit transaction label tl (transaction label).
l) area, 2-bit retry code rt (retry cod
e) area, 4-bit transaction code tcod
An e (transanction code) area and a 4-bit priority pri (priority) area. The destination ID area indicates the bus number and node number of this node, and the priority area indicates the priority level.

[0007] The second and third quadlets have a 16-bit source ID area and a 48-bit destination offset (destina- tion).
tionoffset) region. The source ID area shows the ID of the node that sent this packet, and the destination offset area shows high (High) and low (L
ow), and indicates the address of the address space of the destination node.

[0008] The fourth quadlet is composed of a 16-bit data length area and a 16-bit extended transaction code (extended tcode) area. The data length field indicates the number of bytes of the received packet, and the extended tcode field is tc.
mode is a Lock transaction
If, the actual locking action performed by the data in this packet
(Lock Action).

[0009] A header CRC (header CRC) added to the quadlet before the data field area (data field)
The area is an error detection code of the packet header. Also,
A data CRC (data CRC) area added to the quadlet after the data area (data field) is an error detection code of the data field.

[0010]

As described above, in the normal computer data transfer performed by the asynchronous transfer, the SBP-based protocol is used as the protocol.
2 (Serial Bus Protocol-2) is used. According to this protocol, a host device (Host) is transferred from a target (Target) that is a storage device.
When transferring data to the initiator, which is a Computer, the data is written from the storage device to the memory of the host computer, and when transferring the data from the host computer to the target,
The transfer is performed in such a manner that the storage device reads the data in the memory of the host computer.

However, a processing circuit system for controlling a so-called transaction layer for transmitting and receiving a large amount of data stored in or read from the storage device in packets of the IEEE 1394 standard. Has not yet been established. There is also a demand for a circuit having a retry function for retransmitting when a busy signal is received from another node.

The present invention has been made in view of the above circumstances, and an object thereof is to automate a retry operation, transmit and receive a large amount of data as a packet conforming to a predetermined standard, and Another object of the present invention is to provide a serial interface circuit capable of performing smooth transmission / reception processing.

[0013]

In order to achieve the above object, the present invention relates to a serial interface circuit for transmitting and receiving a packet between another node connected to the own node via a serial interface bus. , A first data processing circuit for generating a request packet to the other node and transmitting the request packet to the serial interface bus, and a response packet to the request packet, and the received response packet requests retransmission of the request packet. A second data processing circuit for performing a retry operation of transmitting the generated request packet to the serial interface bus again.

The present invention also relates to a serial interface circuit for transmitting / receiving a packet between another node connected to the own node via a serial interface bus, comprising: a storage unit; a request packet from the own node to another node; A request packet generation circuit that generates the request packet and stores the request packet in the storage unit; a first data processing circuit that sends the request packet stored in the storage unit to the serial interface bus; and a response packet to the request packet. A second data processing circuit for performing a retry operation of transmitting the request packet stored in the storage means to the serial interface bus again when the received response packet requests retransmission of the request packet.

Further, in the present invention, the second data processing circuit performs a retry operation of retransmitting the request packet after a set time has elapsed after receiving the retransmission request.

Further, in the present invention, the second data processing circuit includes an interval register which can arbitrarily set a time period from when a retransmission request is received to when a retry operation is performed,
A cycle counter that starts up and counts time when the retransmission request is received, and a comparison circuit that generates a retransmission signal when the time of the cycle counter reaches a time set in the interval register, and the retransmission signal is generated. And the above retry operation is performed.

Further, the present invention has a discriminating circuit for discriminating the number of retransmissions and resetting the set time of the interval register to a longer time when the count value reaches a preset number.

Further, the present invention has a limiting circuit for limiting the number of times of the retry operation. The limiting circuit includes a retry limiting register capable of setting the number of retries to be limited, a retransmission counter that counts the number of retransmission signal outputs of the comparison circuit, and when the value of the retransmission counter reaches the set value of the retry limiting register. A comparison circuit that outputs a timeout signal; and a control circuit that receives the timeout signal and stops transmitting the request packet.

Further, according to the circuit of the present invention, in the first data processing circuit, a request packet from the own node to another node is generated and transmitted to the serial interface bus. Then, when a response packet to the request packet is sent in the second data processing circuit,
When the received response packet requests retransmission of the request packet, a retry operation of transmitting the generated request packet to the serial interface bus again is performed.

Further, according to the circuit of the present invention, in the request packet generation circuit, a request packet from the own node to another node is generated and stored in the storage means. And the first
The request packet stored in the storage means is read out by the data circuit and transmitted to the serial interface bus. Then, in the second data processing circuit, when a response packet to the request packet is sent and the received response packet requests retransmission of the request packet, the generated request packet is again stored in the storage unit. A retry operation of reading and sending out to the serial interface bus is performed.

In the present invention, the retry operation is performed after a lapse of a set time from the reception of the retransmission request.

Further, in the present invention, the time from when the retransmission request is received until the retry operation is performed is arbitrarily set in the interval register. For example, in the second data processing circuit, when a retransmission request is received, a cycle counter is started, and a timekeeping operation is started. When the time of the cycle counter reaches the time set in the interval register, a retransmission signal is generated in the comparison circuit, and when the retransmission signal is generated, a retry operation is performed.

In the present invention, the number of retransmissions is determined by the determination circuit, and when the number of times reaches a preset number, the set time of the interval register is reset to a longer time.

In the present invention, the number of retry operations is limited by the limiting circuit. For example, the retransmission counter counts the number of times a retransmission signal is output by the comparison circuit of the second data processing circuit. When this count value reaches the value set in the retry limit register, a timeout signal is output from the comparison circuit to the control circuit. In the control circuit,
Upon receiving the timeout signal, transmission of the request packet is stopped.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an IEEE 1 according to the present invention.
FIG. 3 is a block diagram illustrating an embodiment of a 394 serial interface circuit. This serial interface circuit is configured to transfer computer data handled in asynchronous communication. Therefore, FIG. 1 does not show a specific configuration of the isochronous communication system circuit.

The serial interface circuit comprises a link / transaction layer integrated circuit 10, a physical layer circuit 20, a hard disk driver (HDD) controller 30 (not shown) as a storage device, and a local processor 40 as a host computer. I have.

The link / transaction layer integrated circuit 10 is formed by integrating the link layer circuit 100 and the transaction layer circuit 120, and controls the asynchronous transfer under the control of the local processor 40, as well as the physical layer circuit. 20.

As shown in FIG. 1, the link layer circuit 100 comprises a link core (Link Core) 101, a CPU interface circuit (Sub-CPU I / F) 102, and a transmission FIFO (AT-AT) used for asynchronous communication. FIFO: First-In F
irst-Out) 103, receiving FIFO (AR-FIFO) 104,
Classification circuit (DeMux) 105 for discriminating received packets, resolver for self ID (Resolver) 106, and control register (ControlRegisters, hereinafter referred to as CR) 1
07.

The link core 101 includes a transmission circuit and a reception circuit for asynchronous communication packets and isochronous communication packets to which commands and computer data are transferred, and a physical layer circuit 20 for directly driving these packets on the IEEE 1394 serial bus BS. It is composed of an interface circuit, a cycle timer reset every 125 μs, a cycle monitor and a CRC circuit. Further, it performs a transmission process of computer data read from a hard disk (not shown) and generated by the transaction layer circuit 120 as a predetermined transmission packet. For example, a transaction controller 1 of a transaction layer circuit 120 described later
Upon receiving a notification that there is data to be sent from 26, the 1394 serial bus is arbitrated via the physical layer circuit 20 to secure the bus. In FIG. 1, the FIFO and the like of the isochronous communication system are omitted as described above.

The CPU interface circuit 102 includes a local processor 40, a transmission FIFO 103, and a reception FIFO 103.
It performs arbitration such as writing and reading of asynchronous communication packets with the IFO 104 and arbitration of transmission and reception of various data between the local processor 40 and the CR 107. For example, a host computer as an initiator transmits an IEEE 1394 interface bus BS, and transmits a command for controlling a hard disk as a storage device stored in a reception FIFO to the local processor 40.

From the local processor 40, data for activating the transaction layer circuit 120 for transmitting and receiving computer data is set in the CR 107 through the CPU interface 102 (ADPst).
= 1).

The transmission FIFO 103 includes IEEE13
Asynchronous communication packets to be transmitted to the N. 94 serial bus BS are stored.
Given to.

Further, the receiving FIFO 104 is an IEEE
Asynchronous communication packets transmitted through the 1394 serial bus BS, for example, commands for controlling a hard disk as a storage device and the like are stored by the classification circuit 105.

The discrimination circuit 105 has a transaction code tcode (Transaction) in the first quadred of the asynchronous communication packet via the link core 101.
code) and transaction label tl (Transaction
label), discriminates whether the packet is a response packet (Response Packet) from the initiator host computer to the target transaction layer circuit or other packets, and only the response packet is transferred to the transaction layer circuit. The packet is input to the circuit 120, and the other packets are stored in the reception FIFO 104.

The transaction label tl used for the sorting check is set to "a" in common, and t
In the code (Transaction code), different data is set for a write request (request) and response (Response), and for a read (Read) request (Read request) and response (Read Response). Specifically, tcode
Is set to "0" in the case of a quadlet write in a write request and "1" in the case of a block write.
"2" for a write response
Is set to It is set to "4" in the case of a quadlet read in a read request (Read request), and is set to "5" in the case of a block read (Block Read). In the case of a read response (Read Response), it is set to “6/7”.

The resolver 106 receives the self-I data transmitted through the IEEE 1394 serial interface bus BS.
The D packet is analyzed and stored in the CR 107. It also has functions such as error checking and counting the number of nodes.

The transaction layer circuit 120
It has a function of automatically transmitting and receiving data of a computer peripheral device (a hard disk in this embodiment) as an asynchronous packet based on the SBP-2 (Serial Bus Protocol-2) standard. Further, the transaction layer circuit 120 has a retry function and a split timeout detection function. The retry function is a function of retransmitting the corresponding request packet when an ack busy ^* Ack code is returned after transmitting the request packet. When retransmitting a packet, the 2-bit rt area in the first quadred of the transmission packet is set from “00” to “01”, and the core link 101 is notified and transmitted. The split timeout detection function is a function for detecting a timeout until a response packet is returned.

This transaction layer circuit 120
Is a transport data interface circuit 121,
Request packet generation circuit (SBPreq) 122, response packet decode circuit (SBPRsp) 123, request FIFO (Request F
IFO: ADPTF) 124, Response FIFO (Response FIFO: ADP)
RF) 125, and the transaction controller 12
6. Then, the request packet generation circuit 122, the response packet decode circuit 123, the request F
A data processing circuit AD is provided by the I / O 124, the response FIFO 125, and the transaction controller 126.
P is configured.

The transport data interface circuit 121 arbitrates the transmission and reception of data between the HDD controller 30, the request packet generation circuit 122, and the response packet decode circuit 123.

The request packet generation circuit 122 has a link
Upon receiving a data transfer start instruction from the CR 107 of the layer circuit 100, in the case of transmission (write), the transport data interface circuit 1 according to the SBP-2 standard.
21 so that the computer data recorded on a hard disk (not shown) obtained through
The data is divided into a plurality of pieces of data, and the address of the SBP protocol is calculated based on the data such as the transfer data length set in the CR 107. The 1394 bus address and the transaction label tl (= a) and the transaction code tcode ( For example, a 1394 header made up of four cladlets in which, for example, 1 or 5) is set is stored in the request FIFO 124. In the case of reception (reading), CR1 is used in accordance with the SBP-2 standard.
07, the SBP protocol address is calculated based on the data such as the transfer data length, and the 1394 bus address and the transaction label tl (= a), the transaction code tcode (for example, 1 or 5), etc., which are increased for each packet, are calculated. Set and specified address,
1394 block read request command (B
lock read Request Command) is stored in the request FIFO 124 as one or more packets.

The request packet generating circuit 122 calculates the maximum data length of the response packet to the request packet to be transmitted upon receiving the maximum length data max-payload specified by the CR 107 during transmission and reception. This maximum data length (byte) maxpl is obtained based on the following equation.

[0042]

[Formula 1] maxpl = 2 ^{(max, Payload + 2)} (1)

The response packet decode circuit 123 reads the data stored in the first FIIFO 124 at the time of reception, removes the 1394 header, and transfers the data at a predetermined timing to the transport data interface circuit 12.
1 to the HDD controller 30.

The request FIFO 124 stores packetized transmission data when transmitting (writing), and stores a 1394 block read request command when receiving (reading). The request FIFO 12
When the data to be transmitted is stored, the signal 4 outputs an active signal EMT, for example, at a low level (“0”) indicating this to the transaction controller 126.

In the case of reception (reading), the response FIFO 125 stores reception data transmitted from the host computer via the 1394 serial bus BS. The response FIFO 125 sends a signal S125 indicating the remaining storage capacity to the transaction controller 12.
6 is output.

The transaction controller 126
The packetized transmission data stored in the request FIFO 124 at the time of transmission, and the request FIFO 12 at the time of reception.
4 controls the output of the 1394 block read request command (request packet) stored in No. 4 to the link core 101 of the link layer core circuit 100. Also, when sending,
Upon receiving a response packet from the classification circuit 105 of the link layer circuit 100, the retry code rcode is set to C
The response packet from the classification circuit 105 is stored in the response FIFO 125 upon reception.

The transaction controller 12
6 is an ack busy ^* ack after transmitting the request packet.
If the code is returned, has the retry function to retransmit the corresponding request packet, the retransmission when performing the the set after receiving Ackbusy ^* is a retransmission request time (e.g. cycle time 125μs After the elapse of an integral multiple of the time). When the packet is retransmitted, the 2-bit rt area in the first quadred of the transmission packet is set from “00” to “01”, and the core link 101 is notified and transmitted.

FIG. 2 is a block diagram showing a configuration example of a retry circuit for realizing the retry function. This retry circuit, as shown in FIG.
1, cycle counter (Cycle Counter) 1262, interval register (Retry IntervalCounter) 1263,
Retry limit register 1264, comparison circuit (Comp) 1265, 1266, busy counter (Busy Co.)
unter) 1267 and a busy number discrimination circuit 1268.

[0049] ack code discrimination 1261, if it is determined the ack busy ^* In response to the ack code, pulse signal S
1261 is output to the cycle counter 1262 and the busy number discrimination circuit 1268.

The cycle counter 1262 is activated upon receiving the pulse signal S1261, and is incremented every time 125 μs is counted. Interval register 12
The time 63 can be arbitrarily set from the time when the retransmission request is received to the time when the retry operation is performed.
It is set to an integral multiple of μs, for example, 1, 2,. In the retry limit register 1264, a value (for example, 15) for limiting the number of retries is set.

The comparison circuit 1265 includes a cycle counter 1
When the time of H.262 reaches the time set in the interval register 1263, a retransmission signal SR is generated and the request FIFO 1
24 and a busy counter 1267. When the value of busy counter 1267 reaches the value set in retry limit register 1264, comparison circuit 1266 outputs timeout signal TO to CR 107. Busy counter 12
67 counts the number of times the comparison circuit 1265 outputs the retransmission signal SR.

The busy number discrimination circuit 1268 counts the pulse signal S1261 based on the ack code discrimination 1261. When the count value reaches a preset number, the set time of the interval register 1263 is set to a longer time, for example, twice the initial value. Reset to. When a series of packet transmission / reception is completed, the cycle counter 1
262, interval register 1263, and retry limit register 1264 are initialized.

Here, the operation of the retry circuit shown in FIG. 2 will be described, and then the normal operation of transmitting and receiving computer data when transferring a packet determined by the SBP-2 standard will be described.

In the retry circuit, when a response packet to the request packet is sent,
The ck code is input to the ack code determination 1261.
In the ack code determination 1261, when ack busy ^* is determined based on the input ack code, the pulse signal S 126
1 is generated and output to the cycle counter 1262 and the busy number determination circuit 1268. Cycle counter 1
At 262, it is started upon receiving the pulse signal S1261, and 1
It is incremented every time 25 μs is counted. The value of the cycle counter 1262 is compared with the value of the comparison circuit 1265.
Is compared with the set time of the interval register 1263. As a result of the comparison, when the count value reaches the set time, a retransmission signal SR is generated and output to the request FIFO 124 and the busy counter 1267.

As a result, as shown in FIG.
The read pointer in the IFO 124 is returned to the head of the previous packet, and the packet for which the retry request has been issued is read again. And when resending the packet,
2-bit rt in the first quadred of the transmitted packet
The core link 101 is notified to set the area from “00” to “01”, and retransmission is performed.

The busy counter 1267 counts the number of times the retransmission signal SR is output by the comparison circuit 1265, and outputs the count value to the comparison circuit 1266. When the comparison circuit 1266 obtains a result indicating that the value of the busy counter 1267 has reached the value set in the retry limit register 1264, the timeout signal TO
7 is output. Thereby, the local processor 40
Stops the packet transmission operation.

In the busy count determination circuit 1268, the pulse signal S1 based on the ack code determination 1261 is used.
When the count value reaches a preset number, the set time of the interval register 1263 is reset to a longer time. When a series of packet transmission / reception is completed, the cycle counter 126
2. The values of the interval register 1263 and the retry limit register 1264 are initialized.

Next, a description will be given of a normal transmission and reception operation of computer data in the case of transferring a packet determined by the SBP-2 standard in the above configuration.

First, a transmission operation, that is, a case where data is transferred from a target hard disk to a host computer which is an initiator and an operation of writing data from a storage device (hard disk) to a memory of the host computer is performed will be described. I do.

An O based on the SBP-2 standard transmitted from the host computer via the 1394 serial bus BS.
Packet data such as RB (Operation Request Block) is transmitted to the physical layer circuit 20 and the link layer circuit 10
0 is input to the classification circuit 105 via the link core 101 of 0.

The classification circuit 105 receives the received packet and receives a response packet (Response) from the host computer to the target transaction layer circuit.
Packet) or other packets. In this case, the received data is stored in the receiving FIFO 104 because it is another packet.
The reception data such as the ORB stored in the reception FIFO 104 is input to the local processor 40 via the CPU interface circuit 102. Local processor 4
At 0, OR is output via the CPU interface circuit 102.
According to the contents of B, the register for the transaction layer circuit of the CR 107 is initialized. As a result, the transaction layer circuit 120 is activated.

In the activated transaction layer circuit 120, the request packet generation circuit 122 starts requesting data to the HDD controller 30 via the transport interface 121. The transmission data transmitted via the transport interface 121 in response to the request is transmitted to the request packet generation circuit 1.
At 22, the computer data recorded on the hard disk (not shown) obtained via the transport data interface circuit 121 in accordance with the SBP-2 standard is divided into one or more data so as to be divided into packets.
The address of the SBP protocol is calculated based on the data such as the transfer data length set in the CR 107, and the 1394 bus address which increases for each packet, the transaction label tl (= a), and the transaction code tco
1394 header consisting of four cladlets in which de (for example, 1 or 5) is set,
It is stored in O124.

One 1394 is stored in one FIFO for request 124.
When data equal to or larger than the packet size is stored, the data is sent to the link core 101 of the link layer circuit 100 by the transaction controller 126. The link core 101 arbitrates the 1394 serial bus BS via the physical layer circuit 20. As a result, if a bus can be acquired, a write request packet (Write Request Packet) including transfer data is sent to the physical layer circuit 2.
0, transmitted to the host computer via the 1394 serial bus BS.

After the transmission, an Ack code for the write request packet and a write response packet (Write Response Packet) are transmitted from the host computer, and the physical layer circuit 20 and the link core 101 of the link layer circuit 100 are transmitted. Classification circuit 10 via
5 is input.

In the classification circuit 105, the transaction code tcode and the transaction label tl of the received packet are checked, and the target transaction layer circuit 12 is sent from the host computer.
If the response packet is determined to be a response packet (Response Packet) for the
Transaction controller 12 of layer circuit 120
6 is input.

In the transaction controller 126, if the Ack code and the response code (Response code) of the input response packet are normal, the next data is transmitted to the link core 101. By repeating the above operation, the operation of writing (transmitting) the computer data to the memory of the host computer is performed.

FIG. 4 shows an outline of the operation of the transaction layer circuit 120 for the above transmission.

Next, a description will be given of a receiving operation, that is, a case where data is transferred from the host computer to the target, in which the storage device (hard disk) performs an operation of reading data from the memory of the host computer.

An O based on the SBP-2 standard transmitted from the host computer via the 1394 serial bus BS.
Packet data such as RB is a physical layer circuit 2
0, which is input to the classification circuit 105 via the link core 101 of the link layer circuit 100.

Upon receiving the received packet, the classification circuit 105 receives a response packet (Response) from the host computer to the target transaction layer circuit.
Packet) or other packets. In this case, the received data is stored in the receiving FIFO 104 because it is another packet.
The reception data such as the ORB stored in the reception FIFO 104 is input to the local processor 40 via the CPU interface circuit 102. Local processor 4
At 0, OR is output via the CPU interface circuit 102.
According to the contents of B, the register for the transaction layer circuit of the CR 107 is initialized. As a result, the transaction layer circuit 120 is activated.

In the activated transaction layer circuit 120, the request packet generation circuit 122
According to the BP-2 standard, the address of the SBP protocol is calculated based on the data such as the transfer data length set in the CR 107, and the 1394 bus address which increases for each packet, the transaction label tl (= a), and the transaction code tcode (for example, 1 or 5) is set, and 139 of the specified address and data length are set.
4 block read request command (Block readRequest C
ommand) is packetized and stored in the request FIFO 124.

The read request command packet stored in the request FIFO 124 is sent by the transaction controller 126 to the link core 101 of the link layer circuit 100. The link core 101 arbitrates the 1394 serial bus BS via the physical layer circuit 20.
As a result, if the bus is acquired, a read request packet (Read Request Packet) is transmitted to the host computer via the physical layer circuit 20 and the 1394 serial bus BS.

After transmission, an Ack code for a read request packet from the host computer and a read response packet (Read R) including data of the designated data length are read.
esponse Packet) is sent to the physical layer circuit 20 and the link core 10 of the link layer circuit 100.
The signal is input to the classification circuit 105 through the line 1.

In the sorting circuit 105, the transaction code tcode and the transaction label tl of the received packet are checked, and it is determined that the received packet is a response packet (Response Packet) from the host computer to the target transaction layer circuit. Then, the response packet is input to the transaction controller 126 of the transaction layer circuit 120.

In the transaction controller 126, the response packet from the classification circuit 105 is
It is stored in O125. The data stored in the response FIFO 125 is read by the response packet decoding circuit 123, the 1394 header is removed, and the data is output to the HDD controller 30 via the transport data interface circuit 121 at a predetermined timing.
By repeating the above operation, the operation of writing (receiving) the computer data to the storage device (hard disk) is performed.

FIG. 5 schematically shows the operation of the transaction layer circuit 129 relating to the above reception.

As described above, according to the first embodiment, a storage device is connected, data of the storage device is read, a self-designated transaction label is added to the serial interface bus BS as a transmission asynchronous packet. When transmitting and transferring the data of the other node to the storage device, a request packet with a self-designated label is generated and transmitted to the serial interface bus BS, and a response packet to the request packet from the other node is received. And a transaction as a data processing circuit for extracting a data portion from the response packet and transferring the data portion to the storage device.
Since the layer circuit 120 is provided, the large-capacity data stored in or read from the storage device can be converted into an IE conforming to the SBP-2 standard.
EE1394 packets can be transmitted and received.
Large-capacity data transfer can be realized by using asynchronous packets of the IEEE 1394 serial bus interface. And O based on the SBP-2 standard.
Sequences such as RB fetch, data transfer, and status transmission to the initiator can be simplified, and an optimum design can be made when data of a computer peripheral device such as a disk driver and a tape streamer is connected to the IEEE 1394 serial bus.

Also, an interval register 1263 that can arbitrarily set the time from when a retransmission request is received to when a retry operation is performed, a cycle counter 1262 that starts and measures time when ack busy ^* is received, a cycle counter 1262 time interval register 1263
, A comparison circuit 1265 that generates a retransmission signal SR, a retry limit register 1264 that can set the number of retries to be restricted, and a busy counter 1267 that counts the number of retransmission signal outputs of the comparison circuit 1265
And a comparison circuit 1266 that outputs a time-out signal TO when the value of the busy counter 1267 reaches the set value of the retry limit register 1264. When a request packet is transmitted, an ack busy ^* ack code is returned. When retransmitting the corresponding request packet, after the set time has passed after receiving the retransmission request ack busy ^* , the packet transmission operation should be stopped when the number of retries reaches the set number. Therefore, the retry operation can be automated, the addition of a control system circuit can be reduced, and the retry interval can be set arbitrarily, so that a smooth transmission / reception process according to the specification can be performed.

Further, the transaction layer circuit 1
20 is a request FIFO 124 and a response FIFO 12
5 as well as the transmission FIFO 103 and the reception FIFO 104 in the link layer circuit 100, the request FIFO 124 and the response FIFO 12
5, the transmission and reception of normal 1394 packets other than the data can be performed in parallel with the exchange of the data according to the fifth embodiment.

Further, the transaction code tcode (Transaction code) and the transaction label tl (Transaction label) in the first quadred of the asynchronous communication packet via the link core 101 are checked, and the target transaction is transmitted from the host computer as the initiator. Discriminating whether the packet is a response packet (Response Packet) to the layer circuit or another packet, input only the response packet to the transaction layer circuit 120, and store the other packet in the reception FIFO 104 Since the classification circuit 105 is provided, even if a fatal error occurs in the transaction layer circuit 120 and the data read / write operation is stopped, for example, the read command of the next input command of the data is read. Without becomes possible out, there is an advantage that the reception of the no command regardless of the data read / write status can be smoothly performed.

[0081]

As described above, according to the present invention,
The retry operation can be automated, the addition of a control circuit can be reduced, large-capacity data can be transmitted and received as packets conforming to a predetermined standard, and smooth transmission / reception processing can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an IEEE 1394 serial interface circuit according to the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a retry circuit according to the present invention.

FIG. 3 is a diagram for explaining a re-read operation of a FIFO during a retry operation;

FIG. 4 is a diagram schematically illustrating a transmission operation in the transaction layer circuit according to the present invention.

FIG. 5 is a diagram schematically illustrating a receiving operation in the transaction layer circuit according to the present invention.

FIG. 6 is a diagram for explaining asynchronous transfer of the IEEE 1394 standard.

[Explanation of symbols]

10 link / transaction layer integrated circuit, 20
... Physical layer circuit, 30 ... HDD controller, 40 ... Local processor, 100, 100a ... Link layer circuit, 101 ... Link core, 102 ... CP
U interface circuit, 103: Asynchronous transmission FIFO, 104: Asynchronous reception FIFO, 1
05, 105a: Classification circuit, 106: Resolver, 107
... Control register, 120 ... Transaction
Layer circuit, 121: transport data interface circuit, 121: request packet generation circuit, 123: response packet decoding circuit, 124: request FIFO, 1
25 ... Response FIFO, 126 ... Transaction controller, 1261 ... ACK code discrimination, 1262 ... Cycle counter (Cycle Counter), 1263 ... Retry Interval Counter, 1264 ... Retry limit register (Retry Limit) register, 1265, 126
6 ... Comparator (Comp), 1267 ... Busy counter (Busy)
Counter), 1268: Busy number discrimination circuit.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H04L 12/56 H04L 11/20 102Z

Claims (20)

[Claims] 1. A serial interface circuit for transmitting and receiving a packet between a self-node and another node connected via a serial interface bus, comprising: generating a request packet from the self-node to another node; A first data processing circuit for transmitting the request packet to the serial interface bus when the response packet to the request packet is received, and the received response packet requests retransmission of the request packet. Second retry operation to send
And a data processing circuit. 2. The serial interface circuit according to claim 1, wherein the second data processing circuit retransmits the request packet after a lapse of a set time after receiving the retransmission request. 3. The second data processing circuit includes: an interval register capable of arbitrarily setting a time period from when a retransmission request is received to when a retry operation is performed; 3. A serial circuit according to claim 2, further comprising: a cycle counter that performs a retry operation when the time of the cycle counter reaches a set time of the interval register, and a retry operation when the retransmission signal is generated. Interface circuit. 4. The serial interface circuit according to claim 3, further comprising a discriminating circuit for discriminating the number of retransmissions and resetting the set time of said interval register to a longer time when the count value reaches a preset number. 5. The serial interface circuit according to claim 1, further comprising a limiting circuit for limiting the number of retry operations. 6. The serial interface circuit according to claim 2, further comprising a limiting circuit for limiting the number of retry operations. 7. The serial interface circuit according to claim 3, further comprising a limiting circuit for limiting the number of times of said retry operation. 8. The serial interface circuit according to claim 4, further comprising a limiting circuit for limiting the number of retry operations. 9. A retry limit register capable of setting the number of times of retry to be limited, a retransmission counter for counting the number of retransmission signal outputs of the comparison circuit, and a value of the retransmission counter being a value of the retry limit register. 8. The serial interface circuit according to claim 7, further comprising: a comparison circuit that outputs a timeout signal when a set value is reached; and a control circuit that receives the timeout signal and stops transmitting the request packet. 10. A retry limit register capable of setting the number of retry times to be limited, a retransmission counter for counting the number of retransmission signal outputs of the comparison circuit, and a value of the retransmission counter value of the retry limit register. 9. The serial interface circuit according to claim 8, further comprising: a comparison circuit that outputs a timeout signal when a set value is reached; and a control circuit that receives the timeout signal and stops transmitting the request packet. 11. A serial interface circuit for transmitting and receiving packets between another node connected to the own node via a serial interface bus, comprising: a storage unit; and a request packet for generating a request packet from the own node to another node. A request packet generation circuit for storing the request packet stored in the storage means, a first data processing circuit for transmitting the request packet stored in the storage means to the serial interface bus, a response packet for the request packet, and a received response packet And a second data processing circuit for performing a retry operation of retransmitting the request packet stored in the storage means to the serial interface bus when requesting retransmission of the request packet. 12. The serial interface circuit according to claim 11, wherein said second data processing circuit retransmits said request packet after a lapse of a set time after receiving a retransmission request. 13. The second data processing circuit includes: an interval register capable of arbitrarily setting a time period from when a retransmission request is received to when a retry operation is performed; And a comparison circuit for generating a retransmission signal when the time of the cycle counter reaches the set time of the interval register. When the retransmission signal is generated, the request packet stored in the storage unit is read. 13. The serial interface circuit according to claim 12, wherein the retry operation is performed by using the serial interface. 14. The serial interface circuit according to claim 13, further comprising a discriminating circuit for discriminating the number of times of retransmission and resetting the set time of said interval register to a longer time when the count value reaches a preset number. 15. The serial interface circuit according to claim 11, further comprising a limiting circuit for limiting the number of retry operations. 16. The serial interface circuit according to claim 12, further comprising a limiting circuit for limiting the number of times of said retry operation. 17. The serial interface circuit according to claim 13, further comprising a limiting circuit for limiting the number of times of said retry operation. 18. The serial interface circuit according to claim 14, further comprising a limiting circuit for limiting the number of times of said retry operation. 19. A retry limit register capable of setting a retry count to be restricted, a retransmission counter for counting the number of retransmission signal outputs of the comparison circuit, and a value of the retransmission counter being a value of the retry limit register. 18. The serial interface circuit according to claim 17, comprising: a comparison circuit that outputs a timeout signal when the set value is reached; and a control circuit that receives the timeout signal and stops transmitting the request packet. 20. A retry limit register capable of setting a retry count to be limited, a retransmission counter for counting the number of retransmission signal outputs of the comparison circuit, and a value of the retransmission counter being a value of the retry limit register. 19. The serial interface circuit according to claim 18, further comprising: a comparison circuit that outputs a timeout signal when a set value is reached; and a control circuit that receives the timeout signal and stops transmitting the request packet.