JPH1116966A - Pad arrangement method of one-chip microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pad arrangement method for enabling rationalization of a measuring method, wherein a plurality of chips can be simultaneously measured, in a measuring method of one-chip microcomputers. SOLUTION: In a pad arrangement method of a one-chip microcomputer containing a nonvolatile memory constituted of an erasable EEPROM (flash memory) as a program memory, pads 33A for a nonvolatile storage device 32 are arranged on two facing edges, and pads 33B for microcomputers 31 are arranged on the other two facing edges. Thereby a plurality of chips can be measured simultaneously.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a one-chip microcomputer having a built-in nonvolatile memory and, more particularly, to a technique related to a pad arrangement method in the microcomputer.

[0002]

2. Description of the Related Art When looking at recent one-chip microcomputers, there is an increasing tendency to incorporate an EEPROM (flash memory) instead of a mask ROM as a nonvolatile memory for storing program data. this is,
This is because the EEPROM has features not found in the mask ROM. For example, when the function of a one-chip microcomputer is changed, if a mask ROM is used, a new mask must be designed and manufactured. Therefore, there is a problem that a development cost is increased and a development period is lengthened. On the other hand, if the EEPROM is used, new program data can be written using a PROM writer or the like after the old program data is electrically erased, so that the development cost can be reduced and the development period can be shortened.

FIG. 6 is a diagram showing a structure of a cell portion (for example, 2 bits) of an EEPROM having the above characteristics. 6, reference numerals 1 and 2 denote Ms with floating gates.
OS transistor. The MOS transistor 1,
Numerals 2 each correspond to a 1-bit cell, the gate is connected to the word lines WL1 and WL2, the drain is commonly connected to the bit line BL, and the source is commonly connected to the source line SL (always 0 volt). 3 is a sense amplifier, which compares a reference current with a current of the bit line BL,
It outputs a logical value "1" or "0".

For example, a control voltage V is applied to the word line WL1.
When H (for example, 4 volts) is applied, a cell current flows through the MOS transistor 1 and the current of the bit line BL becomes larger than the reference current, so that the logical value “1” is output from the sense amplifier 3. On the other hand, when the control voltage VH is applied to the word line WL1, if the MOS transistor 1 is in the programmed state, the transistor is turned off, and no cell current flows through the MOS transistor 1, and the current of the bit line BL becomes smaller than the reference current. , Sense amplifier 3 outputs a logical value "0". Note that MOS transistor 2
Operates similarly. That is, if the selected MOS transistors 1 and 2 are in the erased state, each bit value is a logical value “1”.
When the MOS transistors 1 and 2 are in the programmed state, the EEPR is set so that each bit value becomes a logical value “0”.
The OM is configured.

The technology relating to the one-chip microcomputer described above is disclosed in Japanese Patent Application No. 9-55 filed earlier by the present applicant.
No. 169, for example. Less than,
The pad arrangement of the one-chip microcomputer will be described with reference to FIG. FIG. 7 is a diagram showing the layout of the one-chip microcomputer. Reference numeral 5 denotes a core circuit block on the microcomputer side, and reference numeral 6 denotes a core circuit block on the nonvolatile memory (EEPROM and mask ROM). A large number of pads 7 are arranged on four sides of a peripheral portion surrounding the core circuit block 5 on the microcomputer side and the core circuit block 6 on the nonvolatile memory. Each of the pads 7 has a nonvolatile memory terminal and Microcomputer terminals are randomly arranged.

A description will now be given of a wafer check by an LSI tester in the above-described one-chip microcomputer shipment inspection. Since the wafer check process is performed by a conventionally well-known procedure, it will be briefly described. First, first
In the measurement step, data of the nonvolatile memory is determined using a logic tester. Subsequently, after passing through a baking step for a data retention acceleration test, in a second measurement step, a logic tester is used to determine the data retention state of the above-described nonvolatile memory and to determine the function of the microcomputer. Was.

[0007]

SUMMARY OF THE INVENTION
When a non-volatile memory is determined by using a logic tester in the first measurement step as described above when a wafer is checked by an SI tester, there is a memory-specific measurement. Was very long. Further, when the determination is performed using only the memory tester, there is a problem that complicated measurement unique to the microcomputer cannot be performed.

Therefore, at the expense of shortening the measurement time, the first and second measurement steps have been performed by the logic tester. Further, as shown in FIG. 7, the terminals for the nonvolatile memory and the terminals for the microcomputer are randomly arranged on the pads in four directions, respectively, so that a plurality of chips cannot be measured at the same time. That is, as shown in FIG. 8, the pad 7 to which the nonvolatile memory terminal is connected is connected.
Is represented by, for example, a pad 7A, since the pads 7A are randomly arranged on pads in four directions, it is necessary to make the needles 8A of the probe card correspond to the pads 7A arranged in four directions. , Only one chip could be measured, a plurality of chips could not be measured at the same time, and the measurement time could not be reduced.

Accordingly, the present invention provides a pad arranging method for realizing a rationalization of a measuring method capable of simultaneously measuring a plurality of chips in a measuring method of a one-chip microcomputer.

[0010]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional drawbacks, and has been made in view of the above-mentioned problems. In this, a plurality of chips can be measured simultaneously by arranging pads for nonvolatile memory on two opposing sides and arranging pads for a microcomputer on the other two opposing sides.

Further, in order to perform a retention test of data programmed in the nonvolatile memory, when performing two wafer checks, in the first measurement step, data determination in the nonvolatile memory is performed using a memory tester. After the baking step for the retention acceleration test, in the second measurement step, the data in the nonvolatile memory is determined using a logic tester as in the related art, and the function of the microcomputer is determined. By using a memory tester instead of the logic tester used in the conventional first measurement process, the total measurement time can be reduced.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a general one-chip microcomputer incorporating a nonvolatile memory to which the present invention is applied will be described with reference to the drawings. First, FIG.
Replaces the ROM of the microcomputer with the non-volatile memory (E
EPROM), and the EEPROM 11 includes a program area 1 as shown in FIG.
2, composed of a data area 13 and a control circuit 14,
Reference numeral 5 denotes a core unit including, for example, a CPU, an I / O port, and the like.

FIG. 2 shows a plurality of independent EEPROMs 17 and 1 compared to the one-chip microcomputer shown in FIG.
8, the first EEPROM 17 has a program area 19 and a control circuit 20, and has a second EEPROM 17.
The PROM 18 has a configuration including a data area 21 and a control circuit 22, and 23 is a core unit. FIG. 3 further includes an EEPROM 24 as a first nonvolatile memory and a mask ROM 25 as a second nonvolatile memory. The EEPROM 24 has a first program area 26,
With the configuration having the data area 27 and the control circuit 28, the mask ROM 25 becomes the second program area 29
0 is a core part.

In the mask ROM 25, the EEPR
A data rewriting program of the OM 24 is stored. In the mask ROM 25, only a data rewriting program of the EEPROM 24 required by all users is mounted, and rewriting by the users is disabled. Hereinafter, the pad arrangement method of the present invention applied to the above-described one-chip microcomputer will be described with reference to the drawings.

FIG. 4 is a diagram showing a layout of a one-chip microcomputer according to the present invention, wherein 31 is a core circuit block on the microcomputer side, and 32 is a core circuit block on the nonvolatile memory side. The nonvolatile memory included in the core circuit block 32 on the nonvolatile memory side includes the above-described EEPROM 11 (see FIG. 1), the first and second EEPROMs 17 and 18 (see FIG. 2), and the first nonvolatile memory. An EEPROM 24 as a memory and a mask ROM 25 as a second nonvolatile memory (see FIG. 3). A large number of pads 33 are arranged on four sides of a peripheral portion surrounding the core circuit block 31 on the microcomputer side and the core circuit block 32 on the non-volatile memory side.

A feature of the pad arrangement method of the present invention resides in the pads 33 arranged on four sides of the peripheral portion surrounding the core circuit block 31 on the microcomputer side and the core circuit block 32 on the non-volatile memory side. Pads 33A arranged on two opposite sides are pads for nonvolatile memory terminals, and pads 33B arranged on the other two opposite sides are pads for microcomputer terminals.

As described above, in the present invention, the pad 33A for the non-volatile memory terminal and the pad 33B for the microcomputer terminal are separately arranged on two opposing sides. As described above, in the present invention, the pads 33A for the non-volatile memory terminals and the pads 33B for the microcomputer terminals are arranged on the two opposite sides, respectively, so that a plurality of chips are arranged side by side as shown in FIG. Measurement can be performed, and the measurement time per chip can be reduced. Reference numeral 34 denotes a window of the probe card, and reference numeral 35 denotes a needle of the probe card, from which signals are exchanged with the LSI tester. Therefore,
Simultaneous measurement is possible up to the allowable size depending on the size of the window 34 of the probe card described above (FIG. 5 shows a state of simultaneous measurement of data in the nonvolatile memory by a memory tester (not shown) for two chips. ing.).

A description will now be given of a wafer check by an LSI tester in the above-described one-chip microcomputer shipment inspection. First, in a first measurement step, data determination of a nonvolatile memory is performed using a memory tester. continue,
After passing through the baking step for the data retention acceleration test, in the second measurement step, the data retention of the above-described nonvolatile memory is determined using a logic tester, and the function of the microcomputer is determined.

As described above, in order to perform a retention test of data written in the nonvolatile memory, when performing two wafer checks, in the first measurement step, the memory tester is used as shown in FIG. The data of the non-volatile memory is determined by using a logic tester (not shown) in the second measurement step after the baking step for the retention acceleration test. By performing the function determination of the microcomputer, the total measurement time can be reduced by using a memory tester dedicated to a memory instead of the logic tester used in the first measurement step in the related art. Note that the chip shown in FIG.
A plurality of chips can be measured at the same time by performing measurement in a state rotated by degrees.

[0020]

As described above, according to the present invention, 1
Simultaneous measurement of multiple chips is possible by arranging pads for nonvolatile memory on two opposing sides and arranging pads for microcomputers on the other two opposing sides in the chip microcomputer pad arrangement method Thus, the measurement time per chip can be shortened.

Further, in order to perform a retention test of data written in the nonvolatile memory, when performing two wafer checks, in the first measurement step, the data of the nonvolatile memory is determined using a memory tester. After the baking step for the retention acceleration test, in the second measurement step, data in the nonvolatile memory is determined using a logic tester as in the related art, and the function of the microcomputer is determined. In addition, the use of a memory tester instead of the logic tester used in the conventional first measurement process, and the simultaneous measurement of a plurality of chips can be performed, so that the total measurement time can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a general one-chip microcomputer to which the present invention is applied.

FIG. 2 is a diagram showing a general one-chip microcomputer to which the present invention is applied.

FIG. 3 is a diagram showing a general one-chip microcomputer to which the present invention is applied.

FIG. 4 is a diagram showing a pad layout of the one-chip microcomputer according to one embodiment of the present invention;

FIG. 5 is a diagram showing a wafer check state of the one-chip microcomputer of one embodiment of the present invention.

FIG. 6 is a diagram showing a structure of an EEPROM applied to a conventional one-chip microcomputer.

FIG. 7 is a diagram showing a pad layout of a conventional one-chip microcomputer.

FIG. 8 is a diagram showing a wafer check state of a conventional one-chip microcomputer.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H01L 27/04 G01R 31/28 V 21/822 H01L 27/04 E 27/115 27/10 434 27/10 461 (72) Invention Katsumi Tatekawa 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd.

Claims (3)

[Claims] 1. A pad arrangement method for a one-chip microcomputer having a built-in nonvolatile memory, wherein pads for a nonvolatile memory are arranged on two opposite sides, and pads for a microcomputer are arranged on the other two opposite sides. A pad arrangement method for a one-chip microcomputer, comprising: 2. A pad arrangement method for a one-chip microcomputer having a rewritable nonvolatile memory as a program memory, wherein pads for the nonvolatile memory are arranged on two opposing sides, and the other opposing two pads are arranged. A pad arrangement method for a one-chip microcomputer, wherein a pad for a microcomputer is arranged on a side. 3. The device according to claim 1, wherein the nonvolatile memory is an EEPROM.
A pad arrangement method for a chip microcomputer.