JPH11168172A - Manufacture of semiconductor chip, three-dimensional structure using semiconductor chip thereof, manufacture thereof and electrical connection thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a three-dimensional structure using a semiconductor chip by a method wherein at least one or more of projected parts are formed on the outer periphery of the chip substrate of the chip, and the projected parts are inserted in recess parts, which are individually formed dividedly in a base substrate for fixing the chip on the base substrate. SOLUTION: A light-emitting element, a light-receiving element, a mirror, a lens, a microscopic electro-mechanical structure and the like are formed on a semiconductor chip 19. Projected parts 18, consisting of a martial constituting a substrate of the chip 19, are formed on the outer periphery of the chip 19, and the number of the parts 18 can be one or a plurality. The wholes of the parts 18 are formed in a form, which is gradually tapered toward the points thereof. Thereby, the parts 18 are enabled to insert smoothly in recessed parts 21, and openings 22, which are formed in a base substrate 20 and are individually divided, are made insartable in accurate positions. Especially, at the time of the insertion of the parts 18, the parts 18 are prevented from being broken and a three-dimensional structure 23 can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor chip such as a micromachine component formed using a semiconductor substrate, a three-dimensional structure using the semiconductor chip, a method of manufacturing the same, and an electrical connection method thereof.

[0002]

2. Description of the Related Art At present, micro machines or MEMS
Research on micromachines called (Micro Electro Mechnical Systems) has been earnestly researched and developed around the world.
Such micromachines have been realized as micromachines (motors and the like) by applying semiconductor microfabrication technology, and have come to attract attention at once. Micromachines using semiconductor processes (etching and lithography), as typified by MEMS, generally do not require assembly or adjustment, and can realize a system integrated with electronic circuits and sensors on a single substrate. It is said that However, it is very difficult to integrate circuits and micromachines on the same substrate, and as a device actually realized, the micromechanical structure is simple and made of a material suitable for the semiconductor process for making circuits. Only very limited devices such as possible automotive pressure sensors, acceleration sensors and the like. Further, it is more difficult to integrate components made of different semiconductor materials, for example, a laser made of GaAs and a circuit made of silicon on the same substrate. Must be used. The structure of a MEMS utilizing a semiconductor process is generally 3
Since it is far from a three-dimensional structure, a method of creating a three-dimensional micromechanical structure has been researched and developed at present.

[0003] In such a situation, in particular, a method of creating a three-dimensional MEMS structure has attracted much attention at present. Typical examples of this are [IE
EE PHOTONICS TECHNOLOGY LETTERS, VOL.6, NO.12, DECEMB
ER 1994] "Micro-Machined Three-Di
This is a method in which a part is lifted and erected using a hinge structure created by a surface micromachining method such as "mensional Micro-Optical System". In this method, when creating a three-dimensional structure of paper without cutting and pasting, create a development view of the three-dimensional structure on paper, cut it into that shape, then bend the joint part of each surface and create a three-dimensional structure Is the same. However, since the material is a fragile material such as polycrystalline silicon and cannot be bent like paper, a hinge, that is, a hinge structure is formed at a bent portion, and the material can be freely bent to some extent. FIG. 32 shows a conventional structure in which minute components are simply erected. This is called `` Micro-Machined Three-Dimensional Micro-Optic
al System ", which is a three-dimensional structure in which a Fresnel lens, which is a minute component, stands almost perpendicular to the substrate surface. Although not described in detail, all the thin plate structures are formed on the sacrificial layer on the surface of the substrate 1 in a planar manner.
Thereafter, the sacrificial layer under the thin film structure is removed by etching to form a Fresnel lens plate (made of polysilicon) 3 on which the Fresnel lens 2 floating from the substrate surface is formed.
The Fresnel lens plate 3 is erected substantially vertically using a hinge (hinge) 4 structure provided at the connection between the substrate and the substrate (silicon) 1. Thereafter, the stopper (Slide Latch) plates 5 on both sides similarly prepared are lifted and fall down to the Fresnel lens plate 3 side which is set up substantially vertically, so that the Fresnel lens plate is formed in the slit 6 formed in the stopper plate 5. 3
Is inserted and mechanically fixed. The role of the stopper plate 5 is to obtain a more accurate angle (in this case, an angle perpendicular to the surface of the substrate 1).

[0004] The above-mentioned conventional example relates to a three-dimensional structure from the viewpoint of a micromachine. Hereinafter, a three-dimensional structure of a semiconductor chip from the viewpoint of a semiconductor will be described. In order to reduce the cost of a computer and improve its performance (processing speed), it is desirable to mount as many electronic circuits as possible in the smallest possible area. A simple packing configuration is a semiconductor chip having a cubic structure,
This is to construct a three-dimensional structure, and various three-dimensional structures have been proposed. The most typical three-dimensional structure of a semiconductor chip will be described below.

FIG. 33A shows a three-dimensional structure 8 of a semiconductor chip 7 disclosed in US Pat. No. 5,310,072. FIG.
3 (b) is a cross-sectional view taken along line 3-3 shown in FIG.
FIG. 33C shows a state before the semiconductor chip 7 is mounted.
Is a similar cross-sectional view, where the semiconductor chip 7 is mounted. In the three-dimensional structure 8 of the semiconductor chip 7 shown here, a continuous elongated recess 10 in which the semiconductor chip 7 is just fitted is formed in a base substrate 9 made of silicon. It is formed by inserting one end portion. This recess 10
Is formed by anisotropic etching of a silicon (110) substrate. Here, an electric wiring 11, an electric terminal 12 as a three-dimensional structure, and an electric terminal 13 for electric connection with the semiconductor chip 7 are formed on the base substrate 9 made of silicon. Electric terminal 13 of semiconductor chip 7
Are formed so that, when the semiconductor chip 7 is inserted into the concave portion 10, it comes to the same position as the wiring terminals 14 provided on the base substrate 9. The semiconductor chip 7 is inserted into the recess 10 of the base substrate 9, and the wiring terminals 14 formed on the base substrate 9 and the semiconductor chip terminals 15 are soldered 16
Thus, a three-dimensional structure 8 electrically connected to the semiconductor chip 7 is formed. The connection between the terminals by the solder 16 is performed in a reflow process.

[0006]

In the conventional structure shown in FIG. 32, a flat Fresnel lens plate 3 corresponding to an exploded view of a three-dimensional structure formed two-dimensionally is usually made of polycrystalline silicon. The thickness is several microns, and the thickness of lenses, mirrors, etc. is several hundred microns, which is much larger than the thickness. Such a structure is generally made by using a planar micromachining technique. In this case, the sacrificial layer is removed by etching, and the Fresnel lens plate 3 is floated from the base substrate 1. However, at this time, sticking (the thin Fresnel lens plate 3 adheres to the surface of the substrate 1 due to the surface tension of the etching solution or the like) becomes a serious problem, and the production yield is reduced, or sticking is prevented. It has problems such as the need for complicated processes. In addition, since a polycrystalline silicon thin film is used, there is a large problem that the Fresnel lens 2, the hinge 4, and the like are distorted by internal stress of the polycrystalline silicon itself.

On the other hand, in the known example shown in FIG.
In the method in which the semiconductor chip 7 is inserted into the continuous recesses (by anisotropic etching of silicon and mechanical processing) 10 provided on the base substrate 9 and the semiconductor chip 7 is easily erected, the semiconductor chip 7 easily falls down. Handling is a major issue. Since the semiconductor chip 7 falls down even with a slight vibration, the movement to the next step or the contents of the next step must be made to have almost no vibration.

[0008]

According to the first aspect of the present invention,
This chip substrate is formed around a semiconductor chip formed by dividing a semiconductor substrate on which a plurality of electric circuits, electronic circuits, light emitting elements, light receiving elements, mirrors, lenses, micro-electro-mechanical structures and the like are formed individually. At least one or more projections are formed, and the semiconductor chips are fixed to the base substrate by inserting the projections into recesses or openings formed by dividing the base substrate individually. Therefore,
A three-dimensional structure made of semiconductor chips can be manufactured very easily and with a very high density and a minimum volume.

According to a second aspect of the present invention, when a large number of semiconductor chips having a convex portion are taken from a semiconductor substrate, the convex portions of the semiconductor chips are arranged alternately with facing each other. Therefore, a large number of semiconductor chips can be obtained from one semiconductor substrate.

According to a third aspect of the present invention, the material of the semiconductor substrate is single crystal silicon. Therefore, fine processing of the projection can be easily performed.

According to a fourth aspect of the present invention, when the semiconductor chip having the convex portion is individually divided from the semiconductor substrate, the semiconductor chip is fixed to the semiconductor substrate by at least one beam. Therefore, the individual semiconductor chips do not fall apart when the projections are formed.

According to a fifth aspect of the present invention, at least a divided surface of the semiconductor chip is subjected to insulation treatment in a state where the individual semiconductor chips are fixed to the semiconductor substrate by beams. Therefore, electrical connection is possible even with a semiconductor chip having only a convex portion formed thereon, but the insulating treatment necessary for more reliable connection is completely connected to the substrate by a beam even after the convex portion is formed. Since the process is performed in the state, the process can be simplified.

According to a sixth aspect of the present invention, the semiconductor chip is divided into individual semiconductor chips by folding beams. Therefore, since the individual chips are divided by folding the beam in a state where the individual chips are fixed, an adhesive tape or the like is not required.

According to a seventh aspect of the present invention, the shape of the individually divided concave portions and openings formed in the base substrate is expanded near the substrate surface on the side where the convex portion of the semiconductor chip is inserted. Therefore, the smooth insertion of the projection is made possible.

According to an eighth aspect of the present invention, the shape of each of the divided holes formed in the base substrate is expanded near the back surface of the base substrate. Therefore, the fixing force of the semiconductor chip can be improved.

According to a ninth aspect of the present invention, the individually divided concave portions and openings formed in the base substrate are formed to have a shape that elastically expands when the semiconductor chip convex portion is inserted. Therefore, it is possible to smoothly insert the convex portion and to fix the semiconductor chip in a stable state.

In a tenth aspect of the present invention, the base substrate is made of silicon. Therefore, an electric / electronic circuit or the like can be formed on the substrate itself, and further, minute concave portions and openings can be easily formed.

According to the eleventh aspect of the present invention, the shape of the bottom of each of the divided recesses formed in the base substrate is expanded. Therefore, by forming a protrusion at the tip of the projection, the fixing force of the semiconductor chip can be improved.

In the twelfth aspect of the present invention, the recessed portion or the opening of the opening formed in the base substrate is formed by using anisotropic etching of single crystal silicon. Therefore, the step of forming the enlarged portion can be simplified.

According to a thirteenth aspect of the present invention, there is provided a semiconductor chip substrate comprising: a convex portion on an outer periphery of the semiconductor chip substrate;
ICP-RIE (Inductiv
elycoupled plasma-Reactive ion etching) method was used. Therefore, fine processing can be performed, and substantially vertical side wall processing can be performed.

According to a fourteenth aspect of the present invention, the projection of the semiconductor chip is inserted into the recess or the opening of the base substrate in a state where the edge of the semiconductor chip is spaced from the substrate surface of the base substrate. Therefore, when making an electrical connection using solder,
It is possible to prevent the occurrence of electrical failure due to a solder bridge or the like.

According to a fifteenth aspect of the present invention, a protrusion is formed on the convex portion of the semiconductor chip, and the protrusion is engaged with an enlarged portion formed on the back surface of the base substrate or on the bottom of the individually divided concave portion. did. Therefore, the fixing force of the semiconductor chip can be improved.

According to a sixteenth aspect of the present invention, the electrode provided near the convex portion of the semiconductor chip is electrically connected to the electrode provided near the concave portion or opening of the base substrate. Therefore, the mechanical and electrical connection between the semiconductor chip and the substrate can be easily and finely made.

According to a seventeenth aspect of the present invention, an electrode is provided on a surface of a convex portion of a semiconductor chip, and an electrode is provided on an inner wall of a recess or an opening which is separated from each other on a base substrate, so that electrical contact is obtained only by mechanical contact. Added connection. Therefore, the electrical connection between the semiconductor chip and the substrate can be made very easily.

According to the present invention, an electric / electronic inspection of a semiconductor chip mounted on a base substrate is performed in a state where a projection of the semiconductor chip is simply inserted into a concave portion or an opening of the base substrate. did. Therefore, when the semiconductor chip is defective, replacement can be easily performed.

According to a nineteenth aspect of the present invention, the base substrate
An opening for heat dissipation was formed in addition to the individually divided openings for inserting the protrusions of the semiconductor chip. Therefore, even if the semiconductor chips are integrated, high heat dissipation can be provided, and there is no adverse thermal effect.

According to a twentieth aspect of the present invention, a semiconductor substrate on which a plurality of electric circuits, electronic circuits, light emitting elements, light receiving elements, mirrors, lenses, micro-electro-mechanical structures, etc. are formed is divided into individual parts. At least one or more protrusions made of the chip substrate are formed on the outer periphery of a chip substrate of a semiconductor chip, and the protrusions are inserted into recesses or openings formed by dividing the base substrate individually. The semiconductor chip is fixed to the semiconductor chip, electrodes are provided in the vicinity of the protrusions of the semiconductor chip, the electrodes are provided in the vicinity of the recesses or openings of the base substrate, and these electrodes are connected to each other to form a three-dimensional structure of the semiconductor chip. Is formed.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. First, FIG.
7 shows a three-dimensional structure 23 manufactured by a method of inserting a semiconductor chip 19 having a convex portion 18 on the outer circumference of the base 7 into an individually divided concave portion 21 or an opening 22 formed in a base substrate 20. Here, means for creating a structure similar to the three-dimensional structure of the micromachine having the Fresnel lens set up in the conventional example will be described.

FIG. 1A shows members constituting the three-dimensional structure 23. That is, the base substrate 20 having the individually separated concave portions 21 or the openings 22,
A semiconductor chip 19 in which a convex portion 18 is formed on the outer periphery of a chip substrate 17 and a Fresnel lens 24 is formed is shown. FIG. 1B shows a projection 18 using these components.
Is a three-dimensional structure 23 created by a method of inserting the hole into the recess 21 or the opening 22. FIG. 1 (c)
It is sectional drawing cut | disconnected by CC 'shown in (b), and has shown the state before the semiconductor chip 19 is inserted. As can be seen from this figure, the projection 18 formed on the semiconductor chip 19 is inserted into the recess 21 or the opening 22 formed on the base substrate 20 so that the three-dimensional structure 2 is formed.
3 is created. This figure shows that the protrusions 18 of the semiconductor chip 19 are all inserted into the recesses 21 and the openings 22. The concave portion 21 and the opening 22 provided on the base substrate 20 are individually divided according to the size and pitch of the convex portion 18 and are formed independently. The material of the semiconductor chip 19 is silicon or a compound semiconductor, and the material of the base substrate 20 may be ceramic, glass, plastic, or the like in addition to the semiconductor similar to the chip.

The Fresnel lens 24 in the present embodiment
2 is shown in FIG. 2 and the method of preparation will be described below. As the semiconductor substrate 25, a silicon oxide film (SiO ₂ ) is formed on a 4-inch diameter single crystal silicon wafer (100).
(2 μm), single crystal silicon (3 μm) formed S
An OI (Silicon on insulator) substrate was used. First, a silicon nitride film (SiNx) is formed on the back surface of the semiconductor substrate 25.
Of low pressure chemical vapor depositi
on), and chromium (Cr) is formed on the surface by sputtering to a thickness of 0.5 μm. Thereafter, the SiNx of the silicon substrate portion corresponding to the opening of the Fresnel lens 24 is formed.
Is removed by a photolithography process, and silicon on the substrate is removed by anisotropic etching using an aqueous solution of potassium hydroxide (KOH) using SiNx as a mask. Thereafter, a chromium layer is formed in a pattern of the Fresnel lens 24 by a photolithography process. Then, using this Cr pattern as a mask, the single crystal silicon (3 μm) is converted into an RI using sulfur hexafluoride (SF6) gas.
E removes by etching until it reaches the SiO ₂ layer. The ring portion and the gap were each 3 μm. Through such a process, a ring through which light can pass is formed, and the Fresnel lens 24 is obtained. As is clear from this figure,
Fresnel lens 24 is mounted on a 4 inch diameter SOI substrate,
Many are formed. This many formed Fresnel lens 2
As described later, the semiconductor chip 4 is individually divided (by ICP-RIE) so as to have a convex portion 18 as an outer shape of the semiconductor chip 19, and the divided semiconductor chip (Fresnel lens) 19 is used as a base. A three-dimensional structure (Fresnel lens stands upright with respect to the base substrate) 23 equivalent to that shown in the known example 23 by being inserted into the concave portion 21 or the opening 22 formed in the substrate 20.
Can be formed. In the present embodiment, the thickness of the semiconductor substrate 25 is 200 μm (total thickness),
The protrusion 18 had a width of 100 μm and a pitch of 200 μm, and the length (projection) of the protrusion 18 was 200 μm. Semiconductor chip 19 on which Fresnel lens 24 is formed
Had a width of 3000 μm and a height of 2000 μm. Similarly, the base substrate 20 is a single-crystal silicon wafer having a diameter of 4 inches, and the thickness of the base substrate 20 is 200 μm and 400 μm.
Silicon was removed by etching to a depth of 200 μm by CP-RIE. That is, the base substrate 20 having a thickness of 200 μm
In this case, an opening 22 is formed, and a 400 μm thick base substrate 20 is formed.
Thus, the recess 21 is formed. The dimensions of the opening 22 and the recess 21 were formed to be 10 μm larger than the cross section of the projection 18 of the semiconductor chip 19, so that they had a 110 × 210 μm square shape.
The base substrate 20 has an outer shape of 5000 × 500
As in the case of the semiconductor chip 19, a large number of chips formed on a substrate were individually divided to form a base substrate 20. The division of the base substrate 20 was performed using a normal dicing apparatus.

Next, a semiconductor chip 19 for forming the three-dimensional structure 23 of the present embodiment will be described. FIG.
Shows the shape of the semiconductor chip 19 for the three-dimensional structure 23 of the present invention. Although not shown in the figure, the semiconductor chip 19 has an electric / electronic circuit, a light emitting element, a light receiving element, a mirror, a lens, a fine electro-mechanical structure, and the like formed on the surface thereof. Generally, the semiconductor chip 19
Although an LSI, a light emitting element, a light receiving element, and the like are known, in the present embodiment, an ME including a mirror, a lens, or a mechanical element formed on a semiconductor material substrate is used.
MS and the like are also included.

As is apparent from the drawing, a major feature of the present embodiment is that a projection 18 made of the substrate material is formed on the outer periphery of the semiconductor chip 19 (the thickness is the same as that of the chip). Although the figure shows the case where five protrusions 18 are formed at the lower end of the semiconductor chip 19, the protrusions may be formed at the left and right ends, the upper end, or the corners as long as the outer periphery of the semiconductor chip 19 is provided. Further, the number of the convex portions 18 to be formed may be one or plural. Further, the shape is not limited to the rectangular shape shown in FIG. What is shown in FIG.
A representative example of the protrusion 18 formed on the semiconductor chip 19 is shown. FIG. 4A shows a shape in which the entirety of the projection 18 gradually tapers toward the tip, and FIG. 4B shows a shape in which only the vicinity of the tip of the projection 18 gradually tapers toward the tip. ,
FIG. 4C shows a shape in which only the vicinity of the distal end of the convex portion 18 is tapered with a curvature toward the distal end. FIG. 4 (d)
The overall shape of the convex portion 18 is a shape in which a wide rectangular shape and a narrow rectangular shape are combined, and only the vicinity of the distal end portion of the convex portion 18 is tapered with a curvature toward the distal end portion. Further, the shapes may be a combination of these shapes, and are not limited to these shapes.
When the three-dimensional structure 23 of the semiconductor chip 19 to be described later is formed, the tapered shape of the convex portion 18 is used to form an individually divided concave portion 21 and an open hole 22 formed on the base substrate 20.
In addition, it is possible to smoothly insert the projection 18. Since the tapered portion at the tip is smaller than the opening of the recess 21 and the opening 22, even if the positioning of the projection 18 and the recess 21 / the opening 22 is rough, if only the tip is inserted, the projection is the rest. 18
The tip shape is easily inserted, and inserted at an accurate position. In addition, the convex portion 18 and the concave portion 2
Even if the play of the first part is made small (the clearance between each other is very small), it is possible to easily insert the same for the above-mentioned reason, that is, to prevent the breakage of the convex part 18 particularly at the time of insertion, and to realize a three-dimensional structure. The manufacturing yield of the body 23 can be greatly improved, and a three-dimensional structure 23 having very good dimensional accuracy and high mechanical bonding strength can be formed.

FIG. 5 shows the shape of a typical convex portion 18 in which a slit 26 is formed in the convex portion 18. In FIG. 5A, one slit 26 is formed at the center up to the base of the projection 18. In FIG. 5B, one slit 26 is located at the center of the convex portion 18 and formed halfway through the convex portion 18.
In FIG. 5C, one slit 26 is formed at the center of the convex portion 18, passes through the base of the convex portion 18, and penetrates into the semiconductor chip 19. FIG. 5 (d) shows that the projection 18 is formed at the center and at the bases on both sides of the projection 18 until it enters the semiconductor chip 19. In FIG. 5E, two slits 26 are formed in the protrusion 18 up to the base of the protrusion 18. In this figure, the whole shape of the convex portion 18 is shown as a quadrangle, but there is no problem even if the shape has the shape shown in FIG. In addition, the shape of the slit 26 and the number of the slits 26, the slit 2
The length of 6 is not limited to the shape shown in FIG. By adopting the slit structure as shown here, the breakage of the convex portion 18 is prevented when the convex portion 18 is inserted into the individually separated concave portion 21 and opening 22. When the projection 18 is inserted, the individually divided projections 18 bend toward the slit 26 side, so when the clearance is small, for example,
By this action, breakage of the projection 18 can be greatly reduced. Further, the entire shape of the convex portion 18 is changed to the concave portion 21 and the opening 2
By making it slightly larger than the shape of 2, the mechanical joining strength can be further increased. Slit 2
In particular, as shown in FIG. 5C, the shape of the slit 6 is such that the slit 26 is smaller than the base of the projection 18 in the semiconductor chip 19.
The shape extending to the inside of the semiconductor substrate 25 is desirable. However, since it is impossible to form an electric / electronic circuit in the portion of the slit 26, the electric / electronic circuit in the semiconductor substrate 25 is not formed.
The substrate area available for electronic circuits is reduced, albeit slightly.

FIG. 6 is a sectional view showing the slit
And a structure in which projections 27 are provided at the ends of both ends of the convex portion 18. In FIG. 6A, the projection 18 has a rectangular shape, and a triangular projection 27 is formed at the left and right ends of the projection 18 provided with the slit 26 at the center. In FIG. 6B, a protrusion having a curvature is formed at the tip of the similar projection 27. The shape of the protrusion, the entire shape of the projection 18, or the shape and length of the slit 26 are not limited to the shapes shown in FIG. However, FIG.
(a) In the case of the entire shape of the convex portion 18 shown in (b), that is, in the case of a rectangular shape, the amount of protrusion at the tip portion is equivalent to the sum of the amounts of both protrusions being equal to the width of the slit 26. Or rather, it is desirable to make it smaller. This protrusion is formed at the bottom of a concave portion 21 formed in a base substrate 20 described later,
Alternatively, the semiconductor chip 19 is engaged with the enlarged portion on the back surface side of the opening 22 to prevent the semiconductor chip 19 from easily falling off. It is desirable that the shape of the engagement portion of the projecting portion is substantially equal to the angle of the widening.

FIG. 7 shows a shape in which a radius is formed at the base of the convex portion 18 formed on the semiconductor chip 19. FIG.
3A, a radius is formed at the roots of both ends of a simple rectangular projection 18. FIG. 7 (b) shows a case in which the center of the rectangular projection 18 extends into the semiconductor substrate 25 of the semiconductor chip 19.
Roots at both ends of the convex portion 18 having the slits 26,
A radius was formed at the base of the slit 26. The size of the radius (radius of curvature and the like), the overall shape of the convex portion 18, and the like are not limited to the shapes shown in FIG.

FIG. 8 shows a structure in which the protruding portion 18 formed on the semiconductor chip 19 is provided with a saw-toothed jaw 28 which is expanded toward the base. The knurls 28 are formed for the purpose of smooth insertion into the recess 21 and the opening 22 and to make it difficult for the semiconductor chip 19 to come off. The shape of the jagged teeth 28 and the overall shape of the projections 18 are not limited to the shapes shown in FIG.

FIG. 9 shows a structure in the thickness direction of the semiconductor chip 19, which is different from the structure in the plane direction described above. As is clear from the figure, the protrusion 18 is thinner than the thickness of the semiconductor chip 19. By reducing the cross-sectional area of the concave portion 21 or the convex portion 18 inserted into the opening 22, the cross-sectional area of the concave portion 21 and the opening 22 is reduced, and the wiring density of a circuit formed on the base substrate 20 is improved. This makes it possible to configure the three-dimensional structure 23 with higher density. Further, by providing a step of the thickness in the middle of the convex portion 18, it becomes possible to regulate the insertion stop position, similarly to the shape shown in FIG. The position, shape, and the like of the step portion are not limited to the shapes shown in FIG.

FIG. 10 shows a state in which a semiconductor chip 19 having a projection 18 is cut out from a semiconductor substrate 25.
If the entire outer periphery of the semiconductor chip 19 is etched from the semiconductor substrate 25 made of a semiconductor material wafer in accordance with the shape of the semiconductor chip 19, the semiconductor chip 19 itself is separated from the wafer, so that the etched semiconductor chip 19 is fixed to the wafer. This shows a structure in which a beam 29 is provided.
FIG. 11 shows a semiconductor chip 1 having a projection 18.
9 is a schematic diagram in which a number 9 is formed on a plurality of wafers. Since the actual shape of the semiconductor chip 19 is approximately several thousand microns square,
The beam 29 may be very thin. Further, not only one place but also a plurality of places may be provided. The shape of the beam 29 is not limited to the rectangular shape shown here. However, it is desirable that the portion where the beam 29 is provided is provided in a portion that does not obstruct the three-dimensional structure, that is, in the present embodiment, on a side having no convex portion 18. This is achieved by folding the beam 29, as will be described below.
This is because unevenness occurs in the portion where the beam 29 was present because 9 is separated from the wafer.

FIG. 12 shows that, when a large number of semiconductor chips 19 having the convex portions 18 are taken from the wafer, simply arranging the chips reduces the number of chips by the amount of the convex portions 18. 18 shows a structure in which 18 are faced and staggered. By doing so, the number of semiconductor chips 19 that can be obtained from a wafer having a predetermined area can be increased. FIG. 13 is a schematic diagram when a plurality of semiconductor chips 19 are formed on a wafer.

A method of separating a semiconductor chip 19 having a plurality of protrusions 18 from a wafer on which a plurality of semiconductor chips 19 have been formed as described above will be described. For ease of explanation,
It is assumed that a large number of circuits (Fresnel lenses in the above embodiment) and the like are already formed on the semiconductor material wafer. It is assumed that the layout of the semiconductor chips 19 on the wafer has a layout as shown in FIG. The semiconductor wafer material is silicon.

A photoresist is applied to a semiconductor wafer on which circuits and the like are formed, and after baking the photoresist, the shape of the semiconductor chip 19 having the convex portion 18 is drawn (of course, the portion of the beam 29 is also drawn). Exposure and development are performed using a glass mask. Thereafter, the photoresist is baked, and the outer shape of the chip is etched away by the thickness of the semiconductor substrate 25 using the photoresist as a mask. As an etching method, a dry etching process using a fluorine-based gas (RIE: reactive ion
tching) is applied. As a typical method of this process, the temperature of the substrate is cooled to about -100 degrees, and the verticality of the etching wall is improved.
Cracking of the photoresist causes a problem, and it is preferable to use a metal mask.) Or ICP-RIE (inductively coupled plasma reactant) which enables highly anisotropic etching by room temperature, low vacuum, and high density plasma.
ive ion etching) equipment. If the thickness of the semiconductor chip 19 (corresponding to the thickness of the wafer) is 100 microns or less, cryo-etch can be used as such, but if it is several hundred microns, it is desirable to use an ICP-RIE apparatus. In this experiment, a high-density plasma ICP-RIE device was used. When this apparatus is used, a silicon etching rate of 2 μm / min or more, a selectivity with respect to a photoresist mask of 75 or more can be obtained, and an extremely high verticality of a side wall can be obtained. In this experiment, the back surface of a silicon wafer on which circuits and the like were formed was polished to 200 μm, and then etched by the above method. Under this experimental condition, it took about 90 minutes (about 2.2 μm / min) to etch 200 microns. The etched surface was almost perpendicular to the substrate surface. The various shapes described above could also be created with very high accuracy. Since the semiconductor chips 19 arranged on the wafer are fixed to the wafer in a structure having individual beams 29, the removal of the photoresist after the etching is performed not by individual chip units but by one chip. The operation was easy because it could be processed as a single wafer. After the work is completed, the work can be divided into individual semiconductor chips 19 by folding the beam 29. This also greatly facilitates the work.

FIG. 14 shows a structure in which an enlarged portion 30 is formed in the concave portion 21 or the open hole 22 formed in the base substrate 20 in the vicinity of the surface where the convex portion 18 is inserted. FIG. 14A shows a case where the expanding portion 30 is formed in the concave portion 21, and FIG.
5 shows a case where the enlarged portion 30 is formed in the opening 22. By forming such an expanded portion 30, the initial insertion of the convex portion 18 of the semiconductor chip 19 into the concave portion 21 or the opening 22 can be performed very smoothly. The expanding portion 30 serves as a guide for the convex portion 18. When the three-dimensional structure 23 is manufactured, the convex portions 18 and the concave portions 21
Alternatively, even if the position of the opening 22 is misaligned (if it is within the widening portion 30), it is guided along the slope of the widening portion 30. The enlarged portion 30 can be formed by etching. However, when silicon, particularly a (100) wafer, is used for the base substrate 20, a KOH aqueous solution, desirably, compatibility with a circuit (less impurity contamination).
From the point of performing anisotropic etching using an alkali solution such as tetramethyl ammonium hydrate aqueous solution,
The work is easy, and the above-described enlarged portion 30 can be easily obtained due to the characteristics of the anisotropic etching. In the manufacturing process, first, the enlarged portion 30 is formed by anisotropic etching, and then the concave portion 21 or the opening 22 is formed by ICP-RIE.

FIG. 15 shows a structure in which an enlarged portion 31 is provided at the bottom of the concave portion 21 and near the back surface side of the base substrate 20 in the opening 22. As shown in FIG. 15A, in order to form the enlarged portion 31 at the bottom of the concave portion 21, first, the concave portion 21 is formed by ICP-RIE.
Are formed, and the side wall and the bottom of the concave portion 21 and the base substrate 20
Of silicon nitride (SiNx) etc. on the surface of
ical vapor deposition), and thereafter, only the silicon nitride film (SiNx) at the bottom of the concave portion 21 is subjected to ICP.
-Etching removal by RIE. Thereafter, the base substrate 20 on which the concave portions 21 are formed is immersed in an alkaline liquid such as a KOH aqueous solution, and wet etching is performed only on the bottom. By doing so, the rhombus-shaped expanding portion 31 as shown in the figure is obtained.
Can be formed. This shape can also be circular. Then, the silicon nitride film (SiNx) formed on the side wall is removed to form the concave portion 21. As shown in FIG. 15B, the enlarged portion 31 near the back surface of the base substrate 20 at the portion of the opening 22 can be easily formed by using anisotropic etching of silicon as described above. The enlarged portion 31 is provided when the circuit or the like is not formed on the back surface of the base substrate 20 as shown in FIG.
As shown in FIG.
In this case, even if the material thickness of the base substrate is increased, the thickness of the opening to be etched by ICP-RIE is reduced, so that the mechanical strength of the base substrate 20 is increased and the etching time is greatly reduced. I do.

FIG. 16 shows a state in which the projection 18 is inserted into the recess 21 or the opening 22 formed in the base substrate 20.
The structure of the recess 21 and the opening 22 having a so-called elastic flexible structure in which the insertion opening 32 is expanded is shown. In this case, since the area occupied by the concave portion 21 and the opening 22 increases, the area in which an electric / electronic circuit or the like formed on the base substrate 20 can be reduced, but the convex portion is formed because the insertion port 32 has a flexible structure. The insertion of the projection 18 can be easily performed, and the mechanical coupling strength can be increased by making the projection 18 slightly larger than the insertion opening 32. The shape is not limited to the shape shown here, and other shapes have no problem. This is a so-called spring structure utilizing the elasticity of the material of the base substrate 20 itself. As described above, the opening 22 can be manufactured by etching in such a shape by ICP-RIE. In the case of the recess 21, however, a sacrifice layer 33 as shown in FIG. Requires an intermediate film such as ₂ . In this case, as the base substrate 20, a silicon wafer with SiO ₂ and a silicon wafer are bonded by using a method such as anodic bonding, and an electric / electronic circuit or the like is formed on the upper Si portion. After this, the ICP-RIE device
The recess 21 is removed by etching until reaching the SiO ₂ layer as an intermediate layer. In this state, the support portion 34 is not movable because it is bonded to SiO ₂ . Therefore, the SiO ₂ of the sacrifice layer 33 serving as the adhesive layer is removed by etching.
The support portion 34 made of silicon is set in a floating state. With such a method, the support portion 34 is floated above the base substrate 20, and the support portion 34 has a spring structure.

FIG. 17 shows a structure in which the protrusions 18 formed on the semiconductor chip 19 are not completely inserted. Although the drawing shows a structure in which a mere rectangular protrusion 18 is partially inserted into the recess 21, the shape of the protrusion 18 having a two-stage structure shown in FIG.

FIG. 18 shows an enlarged portion 35 formed near the back surface of the opening 22 of the base substrate 20 on the substrate surface.
The protrusion 36 formed at the tip of the projection 18 of the opening 9
2 shows a situation in which the second engaging portion 35 is engaged. FIG. 18A shows a state before insertion, and FIG. 18B shows a state after insertion. As can be seen from this figure, it is desirable that the protrusion 36 of the convex portion 18 formed on the semiconductor chip 19 has a shape (especially an angle) that matches the shape of the enlarged portion 35. In this drawing, since the enlarged portion 35 on the back surface is formed by anisotropic etching of silicon (100), the angle of the enlarged portion 35 is 54.7 degrees. 35.7 degrees would be ideal. In this figure, the opening 22 is shown, but the present invention can be similarly applied to a case where an enlarged portion is provided near the bottom of the recess 21. In this figure, the shape by anisotropic etching is shown, but by the ICP-RIE, the shape of the enlarged portion 35 is rectangular (etched from the back surface to halfway, and then a smaller opening is formed from the front surface). Is also good. In this case, the angle of the protrusion 36 is 90 degrees.

FIG. 19 shows a structure in which three-dimensional structures 23 formed by the above-described base substrate 20 and semiconductor chip 19 are stacked. The semiconductor chips 19 are erected substantially perpendicular to the base substrate 20 and parallel to each other. A concave portion 21 is formed on the upper and lower surfaces of the intermediate base substrate 20, respectively. In this figure, the concave portions 2 formed on both surfaces are shown.
1 are formed at the same position, but they may be alternated or may be the opening 22.
By stacking in this manner, it is possible to integrate the semiconductor chips 19 at a higher density.

FIG. 20 shows a guide chip 37 provided with a projection 18 which fits into the above-mentioned not-shown recess 21 or opening 22 formed on the base substrate 20 similarly to the semiconductor chip 19.
3 shows an example of a three-dimensional structure 23 formed by using the method shown in FIG. In other words, the semiconductor chip 19 has a structure in which the semiconductor chip 19 is set upright on the base substrate 20, and the projections 18, the recesses 21, and the openings 22 are formed with very high accuracy, so that the positional accuracy is very good. In particular, in the case of optical use, for example, a reflection mirror of laser light, this perpendicularity is a very important advantage. In such a case, as can be seen from the figure, a guide tip 37 having a slit 38 is used to further increase the accuracy of the angle. Here, only one side of the guide tip 3
Although the structure using 7 is shown, it may be used on both sides. This is effective not only for improving the positional accuracy but also for further preventing the semiconductor chip 19 from falling down and improving the strength of the structure.

In the three-dimensional structure 23 shown in FIG. 21, two semiconductor chips 19 are provided in parallel on a base substrate 20 at a predetermined interval, and a slit 39 is formed at the upper edge of these semiconductor chips 19 to form a three-dimensional structure. Stopper 4 on slit 39
0 is inserted and reinforced.

A three-dimensional structure 23 shown in FIG. 22 has a structure in which one semiconductor chip 19 is erected on a base substrate 20 and a stopper 41 is cut out from the base substrate 20 to fix the semiconductor chip 19. It is.

The three-dimensional structure 23 shown in FIG. 23 is an example using a 45-degree reflecting mirror often used for optical use as the semiconductor chip 19. In this case, a notch 43 is provided in a part of a triangular guide chip 42 having an angle of 45 degrees (having a convex portion and inserted into a concave portion or opening of the base substrate), and a portion of the notch 43 is provided. The semiconductor chip 19 (mirror chip) having the convex portion 44 was inserted into the substrate to form a 45-degree reflecting mirror. Here is notch 4
Although one number 3 is provided, it is preferable to provide a plurality of the number 3 in order to increase the angle accuracy. With this method, it is possible to create the three-dimensional structure 23 having a desired angle.

FIG. 24 shows a three-dimensional structure 23 of another type. Semiconductor chip 1 on base substrate 20
9 is vertically set, and another semiconductor chip 19 is further vertically set on the semiconductor chip 19. The semiconductor chip 19 erected on the base substrate 20 also has the role of the base substrate 20 of another semiconductor chip 19.

In the above-described example, the semiconductor chip 19 is formed by inserting the convex portions 18 formed on the semiconductor chip 19 into individually separated concave portions 21 and openings 22 formed on the base substrate 20. Although it has been described that the three-dimensional structure 23 can be formed, if the bonding strength of the three-dimensional structure 23 is not sufficient just by inserting the projection 18, the bonding part, that is, the insertion part, may be formed of an adhesive or the like. It is desirable to fix by plating or the like.

FIG. 25 shows a method of electrically connecting the three-dimensional structure 23 by the semiconductor chip 19. FIG.
(a) shows a semiconductor chip 19 having a convex portion 18 in a concave portion 21 or an opening 22 provided in a base substrate 20 on which an electric wiring 45 whose end also functions as an electrode is formed.
This shows a state before the insertion of the acceleration sensor 46 (for example, in which the acceleration sensor 46 is formed). On the base substrate 20,
An electronic circuit 47 such as a C-F converter for detecting the output of the acceleration sensor 46 and the like is formed. The electric wiring 45 connected to the electronic circuit 47 includes the individually divided concave portion 21 and opening 22. Is connected to a terminal (shown as a wiring in the figure) of an electric wiring 45 on the base substrate 20 formed in the vicinity of. In the present embodiment, electric terminals are provided only on the surface of base substrate 20 (recess 21, opening 2).
In the semiconductor chip 19 on which the acceleration sensor 46 is formed, the semiconductor chip 19 on which the acceleration sensor 46 is formed has a suitable height (when the base is completely inserted) near the protrusion 18. A chip terminal (terminal for electrical connection) 48 that functions as an electrode is formed at a position (located near the substrate 20). In the present embodiment, each of the separated recesses 21 or the openings 22
Thus, as is clear from the drawing, the electric wiring 45 (CF converter: connected to the capacitance-frequency conversion circuit) from the back semiconductor chip 19 is connected to the projection 18 of the front semiconductor chip 19. It can be wired through. That is, the recess 21 and the opening 22 which are individually divided
Therefore, a portion where a hole is not formed (dented) can be left in the base substrate 20, and such electric wiring can be performed. In a known example in which a plurality of semiconductor chips 19 are arranged side by side, the semiconductor chip 1
9 is impossible, so that only wiring parallel to the semiconductor chip 19 can be performed. Therefore, wiring between the complicated semiconductor chips 19 is impossible. The gap between the semiconductor chips 19 must be increased (because the number of wirings parallel to the semiconductor chip 19 increases), the area of the base substrate 20 increases, and the volume of the three-dimensional structure 23 increases.
Further, since the wiring length is long, it is difficult to increase the speed of the three-dimensional semiconductor 23. Such a large problem can be solved by the structure shown in FIG. Although not shown in this figure, an insulating film is formed on the wiring except for the terminal portion.

A method for manufacturing base substrate 20 in the present embodiment will be briefly described. Concave portion 21 of base substrate 20,
The opening 22 was formed in the same manner as described above. However, the silicon wafer used in this case is a silicon wafer on which an electronic circuit such as a CF converter has already been formed at a specific location by an IC process. On this wafer, FIG.
The electric circuit 45 and the wiring terminals (there is no electrode film in the portion where the concave portion 21 and the opening 22 are formed and the inside is donut-shaped) shown in FIG.
7, and an insulating film is formed on the electric wiring 45 except for the wiring terminal portion. An ICP-RI is placed at a specific location (in the wiring terminal) of this wafer.
Using E, a concave portion 21 and an opening 22 were formed. A photoresist was used as a mask. The wafer for the base substrate 20 manufactured in this manner is divided individually into the base substrate 20.

FIG. 25B shows that the semiconductor chip 19 having the convex portion 18 on which the acceleration sensor 46 is formed is mounted on the electronic circuit 4.
7 (C-F converter), the electric wiring 45, and the state of being inserted into the individually divided concave portion 21 and opening 22 of the base substrate 20 on which the terminals for electric connection are formed. Although not shown in detail here, after the insertion, the electric terminals of the semiconductor chip 19 and the wiring terminals of the base substrate 20 are electrically connected with solder or a conductive adhesive.

FIG. 26A is an enlarged view of the acceleration sensor 46 according to the present embodiment. The creation method will be described below. As the semiconductor substrate 25, a single-crystal silicon wafer having a diameter of 4 inches is used, and first, 0.5 μm of SiNx and 1 μm of SiO ₂ are formed on the upper surface by low pressure CVD. Next, openings for the spring portion 50 for fixing the weight 49 of the acceleration sensor 46, the fixing portion 52 (anchor) of the comb electrode 51, the on-chip wiring 53, and the terminal pad 54 serving as an electrode are formed of SiO _2. Is formed by etching. Next, similarly, 2 μm of n-type polycrystalline silicon (having a high conductivity) is formed by low-pressure CVD and heat treatment is performed to greatly reduce the internal stress of the polycrystalline silicon. Thereafter, electrodes for the on-chip wiring 53 and the terminal pad 54 are formed, and patterning is performed into wiring and pad shapes. Thereafter, the polycrystalline silicon is removed by etching (using RIE) in the shape of the comb-tooth electrode 51, the weight 49, the spring portion 50, the on-chip wiring 53, and the terminal pad 54 by a photolithography process. Thereafter, similarly to the above-described embodiment, the semiconductor chip 19 is divided into individual semiconductor chips 19 each having a convex portion 18 (connected by a beam). Finally, a silicon oxide film (SiO ₂ ) serving as a sacrificial layer is removed by etching. By separating (bending the beam), as shown in FIG. 26B, an acceleration sensor having a structure in which the comb-tooth electrode 51, the weight 49, and the spring portion 50 are floated on the substrate is obtained.

Since the semiconductor chip 19 shown here is a chip in which only the mechanical element portion of the acceleration sensor 46 (the wiring portion is formed) is used, as described with reference to FIG. An electronic circuit 47 for detecting the output is required, that is, an electrical connection to another member is required. In the acceleration sensor 46, when the weight 49 moves to the left or right due to acceleration, the gap between the comb-tooth electrodes 51 changes, so that the capacitance changes. Therefore, a circuit for detecting the change in the capacitance is used. Is required. This circuit corresponds to the C-F shown in FIG.
It is an electronic circuit 47 using a converter.

FIG. 27 shows the sectional structure of FIG. FIG. 27A shows a state before insertion, and FIG. 27B shows a state after soldering after insertion. In the structure shown here, an electrical connection cannot be made only by inserting the convex portion 18, so that the electric terminals of the semiconductor chip 19 and the electrodes of the base substrate 20 are connected to each other by the solder 55 or a conductive adhesive. Wiring terminals 56 need to be electrically connected.
Although not shown in the figure, when the side wall and the back surface of the projection 18 of the semiconductor chip 19 are not insulated, it is desirable to insulate the inside (side wall, bottom) of the recess 21 and the opening 22. . That is, a short circuit between the semiconductor chip 19 and the base substrate 20 can be prevented, and when a conductive adhesive is used, for example, when a chemical penetrates into a slight gap of the insertion portion and the electric terminal and the substrate itself are short-circuited. Can be prevented. When soldering is used, a solder reflow process can be used.

FIG. 28 shows a case where the protrusion 18 formed on the semiconductor chip 19 is not completely inserted into the recess 21 or the opening 22. The electrical connection method and the like can be performed in the same manner as described above. In this case, when the soldering is performed in the reflow process, it is possible to greatly reduce the short circuit due to the solder bridge between the terminals. By forming the gap 57 between the edge of the semiconductor chip 19 and the base substrate 20, the formation of solder bridges can be greatly reduced. Here, the shape of the convex portion 18 is a simple quadrangle, and the gap 57 is formed by limiting the depth of the concave portion 21 (to a depth shallower than the protrusion of the convex portion 18). By using a convex shape having a step as shown in FIG. 4D, the gap 57 can be easily formed even in the case of the opening 22.

In FIG. 25 shown in this embodiment, two semiconductor chips 19 provided with the acceleration sensor 46 are inserted into the base substrate 20 (sensors having different measurement ranges). It can be inserted. Further, a different sensor chip such as a pressure sensor may be inserted. In this case, needless to say, an electronic circuit 47 for pressure detection needs to be formed on the base substrate 20. The electronic circuits 47 formed on the base substrate 20 do not need to be integrated in one place, and may be formed integrally in the vicinity of a plurality of electronic circuits as long as there are a plurality.

Further, instead of the acceleration sensor, a light receiving element having an electrode, a light receiving layer and the like may be used. Further, a light emitting element using a compound semiconductor as a semiconductor wafer material of a semiconductor chip and forming electrodes, a light emitting layer, and the like may be used. In these cases, a drive circuit for the light-receiving element, a drive circuit for the light-emitting element, or the like may be formed over the base substrate.

FIG. 29 shows a mechanical electrical connection. The electrical connection is made possible only by inserting the projection 18. The semiconductor chip 19 having the convex portions 18 is subjected to insulation treatment on all side walls (excluding the beam structure portion) with the insulating film 58. That is, the back surface and the entire sidewall of the etching region are formed at a low temperature by PCVD (plasma CVD) or the like.
An insulating film 58 such as O ₂ is formed. Terminal part 59 of convex part 18
Needless to say, is exposed. Base substrate 20
The insulating film 58 also insulates the concave portion 21 formed on the inside or the inner wall of the opening 22. PC as above
An insulating film 58 such as SiO ₂ is formed by VD or the like.
Thereafter, a terminal portion 60 serving as an electrode is formed on the inner wall or the bottom. With such a structure, the terminal portions 59, 60 formed in the convex portion 18, the concave portion 21, or the opening 22.
Have independent structures, and as shown in the figure, the electrical connection can be made mechanically only by inserting the projections 18. In this case, the electrodes of the terminal portions 59 and 60 formed are
A metal such as gold, on which a natural oxide film is unlikely to be formed, is desirable.
In this state (mechanical electrical connection), it is determined whether the inserted semiconductor chip 19 operates normally. If the inspection is performed in this state, if the chip is defective, the electrode on the base substrate 20 is less likely to be damaged because the chip may be simply pulled out. It is desirable that the electrode formed on the convex portion 18 is softer than the electrode formed on the inner wall of the concave portion 21 and the opening 22. Thereby, the concave portion 21 due to insertion / removal,
Breakage of the inner wall electrode of the opening 22 can be reduced. In this case, it can be dealt with by changing the method of forming the gold film.
The convex portion 18 is formed by a thin film such as sputtering or vapor deposition, and the concave portion 2 is formed.
1. The inner wall of the opening 22 is formed by plating.
Alternatively, a method such as changing the purity of gold may be used.

FIG. 30 shows an electrical connection using a mechanical + conductive material. Since the reliability of the connection is still insufficient with only the mechanical electrical connection described above, the connection is further fixed using a conductive material such as solder 55 or a plating process. By fixing the defective semiconductor chip 19 by reflow or the like after replacement, it is possible to manufacture the three-dimensional structure 23 in which the semiconductor chip 19 is electrically connected at a very high yield.

FIG. 31 shows the three-dimensional structure 23 of the semiconductor chip 19 in which the opening 6
1 shows the structure formed. The semiconductor chip 19 is assembled into a three-dimensional structure by inserting the protrusion 18 into the recess 21 or the opening 22 as described above.
When the semiconductor chips 19 are integrated at a high density, heat dissipation of each chip and the whole becomes very problematic. Therefore, an opening 61 is formed in an unnecessary portion of the base substrate 20 where the electric wiring 45 and the like are not formed. When the cooling medium is filled in the three-dimensional structure 23 by the opening 61, the opening 61 is formed. The presence of 61 makes it possible to efficiently circulate the refrigerant and greatly contributes to heat dissipation.

[0066]

According to the first aspect of the present invention, a semiconductor substrate on which a plurality of electric circuits, electronic circuits, light emitting elements, light receiving elements, mirrors, lenses, micro-electro-mechanical structures, etc. are formed is divided into individual parts. Forming at least one projection formed of the chip substrate on the outer periphery of the chip substrate of the semiconductor chip, and inserting the projection into a recess or opening formed by dividing the base substrate individually. Since the semiconductor chip is fixed to the base substrate, a three-dimensional structure using the semiconductor chip can be manufactured very easily and with a very high density and a minimum volume.

According to the second aspect of the present invention, when a large number of semiconductor chips having convex portions are taken from the semiconductor substrate, the convex portions of the semiconductor chips are arranged alternately so as to face each other. This has the effect that a large number of semiconductor chips can be obtained.

According to the third aspect of the present invention, since the material of the semiconductor substrate is single crystal silicon, there is an effect that fine processing of the projection can be easily performed.

According to a fourth aspect of the present invention, when the semiconductor chip having the convex portion is individually divided from the semiconductor substrate, the semiconductor chip is fixed to the semiconductor substrate by at least one beam. This has the effect that individual semiconductor chips do not fall apart when the projections are formed.

According to a fifth aspect of the present invention, at least a divisional surface of the semiconductor chip is subjected to insulation treatment in a state where the individual semiconductor chips are fixed to the semiconductor substrate by beams, so that only the protrusions are formed. Although electrical connection is possible even with a semiconductor chip, the insulation process required for more reliable connection is performed after all the parts are joined to the substrate by beams even after forming the convex part, This has the effect that the process can be simplified.

According to the sixth aspect of the present invention, since the beam provided on the semiconductor chip is divided into individual semiconductor chips by folding, the beam is folded by folding the beam in a state where the individual chips are fixed. Because I decided to cut the chip,
This has the effect of eliminating the need for an adhesive tape or the like.

According to the seventh aspect of the present invention, the shape of the individually divided concave portions and openings formed in the base substrate is expanded in the vicinity of the substrate surface on the side where the convex portion of the semiconductor chip is inserted. This has the effect that smooth insertion of the projections can be made possible.

According to the eighth aspect of the present invention, the shape of the individually divided openings formed in the base substrate is expanded near the back surface of the base substrate, so that the fixing force of the semiconductor chip is improved. It has the effect that it can be done.

According to the ninth aspect of the present invention, the individually divided recesses and openings formed in the base substrate are formed to have a shape which is elastically expanded when the semiconductor chip projection is inserted, so that the projection can be smoothly inserted. And the semiconductor chip can be fixed in a stable state.

According to the tenth aspect of the present invention, since the base substrate is made of silicon, an electric / electronic circuit or the like can be formed on the substrate itself, and fine concave portions and apertures can be easily formed. The effect is as follows.

According to the eleventh aspect of the present invention, the bottom shape of the individually divided concave portions formed on the base substrate is expanded, so that a protrusion is formed at the tip of the convex portion, so that the semiconductor chip of the semiconductor chip is formed. This has the effect that the fixing force can be improved.

According to the twelfth aspect of the present invention, the step of forming the enlarged portion is performed by forming the enlarged portion of the concave portion or the opening formed in the base substrate by using anisotropic etching of single crystal silicon. This has the effect of being able to simplify.

According to a thirteenth aspect of the present invention, there are provided a semiconductor chip substrate, a convex portion on the outer periphery, a concave portion individually divided on the base substrate,
ICP-RIE (Inductiv
Since the elycoupled plasma (reactive ion etching) method is used, it is possible to perform fine processing, and it is possible to perform substantially vertical side wall processing.

According to a fourteenth aspect of the present invention, since the convex portion of the semiconductor chip is inserted into the concave portion or the opening of the base substrate in a state where the edge portion of the semiconductor chip is spaced from the substrate surface of the base substrate, the solder is removed. When the used electrical connection is performed, there is an effect that occurrence of electrical failure due to a solder bridge or the like can be prevented.

According to a fifteenth aspect of the present invention, a protrusion is formed on a convex portion of a semiconductor chip, and the protrusion is engaged with an enlarged portion formed on the back surface of the base substrate or on the bottom of a separately divided concave portion. Therefore, there is an effect that the fixing force of the semiconductor chip can be improved.

According to the sixteenth aspect of the present invention, the electrode provided near the convex portion of the semiconductor chip is electrically connected to the electrode provided near the concave portion or opening of the base substrate. This has the effect that mechanical and electrical connection between the semiconductor chip and the substrate can be easily and finely made.

According to a seventeenth aspect of the present invention, an electrode is provided on a surface of a convex portion of a semiconductor chip, and an electrode is provided on an inner wall of a recessed portion or an opening of a base substrate, which is electrically separated only by mechanical contact. Since the connection is made, there is an effect that the electrical connection between the semiconductor chip and the substrate can be made very easily.

According to the eighteenth aspect of the present invention, the semiconductor chip mounted on the base substrate is subjected to an electric / electronic inspection in a state where the projection of the semiconductor chip is simply inserted into the recess or the opening of the base substrate. Therefore, there is an effect that replacement when a semiconductor chip is defective can be easily performed.

According to a nineteenth aspect of the present invention, the base substrate
Openings for heat dissipation are formed in addition to the individually divided openings for inserting the protrusions of the semiconductor chip, so even if the semiconductor chip is integrated, it can have high heat dissipation even if the semiconductor chip is integrated. Has the effect of not having any effect.

According to a twentieth aspect of the present invention, a semiconductor substrate on which a plurality of electric circuits, electronic circuits, light emitting elements, light receiving elements, mirrors, lenses, micro-electro-mechanical structures and the like are formed is divided into individual parts. At least one or more protrusions made of the chip substrate are formed on the outer periphery of a chip substrate of a semiconductor chip, and the protrusions are inserted into recesses or openings formed by dividing the base substrate individually. The semiconductor chip is fixed to the semiconductor chip, electrodes are provided in the vicinity of the protrusions of the semiconductor chip, the electrodes are provided in the vicinity of the recesses or openings of the base substrate, and these electrodes are connected to each other to form a three-dimensional structure of the semiconductor chip. Has the effect that electrical connection of the microfabricated portion can be easily performed.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention, in which (a-1)
Is a plan view of the base substrate, (a-2) is a front view of the semiconductor chip, (b) is a perspective view of a three-dimensional structure formed by attaching the semiconductor chip to the base substrate, and (c-1) has a recess. FIG. 7C is a vertical sectional side view immediately before attaching the semiconductor chip to the formed base substrate, and (c-2) is a vertical sectional side view immediately before attaching the semiconductor chip to the base substrate in which the opening is formed.

FIGS. 2A and 2B show a case where a semiconductor chip is a Fresnel lens, wherein FIG. 2A is a front view thereof, and FIG.

FIG. 3 shows a semiconductor chip, (a) is a front view,
FIG. 3B is a sectional view taken along line AA ′ of FIG.

FIGS. 4A to 4D are front views showing the shapes of convex portions of a semiconductor chip.

FIGS. 5A to 5D are front views showing other shapes of the protrusions of the semiconductor chip.

FIGS. 6A and 6B are front views showing a state in which a protrusion is formed at the tip of a convex portion of a semiconductor chip.

FIGS. 7 (a) and 7 (b) are front views showing a state where a round portion is formed at the root of a convex portion of a semiconductor chip.

FIG. 8 is a front view showing a state in which a protrusion is formed on a convex portion of the semiconductor chip.

9A and 9B show another example of a semiconductor chip, in which FIG. 9A is a front view, and FIG. 9B is a cross-sectional view taken along the line BB ′ of FIG. 9A.

FIG. 10 is a plan view showing a state in which a semiconductor chip is cut out from a semiconductor substrate while leaving a beam.

FIG. 11 is a plan view showing a state in which a large number of semiconductor chips are cut out from a semiconductor substrate.

FIG. 12 is a plan view showing a state in which when a semiconductor chip is cut out from a semiconductor substrate, the protrusions are cut out with facing each other.

FIG. 13 is a plan view showing a state in which a large number of semiconductor chips are cut out from a semiconductor substrate.

14A and 14B show a base substrate, wherein FIG. 14A is a plan view,
(b) is a sectional view of a base substrate provided with a concave portion having an enlarged portion, and (c) is a sectional view of a base substrate provided with an opening having an enlarged portion.

15A and 15B show a base substrate, wherein FIG. 15A is a cross-sectional view of a base substrate having a concave portion having an enlarged portion at a bottom portion, and FIG. 15B is a base substrate having an opening having an enlarged portion on a back surface. Cross section of the
(c) is a cross-sectional view of a base substrate provided with an opening having a large expanded portion.

16A and 16B show a base substrate having an elastic flexible structure, wherein FIG. 16A is a plan view, FIG. 16B is a vertical side view in the case of an opening, and FIG. 16C is a vertical side view in the case of a recess. It is.

FIGS. 17A and 17B show the three-dimensional structure in a state where the protrusions of the semiconductor chip are not completely inserted, wherein FIG. 17A is a front view and FIG. 17B is a side view.

18A and 18B are views showing a state in which a protruding portion having a protrusion fits into an opening, and FIG. 18A is a cross-sectional view showing a state before insertion, and FIG.
FIG. 3 is a cross-sectional view showing a fitted state.

FIG. 19 is a side view showing a stacked three-dimensional structure.

FIG. 20 is a perspective view of a three-dimensional structure supported by a stopper.

FIG. 21 is a perspective view of a three-dimensional structure in which two semiconductor chips are supported by stoppers.

FIG. 22 is a perspective view of a three-dimensional structure in which a semiconductor chip is supported by a stopper raised from a base substrate.

FIG. 23 is a perspective view of a three-dimensional structure in which a semiconductor chip is inclined and fixed.

FIG. 24 is a perspective view of a three-dimensional structure obtained by combining two semiconductor chips.

25 (a) is an exploded perspective view, and FIG. 25 (b) is an assembled perspective view showing an electrical connection of a semiconductor chip to a base substrate.

26A and 26B show a state in which a semiconductor chip is used as an acceleration sensor, where FIG. 26A is a front view, and FIG.
It is a line sectional view.

FIG. 27 shows an electrical connection of a semiconductor chip;
(a) is a longitudinal sectional side view before assembling, and (b) is a longitudinal sectional side view in an assembled state.

FIGS. 28A and 28B show the electrical connection of the semiconductor chip in a state where the protrusions are not completely inserted, wherein FIG. 28A is a longitudinal sectional side view before assembling, and FIG. 28B is a longitudinal sectional side view of the assembled state.

FIG. 29 is a vertical sectional side view showing a state where electrical connection can be made only by inserting a semiconductor chip into a base substrate.

FIG. 30 is a longitudinal sectional side view showing a state where electrical connection is made by inserting a semiconductor chip into a base substrate and using a conductive material.

FIG. 31 is a perspective view showing a state in which an opening for circulating a refrigerant is formed.

FIG. 32 is a perspective view showing an example of the related art.

FIGS. 33A and 33B show another conventional example, in which FIG. 33A is an overall perspective view, FIG. 33B is a sectional view before inserting a semiconductor chip into a base substrate, and FIG. is there.

[Explanation of symbols]

 Reference Signs List 17 chip substrate 18 convex portion 19 semiconductor chip 20 base substrate 21 concave portion 22 opening 25 semiconductor substrate 29 beam 36 protrusion 45 electrode 48 electrode 54 electrode 56 electrode

Continued on the front page (72) Inventor Hiroshi Toshiyoshi 2-16-36 Nakazato, Ninomiya-cho, Naka-gun, Kanagawa Prefecture Highness Inoue Room 105 (72) Inventor Minoru Ogawa 6-78, Minamicho, Mishima-shi, Shizuoka Prefecture Inside the research institute (72) Inventor Yoshiro Mita 2-10-2 Sakuragaoka, Yakiyama, Kure City, Hiroshima Prefecture

Claims (20)

[Claims] 1. A chip substrate of a semiconductor chip formed by individually dividing a semiconductor substrate on which a plurality of electric circuits, electronic circuits, light emitting elements, light receiving elements, mirrors, lenses, micro-electro-mechanical structures and the like are formed. At least one projection formed of the chip substrate is formed on the outer periphery, and the projection is inserted into a recess or opening formed by dividing the base substrate individually, and the semiconductor chip is fixed to the base substrate. A method for manufacturing a three-dimensional structure using a semiconductor chip. 2. A method for manufacturing a semiconductor chip, comprising: forming a plurality of semiconductor chips having convex portions from a semiconductor substrate; and disposing the semiconductor chips with the convex portions of the semiconductor chips facing each other. 3. The method according to claim 2, wherein the material of the semiconductor substrate is single crystal silicon. 4. The semiconductor according to claim 2, wherein when the semiconductor chip having the convex portion is individually divided from the semiconductor substrate, the semiconductor chip is fixed to the semiconductor substrate by at least one beam. Chip manufacturing method. 5. The semiconductor device according to claim 4, wherein at least a divided surface of the semiconductor chip is subjected to insulation treatment in a state where the individual semiconductor chips are fixed to the semiconductor substrate by beams.
The manufacturing method of the semiconductor chip described in the above. 6. The method of manufacturing a semiconductor chip according to claim 4, wherein a beam provided on the semiconductor chip is broken to divide the semiconductor chip into individual semiconductor chips. 7. The semiconductor device according to claim 1, wherein the shape of each of the divided recesses and openings formed in the base substrate is expanded in the vicinity of the substrate surface on the insertion side of the projection of the semiconductor chip. A method for manufacturing a three-dimensional structure using the semiconductor chip according to claim 1. 8. The three-dimensional structure of a semiconductor chip according to claim 1, wherein the shape of each of the divided holes formed in the base substrate is expanded near the back surface of the base substrate. How to make the body. 9. The semiconductor chip according to claim 1, wherein each of the divided recesses and openings formed in the base substrate is elastically widened when the semiconductor chip projection is inserted. A method for manufacturing a three-dimensional structure. 10. The method according to claim 1, wherein the material of the base substrate is silicon. 11. The method for manufacturing a three-dimensional structure by using a semiconductor chip according to claim 1, wherein the bottom shape of each of the divided recesses formed in the base substrate is expanded. 12. The semiconductor chip according to claim 7, wherein the recessed portion or the opening of the opening formed in the base substrate is formed by using anisotropic etching of single-crystal silicon. A method for producing a three-dimensional structure according to the above. 13. A method for forming a convex portion on the outer periphery of a semiconductor chip substrate, a separately divided concave portion and an opening in a base substrate, using an inductively coupled plasma (ICP-RIE).
The method of manufacturing a three-dimensional structure using a semiconductor chip and the semiconductor chip according to claim 3, wherein a reactive ion etching method is used. 14. The semiconductor chip according to claim 1, wherein the semiconductor chip has a convex portion inserted into a concave portion or an opening of the base substrate in a state where an edge portion of the semiconductor chip is spaced from a substrate surface of the base substrate. A method for manufacturing a three-dimensional structure using a semiconductor chip. 15. A protrusion is formed on a convex portion of the semiconductor chip, and the protrusion is engaged with an enlarged portion formed on the back surface of the base substrate or on the bottom of a separately divided concave portion. A method for manufacturing a three-dimensional structure using the semiconductor chip according to claim 1. 16. An electrical connection between an electrode provided near a convex portion of a semiconductor chip and an electrode provided near a concave portion or an opening of a base substrate. A method for manufacturing a three-dimensional structure using the semiconductor chip described in the above. 17. An electrode is provided on a surface of a convex portion of a semiconductor chip, and an electrode is provided on an inner wall of a separately divided concave portion or opening of a base substrate so that electrical connection is made only by mechanical contact. A three-dimensional structure and an electrical connection method using a semiconductor chip according to claim 16. 18. An electric / electronic inspection of a semiconductor chip mounted on a base substrate in a state where a projection of the semiconductor chip is simply inserted into a concave portion or an opening of the base substrate. A method for manufacturing a three-dimensional structure using the semiconductor chip according to claim 17. 19. The semiconductor chip according to claim 16, wherein an opening for heat radiation is formed in the base substrate, in addition to the individually divided openings for inserting the projections of the semiconductor chip. A method for manufacturing a three-dimensional structure. 20. A chip substrate of a semiconductor chip formed by individually dividing a semiconductor substrate on which a plurality of electric circuits, electronic circuits, light emitting elements, light receiving elements, mirrors, lenses, micro-electro-mechanical structures and the like are formed. At least one projection formed of the chip substrate is formed on the outer periphery, and the projection is inserted into a recess or opening formed by dividing the base substrate individually, and the semiconductor chip is fixed to the base substrate. An electrode is provided near a convex portion of the semiconductor chip, an electrode is provided near a concave portion or an opening of the base substrate, and these electrodes are connected to each other.