JPH11150265A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize miniaturization and to achieve high integration by forming a gate electrode in the vertical direction with respect to the surface direction of a semiconductor substrate, and forming the channel region of a current flowing between a source region and a drain region in the vertical direction with respect to the surface of the semiconductor substrate along the gate electrode. SOLUTION: In a semiconductor substrate 1, a diffused layer which becomes a source region 2, and a diffused layer which becomes a drain region 3t are formed in the vertical direction with respect to the surface direction of the semiconductor substrate 1 with a specified distance of separation. Furthermore, in the semiconductor substrate 1 between the source region 2 and the drain region 3, a gate electrode 5 is formed in the vertical direction with respect to the surface direction of the semiconductor substrate 1 via a gate oxide film 4. Therefore, the channel region of the current flowing between the source region 2 and the drain region 3 is formed in the vertical direction with respect to the surface direction of the semiconductor substrate 1 along the gate electrode 5. The channel regions are formed on both sides of the semiconductor substrate 1, at the upper edge side and the lower edge side of the gate electrode 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device that contributes to high integration.

[0002]

2. Description of the Related Art In recent years, a semiconductor integrated circuit has become a main component of the circuit, for example, a field effect transistor such as a MOSFET.
The trend of high-density integration has been realized by miniaturization of semiconductor devices. In particular, a MOSFET semiconductor device only needs to mainly form three electrode portions, that is, a gate electrode, a source electrode, and a drain electrode. By reducing each of the regions in a planar manner, the overall device can be miniaturized, that is, highly integrated. Has been planned.

However, in the conventional semiconductor device, since the gate electrode is formed in a plane on the semiconductor substrate, there is a limit in reducing the occupied area in a manner limited by the width of the gate electrode. That is, in order to secure a certain amount of drive current for the transistor, it is necessary to increase the gate width to some extent. The gate width is larger than the gate length or the dimension of the source / drain diffusion layer in the direction perpendicular to the gate width direction. There was a tendency. As a result, the size of the transistor increases in the direction of the gate width, and there is a limit to further miniaturization due to the size-limiting factor.

[0004]

As described above,
In a conventional field effect transistor semiconductor device,
The gate electrode is formed planarly on the semiconductor substrate, and the width of the gate electrode increases and decreases in parallel with the surface of the semiconductor substrate according to the driving force of the transistor. For this reason, even if the manufacturing process technology of the semiconductor device has advanced remarkably, there is a limit in reducing the planar transistor size in the surface direction of the semiconductor substrate from the viewpoint of the structure of the transistor. This has been an obstacle in increasing the degree of integration of the semiconductor integrated circuit, and has caused a problem that it is difficult to achieve higher integration of the entire semiconductor integrated circuit.

Accordingly, the present invention has been made in view of the above, and it is an object of the present invention to provide a semiconductor device which can be miniaturized to achieve high integration.

[0006]

According to a first aspect of the present invention, there is provided a semiconductor device of a junction type field effect transistor, wherein a source region and a drain region formed in a semiconductor substrate are provided. A gate electrode is formed in the semiconductor substrate sandwiched therebetween in a direction perpendicular to a surface direction of the semiconductor substrate, and a channel region of a current flowing between a source region and a drain region is formed along the gate electrode. It is characterized by being formed in a direction perpendicular to the surface.

According to a second aspect of the present invention, there is provided a semiconductor device of a junction field effect transistor, wherein the semiconductor device is sandwiched between a source region and a drain region formed in a semiconductor layer formed between wiring layers in a multilayer wiring structure. A gate electrode is formed in the semiconductor layer in a direction perpendicular to a surface direction of the semiconductor layer, and a channel region of a current flowing between a source region and a drain region extends along the gate electrode with respect to the surface of the semiconductor layer. It is characterized by being formed in the vertical direction.

According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the source region or the drain region has a regular polygonal or circular cross section in a surface direction of the semiconductor substrate or the semiconductor layer. A plurality of the gate electrodes are formed along the outer periphery of a regular polygon or the outer periphery of a circle of the source region or the drain region, and the gate electrode is formed as one divided transistor. .

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a semiconductor device according to an embodiment of the first aspect of the present invention. FIG. 1A is a front view, and FIG. It is sectional drawing which followed the -A line.

In FIG. 1, the semiconductor device of this embodiment is a junction type field effect transistor (FET) in which an insulator such as an oxide or a nitride is interposed between a gate electrode made of a metal or a semiconductor and a semiconductor. The direction in which the diffusion layer serving as the source region 2 and the diffusion layer serving as the drain region 3 are separated by a predetermined distance in the semiconductor substrate 1 and are perpendicular to the surface direction of the semiconductor substrate 1 (the left-right direction in FIG. 1). (The vertical direction and the depth direction in FIG. 1B). In the semiconductor substrate 1 between the source region 2 and the drain region 3, a gate electrode 5 is formed in a direction perpendicular to the surface direction of the semiconductor substrate 1 via a gate oxide film 4. Therefore,
The channel region of the current flowing between the source region 2 and the drain region 3 is formed along the gate electrode 5 in a direction perpendicular to the surface direction of the semiconductor substrate 1, and the upper side of the gate electrode 5 in FIG. Thus, a channel region is formed on both the semiconductor substrate 1 and the lower side. An insulator layer 6 serving as an element isolation region for isolating this transistor from other regions is formed in the semiconductor substrate 1 so as to surround these regions.

Next, an embodiment of a manufacturing method for manufacturing such a structure will be described.

First, an insulator layer 6 serving as an element isolation region is formed in a depth direction in the semiconductor substrate 1 by a conventionally employed method. Next, the source region 2 is formed by high acceleration implantation.
And a deep diffusion layer to be the drain region 3 is formed. In the case where it is difficult to form a sharp and deep diffusion layer as shown in FIG. 1 with a high-acceleration implant, if the semiconductor substrate 1 is opened, deposition and doping are performed simultaneously by the CVD method, for example, doped polysilicon. Depot,
Finally, unnecessary portions may be removed by a CMP method. After the diffusion layers of the source region 2 and the drain region 3 are formed in this manner, an opening is formed in the semiconductor substrate 1 for embedding an electrode material to be the gate electrode 5. After the opening, a small amount of the semiconductor substrate 1 on the side surface of the groove is oxidized, and a gate oxide film 4 is formed on the side surface of the opened groove. Finally, for example, doped polysilicon or metal serving as a gate electrode material is buried in the trench to form the gate electrode 5, and the semiconductor device of this embodiment is completed. Note that the lead lines from each region, the passivation film, and the like are formed by a conventionally used method. Also, when the gate length becomes shorter, it is considered that it is difficult to form a contact to the gate electrode 5. In this case, however, the lead line is connected to the gate electrode 5 by using a conventionally used buried lead line. May be formed.

FIG. 1 obtained by such a manufacturing method.
It is considered that the structure shown in FIG. 1 has the following effects in terms of area. For example, transistors used in gate arrays in the near future will have a transistor width of 5
It is estimated to be about μm. Therefore, in the transistor having the structure shown in FIG. 1 in order to obtain the same performance as this transistor, a current flows on both sides of the gate electrode 5 to form a channel region. Should be formed. Therefore,
In FIG. 1, the horizontal direction of the source (the horizontal direction in FIG. 1A)
The length, the gate length, the lateral length in the drain, and the element isolation width are set to reasonable values that can be manufactured in the current manufacturing process, for example, about 0.4 μm, and the source region 2 and the drain region 3
0.8 μm in the vertical direction (vertical direction in FIG. 1A)
In this case, the area occupied by the transistor having the structure shown in FIG. 1 is estimated to be about 3.2 μm ² . On the other hand, in a conventional transistor in which a gate electrode is formed on a semiconductor substrate with an insulating film interposed therebetween, the gate width is about 5 μm, so the long side in the gate width direction is about 5.8 μm, The side is about 2 μm as in FIG. 1, and the occupied area is 1
It is estimated to be about 1.6 μm ² . As a result, the transistor of this embodiment employing the structure shown in FIG. 1 can obtain the same performance with an occupied area of about (1 / 3.6) times that of the conventional transistor. Therefore, in this embodiment, the occupied area can be reduced by about 73% as compared with the conventional case, and the occupied area can be significantly reduced.

Although the semiconductor device having the above structure is formed in a semiconductor substrate, it can be formed in a semiconductor formed between insulating layers between wiring layers in a multilayer wiring structure. Even in such a case, the same effect as described above can be obtained.

FIG. 2 is a front view showing the structure of a semiconductor device according to an embodiment of the present invention.

The feature of this embodiment is shown in FIG.
Are arranged in a regular polygon, for example, a close-packed regular hexagon, to form one transistor. In FIG. 2, six gate electrodes 8 are arranged along the outer periphery of the source diffusion layer 7 formed in a hexagon, and a drain diffusion layer 9 surrounds the outside of the gate electrode 8 in a hexagonal shape. Is formed so as to surround the outer periphery thereof. Note that the shape in which the transistors are arranged is not limited to a close-packed regular hexagon, but may be a regular polygon, a circle, or a straight line.

In the transistor employing the buried gate electrode having the structure shown in FIG. 1, there is a high possibility that the size of the gate width is restricted as compared with the conventional structure in which the gate electrode is formed on a semiconductor substrate. Become. That is, since it is difficult to form gate electrodes having various gate widths (depths) from the viewpoint of the manufacturing method, manufacturing is easier if the gate width is limited to a certain size. However, when the gate width is limited, the driving force of the transistor is also limited, and there is a restriction when constructing a circuit. Therefore, by dividing the gate electrode to form one transistor as shown in FIG. 2, a transistor having a larger gate width can be formed from several transistors having a limited gate width. In the structure shown in FIG. 2, for example, when the gate depth (gate width) is about 2.5 μm, since there are 12 channels, a driving force equivalent to that of a conventional transistor having a gate width of about 30 μm is obtained. Becomes possible.

In this case, comparing the occupied area of this embodiment with that of a conventional transistor, the structure shown in FIG. 2 assumes the same manufacturing conditions as those shown in FIG. When a perpendicular line is drawn from the center of the source region 7 to the outer periphery of the insulator layer 9 in the element isolation region and the length of each region is about 0.4 μm, the occupied area is about 8.9 μm.
m ² about to be estimated. On the other hand, in the conventional example, assuming that the gate electrode is divided into six and the gate width of one gate electrode is about 5 μm, the short side of the diffusion layer of the source / drain region and the gate length are each about 0.4 μm. Then
The transistor formation region is a rectangle having sides of 6 μm × 5.8 μm, and the occupied area is about 34.8 μm ² . As a result, according to the configuration of this embodiment, it is possible to obtain the same performance as the conventional one with an occupied area of about 程度 of that of the conventional example, and it is possible to achieve a much smaller size than the conventional one.

FIG. 3 is a front view showing the structure of a semiconductor device according to another embodiment of the present invention.

In FIG. 3, the feature of this embodiment is that the transistor 11 of the embodiment shown in FIG.
Are arranged regularly without gaps to construct a semiconductor device. In such an embodiment, 1
Since the planar shape of the two transistors is a regular hexagon in which close-packed arrangement is possible, it is suitable for the purpose of densely arranging integrated circuits having a regular pattern such as a gate array.

[0022]

As described above, according to the present invention, the gate electrode is formed in the semiconductor substrate in a direction perpendicular to the surface of the semiconductor substrate, and the channel region is formed in the direction perpendicular to the surface of the semiconductor substrate. Therefore, it is possible to provide a transistor which is significantly finer than in the past, and a high integration of a semiconductor device can be achieved by constructing a circuit using the transistor.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a semiconductor device according to an embodiment of the invention described in claim 3;

FIG. 3 is a diagram showing a configuration of a semiconductor device according to another embodiment of the invention described in claim 3;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2, 7 Source region 3, 9 Drain region 4 Gate oxide film 5, 8 Gate electrode 6, 10 Insulator layer 11 Transistor

Claims (3)

[Claims] 1. A semiconductor device of a junction field effect transistor, comprising: a semiconductor device sandwiched between a source region and a drain region formed in a semiconductor substrate; And a channel region for current flowing between the source region and the drain region is formed along the gate electrode in a direction perpendicular to the surface of the semiconductor substrate. 2. A semiconductor device of a junction field effect transistor, wherein said semiconductor layer sandwiched between a source region and a drain region formed in a semiconductor layer formed between wiring layers in a multilayer wiring structure, A gate electrode is formed in a direction perpendicular to a surface direction of the semiconductor layer, and a channel region of a current flowing between a source region and a drain region is formed in a direction perpendicular to the surface of the semiconductor layer along the gate electrode. A semiconductor device, comprising: 3. The source region or the drain region has a regular polygonal or circular cross section in the surface direction of the semiconductor substrate or the semiconductor layer, and the gate electrode has a regular polygonal shape of the source region or the drain region. 3. The semiconductor device according to claim 1, wherein a plurality of transistors are formed along the outer periphery or the outer periphery of the circle, and the gate electrode is divided into one transistor. 4.