JPH11143449A - Sampling clock control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control the phase of a clock to an optimum by automatically generating a sampling clock having a period agreeing with the frequency of the input image signal in a device to display the image signal. SOLUTION: An image signal having a prescribed repetitive pattern is subjected to sample-and-hold in an A/D converter 1 by a dot clock with a changing frequency and phase supplied from a PLL circuit 4, the sample-held data detects the maximum pattern in a maximum detection circuit 3 after it is thinning-out by a thinning-out circuit 2, and the frequency division ratio and the phase of the PLL circuit 4 are set by a judging part 5 using the maximum pattern detected by the maximum detection circuit 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling clock control device, and more particularly to a means for reproducing a sampling clock corresponding to the number of pixels of an input video signal.

[0002]

2. Description of the Related Art In a conventional apparatus for automatically adjusting the frequency and phase of a clock, Japanese Patent Application Laid-Open No. 5-66752 discloses a method in which an input signal is formed based on pixels and has discrete information. As shown in the gazette, a dot signal is detected from an input video signal, and a horizontal scanning cycle is detected from a horizontal synchronization signal,
The frequency division ratio of the PLL circuit is determined from the ratio between the two to reproduce the dot clock.

[0003] With respect to a conventional dot clock reproducing circuit,
This will be described with reference to FIG. In FIG. 9, an edge detector 11 detects edge information on a change point of a signal from a video signal, and a frequency measurement circuit 12 measures a frequency from the edge information. For example, a configuration is generally employed in which a reference pulse is used to count the intervals between transition points included in the edge information. For the horizontal synchronization signal as well, the frequency of the synchronization signal is measured by the frequency measurement circuit 13, and the ratio of the frequencies measured by the measurement circuits 12 and 13, that is, the multiplier, is calculated by the calculation unit 14, and this value is calculated as P
By setting the frequency division ratio of the LL circuit 15, a dot clock corresponding to the number of pixels of the input signal is automatically generated.

[0004]

However, in the above conventional configuration, when the edge of the input video signal is detected, the frequency is measured using the reference pulse, and the period is measured, the change point of the edge detection output is determined. If the method of counting the intervals is adopted, the frequency of the reference pulse needs to be higher than the highest frequency included in the input video signal, and the frequency measurement unit needs to operate at the highest frequency. If the maximum frequency of the reference pulse becomes higher, there is a problem that the frequency of the reference pulse must be increased accordingly.

[0005]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, a sampling clock control device according to the present invention converts an input video signal having a periodic pattern into an A / D signal with a sampling clock of a VCO output locked to a horizontal synchronizing signal. And
A maximum value detecting means for reducing the frequency of the A / D-converted sampled video signal and detecting the maximum value of the frequency-reduced signal for one horizontal synchronization period, wherein the detected maximum value pattern is The sampling clock is controlled by changing the frequency and phase of the sampling clock so as to have a predetermined pattern.

According to the present invention, a sampling clock having an optimal phase and the number of pixels of an input video signal can be automatically reproduced, and the operating frequency of a circuit subsequent to the sampling section can be reduced to half or less. .

[0007]

A sampling clock control device according to a first aspect of the present invention includes means for A / D converting an input video signal having a periodic pattern with a sampling clock of a VCO output locked to a horizontal synchronization signal. A / D
A thinning means for thinning the converted sampled video signal; and a maximum value detecting means for detecting the maximum value of the thinned signal for one horizontal synchronization period, so that the detected maximum value pattern becomes a predetermined pattern. And controlling the sampling clock of the input video signal by changing the frequency and phase of the sampling clock.The sampling clock having the optimum phase at the same cycle as the pixel cycle of the video signal is automatically adjusted. Is obtained.

Next, the invention described in claim 2 of the present invention is:
The input video signal having the periodic pattern is locked to the horizontal synchronizing signal. The VCO output is A / D-converted by a sampling clock obtained by dividing the VCO output by a frequency division ratio corresponding to the number of pixels for one cycle of the periodic pattern. Conversion means, and maximum value detection means for detecting the maximum value of the A / D-converted sampled video signal for one horizontal synchronization period, so that the detected maximum value pattern becomes a predetermined pattern. The sampling clock of the input video signal is controlled by changing the frequency and the phase of the sampling clock. In the sampling control device according to claim 1, a thinning circuit can be omitted, and A sampling clock having a frequency corresponding to the number of pixels of the input video signal can be generated.

(Embodiment 1) The first aspect of the present invention will be described below.
An embodiment of the invention described in claim 2 will be described with reference to FIGS.

In FIG. 1, reference numeral 1 denotes an A / D converter which samples and quantizes an analog video signal at a cycle of a sampling clock and converts it into a digital signal. An input video signal of the A / D converter 1 has a predetermined period signal and at least two pixels or more have one period. In the case of two pixels, it is a binary signal of HIGH and LOW. Now, a four-pixel cycle will be described with reference to FIG. The output of the A / D converter 1 is supplied to a decimation circuit 2 which decimates the data of the video signal input in sampling clock units to reduce the repetition frequency of the data. Further, by changing the thinning position in units of sampling clocks, the phase with respect to one cycle of the video signal waveform (region d in FIG. 3) changes. Next, the video signal data whose repetition frequency is reduced with respect to the sampling clock by the thinning circuit 2 is supplied to the maximum value detection circuit 3.

The maximum value detection circuit 3 includes a selector, a register, a digital filter, and the like. A digital filter (not shown) reduces noise and the like included in the input video signal. The output data of the maximum value detection circuit 3 compares, for each processing pixel, the current pixel value with the maximum value so far, and stores the larger value as the maximum value for one cycle of the horizontal synchronization signal. (Region a in FIG. 3)
+ B + c) to detect the maximum value of the video signal. The maximum value of the video signal during the period of one cycle of the horizontal synchronizing signal detected by the maximum value detection circuit 3 is supplied to the determination unit 5.

FIG. 2 shows the internal configuration of the PLL circuit 4. The output from the judgment section 5 is the V in the PLL circuit 4.
A phase change amount that sets the frequency division ratio α of the output signal of the CO and the delay amount of the delay circuit 45 that delays the output signal of the VCO serving as the sampling clock is output.

The determination unit 5 is composed of a microcomputer or the like,
The PLL circuit 4 uses the maximum value obtained by the maximum value detection circuit 3 when the frequency division ratio and the phase change amount of the circuit 4 are changed, respectively.
Is determined to be equal to the total number of pixels in a period corresponding to one cycle of the horizontal synchronization signal of the input video signal, and whether the phase of the sampling clock is optimal.

The PLL circuit 4 includes a frequency divider 41, a phase comparator 42, an LPF 43, a VCO 44, a delay circuit 45, and the like, as shown in FIG. , And supplies it to the A / D converter 1. The sampling clock is delayed by the delay circuit 45 by the amount of phase change set by the determination unit 5 and outputs sampling clocks having different phases. The changing point of the sampling clock when the total number of pixels in the period corresponding to one cycle of the horizontal synchronizing signal of the input video signal coincides with the division ratio is the same position with respect to all the pixels in the video display area b. Becomes In other words, by giving a certain amount of delay, a certain phase is taken with respect to the pixel of the video signal, and by changing the amount of delay, the phase of the sampled video signal pattern changes. The delay circuit 45 can be realized by being installed at the output line 46 of the frequency divider 41 or the input line 47 to the phase comparator 42, or by being built in the frequency divider 41.

FIG. 3 shows a predetermined video signal typified by an output signal of a personal computer or the like used in controlling the sampling clock and a horizontal synchronizing signal. In the no-signal period, the number of pixels A in the area a after the horizontal synchronization signal in the no-signal period, the number of pixels C in the area c after the synchronization signal in the no-signal period, and the number of pixels B in the video display area b composed of a fixed 4-pixel periodic pattern FIG.

Next, the system shown in FIG.
A case will be described in which a video signal having a signal pattern of a video display area b (a video signal having a pattern of a 4-pixel cycle like the area d) of FIG.

FIG. 4A shows a part of the video signal in the area b in FIG. 3 and is composed of a pattern having a period of four pixels. FIG. 4B shows the A / D converter 1 in FIG. Is input with the video signal having the pattern of the 4-pixel cycle shown in FIG. 3, and the frequency division ratio α set in the PLL circuit 4 and the number of pixels in the period corresponding to one cycle of the horizontal synchronizing signal (area a + b + c in FIG. 3) A / D converter 1 when the difference of A + B + C is 4 or more, which is the number of pixels for one cycle of the video signal pattern, and the number of sampling clocks is larger than the number of pixels in one horizontal period
FIG. 4B shows an output waveform of the A / D converter 1. FIG. 4C shows that the output of the A / D converter 1 is input to the thinning circuit 2 and the A / D converter 1
4B is thinned out at the positions and in the order of the numerals 1, 5, and 9 ° indicated by arrows.

FIG. 4D shows the case where the frequency division ratio α of the PLL circuit 4 is the same and the sampling clock is delayed by one pixel from the above sampling position, that is, from the periodic pattern of four pixels in FIG. The output of the A / D converter 1 (same waveform as in FIG. 4B) when sampling in the order of numbers 1, 2, 3, 4,... .. Are the outputs of the thinning circuit 2 when thinning is performed every four pixels in the positions and in the order of the numbers 2, 6, 10,... Indicated by the arrows in FIG.

FIG. 4 (e) shows a case where the frequency division ratio α of the PLL circuit 4 is the same and the sampling position is further delayed by one pixel from the sampling position, that is, the pattern of FIG. Numbers 1, 2, 3,
The output of the A / D converter (the waveform of FIG. 4 (b)) at the time of sampling in the order of 4,... Is input to the thinning circuit 2, and the numerals 3, 7 indicated by arrows in FIG. , 11 ・
.. Are outputs of the thinning circuit 2 when thinning is performed every four pixels in the position and order of.

Here, in FIGS. 4C, 4D and 4E, the horizontal synchronizing signal 1 when the phase of the sampling clock of the A / D converter 1 is changed by the delay circuit 44.
The number of patterns of the input waveform output from the thinning circuit 2 in the video display area b corresponding to the cycle (the area a + b + c in FIG. 3) is determined by the division ratio α set in the PLL circuit 4 and the one cycle of the horizontal synchronizing signal. Assuming that the absolute value of the difference between the number of pixels A + B + C in the period (region a + b + c in FIG. 3) is Z, a constant value (Z / 4) corresponding to the quotient of 4 pixels of the video signal pattern with respect to Z is obtained. Which phase of the input waveform appears at the start position of the signal period will change.

FIG. 5A shows a part of the video signal in the area b in FIG. 3, and is composed of a pattern having a period of four pixels as in the above case.

FIG. 5B shows the A / D converter 1 shown in FIG.
3 is input, and a period corresponding to one period of the horizontal synchronizing signal and the frequency division ratio α set in the PLL circuit 4 (region a + b + in FIG. 3).
c) The output of the A / D converter 1 when the difference between the number of pixels A + B + C exceeds 4 which is the number of pixels for one cycle of the pattern of the input video signal and the number of sampling clocks is smaller than the number of pixels in one horizontal period. . The output of the A / D converter 1 is a waveform sampled at the position of the arrow near the video signal waveform in FIG.

FIG. 5 (c) shows a waveform obtained by inputting the output of the A / D converter 1 to the thinning circuit 2 and sampling and holding the output of the A / D converter 1 at intervals of four pixels. The output of the decimating circuit 2 is obtained by decimating the sampled video signal shown in FIG. 5B in the positions and in the order of numerals 1, 5, 9,...

FIG. 5D shows a case where the frequency division ratio α of the PLL circuit 4 is the same and is delayed by one pixel from the sampling position, that is, a video signal composed of a periodic pattern of four pixels in FIG. Numbers 1, 2, 3, 4,...
The output of the A / D converter 1 (same waveform as in FIG. 5B) when sampling in the order of is input to the decimation circuit 2 and the numbers 2, 6, 10 and.・
The output of the thinning circuit 2 when thinning is performed every four pixels in the position and in the order of.

FIG. 5 (e) shows a case where the frequency division ratio α of the PLL circuit 4 is the same and is further delayed by one pixel from the above sampling position, that is, the pattern of FIG. The numbers 1, 2, 3
The output of the A / D converter (the waveform of FIG. 5B) when sampling in the order of is input to the thinning circuit 2,
Numerals 3, 7, 11,... Indicated by arrows in FIG.
4 shows the output of the thinning circuit 2 when thinning is performed every four pixels in the position and order shown in FIG.

5C, 5D and 5E, one cycle of the horizontal synchronizing signal when the phase of the sampling clock of the A / D converter is changed by the delay circuit 45 (see FIG. 3). In the image display area b of the area a + b + c),
The number of patterns of the input waveform output from the thinning circuit 2 is
Assuming that the absolute value of the difference between the division ratio α set in the PLL circuit 4 and the number of pixels A + B + C in the period corresponding to one cycle of the horizontal synchronization signal (region a + b + c in FIG. 3) is Z, the pattern of the video signal pattern for Z is 4 A constant value (Z
/ 4), and which phase of the input waveform appears at the start position of the video signal period changes.

FIG. 6A shows a part of the video signal in the area b in FIG. 3, and is assumed to be composed of a pattern having a period of four pixels as in the above case.

FIG. 6B shows the A / D converter 1 shown in FIG.
3 is input, and a period corresponding to one period of the horizontal synchronizing signal and the frequency division ratio α set in the PLL circuit 4 (region a + b + in FIG. 3).
This is the output of the A / D converter 1 when the difference in the number of pixels A + B + C in c) is less than 4 pixels for one cycle of the pattern of the input video signal. The output of the A / D converter 1 is shown in FIG.
This is a waveform sampled at the position of the arrow near the video signal waveform in FIG.

FIG. 6C shows a waveform obtained by inputting the output of the A / D converter 1 to the thinning circuit 2 and sampling and holding the output of the A / D converter 1 every four pixels. The output of the thinning circuit 2 is shown in FIG.
Are thinned out at the positions and in the order of the numbers 1, 5, 9, 13,... Indicated by the arrows.

FIG. 6D shows a case where the frequency division ratio α of the PLL circuit 4 is the same and is delayed by one pixel from the sampling position, that is, a video signal composed of a periodic pattern of four pixels shown in FIG. Numbers 1, 2, 3, 4,...
The output (waveform of FIG. 6B) of the A / D converter 1 when sampling in the order of is input to the decimation circuit 2 and the numbers 2, 6, 10, and 14 indicated by arrows in FIG.・ ・
The output of the thinning circuit 2 when thinning is performed every four pixels in the position and in the order of.

FIG. 6E shows a case where the frequency division ratio α of the PLL circuit 4 is the same and the sampling position is further delayed by one pixel from the sampling position, that is, the pattern of FIG. Numbers 1, 2, 3,
The output of the A / D converter (the waveform of FIG. 6B) at the time of sampling in the order of 4,... Is input to the thinning circuit 2, and the numerals 3, 7 indicated by arrows in FIG. , 11 ・
.. Are outputs of the thinning circuit 2 when thinning is performed every four pixels in the position and order of.

FIG. 6F shows a case where the frequency division ratio α of the PLL circuit 4 is the same and the sampling position is further delayed by one pixel from the sampling position, that is, the pattern of FIG. Numbers 1, 2, 3,
The output of the A / D converter (the waveform of FIG. 6B) when sampling in the order of 4,... Is input to the thinning circuit 2, and the numbers 4, 8 indicated by arrows in FIG. , 12 ・
.. Are outputs of the thinning circuit 2 when thinning is performed every four pixels in the position and order of.

Here, the number of pixels A + B + C and PL in a period (region a + b + c in FIG. 3) corresponding to one cycle of the horizontal synchronizing signal
Assuming that the absolute value of the difference of the frequency division ratio α of the L circuit 4 is Z, the quotient of the four pixels of the video signal pattern with respect to Z is less than 1 (Z / 4
<1), during the period corresponding to one cycle of the horizontal synchronizing signal (region a + b + c in FIG. 3), the video signal pattern 4
It will appear at a part of the input waveform indicated by the pixel (region d in FIG. 3), that is, at the ratio of the quotient in one pixel.

6 (c), (d), (e) and (f), a period corresponding to one cycle of the horizontal synchronizing signal when the phase of the sampling clock of the A / D converter is changed by the delay circuit 45 ( The number of patterns output from the thinning-out circuit 2 in the video display area b in the area a + b + c in FIG. 3 is a constant value (Z / 4) corresponding to the quotient, but the number of patterns in the video signal period (area d in FIG. 3). At the start position, which phase of the input waveform appears will change.

FIG. 7A shows a part of the video signal in the area b in FIG. 3, and it is assumed that the video signal is composed of the above-described pattern having a period of four pixels. Further, FIG. 7A shows A /
This waveform is obtained by sampling the D converter 1 at the position of the arrow near the video signal waveform in FIG. That is, the division ratio α of the PLL circuit 4
In this case, the number of pixels A + B + C in the period (region a + b + c in FIG. 3) corresponding to one cycle of the horizontal synchronizing signal of the input video signal is equal.

FIG. 7B shows a waveform obtained by inputting the output of the A / D converter 1 to the thinning circuit 2 and sampling and holding the output of the A / D converter 1 every four pixels. The output of the thinning circuit 2 is obtained by converting the sampled video signal shown in FIG.
.. Are thinned out in the position and order of 5, 9,....

FIG. 7 (c) shows a case where the frequency division ratio α of the PLL circuit 4 is the same and is delayed by one pixel from the above sampling position, that is, a video signal composed of a periodic pattern of four pixels in FIG. 7 (a). Numbers 1, 2, 3, 4,...
The output (waveform of FIG. 7A) of the A / D converter 1 at the time of sampling in the order of is input to the thinning circuit 2, and the numbers 2, 6, 10,... The output of the thinning circuit 2 when thinning is performed every four pixels in the position and in the order of.

FIG. 7D shows a case where the frequency division ratio α of the PLL circuit 4 is the same and the sampling position is further delayed by one pixel from the sampling position, that is, the pattern of FIG. The numbers 1, 2, 3
The output of the A / D converter (the waveform of FIG. 7 (a)) at the time of sampling in the order of is input to the thinning circuit 2,
Numerals 3, 7, 11,... Indicated by arrows in FIG.
4 shows the output of the thinning circuit 2 when thinning is performed every four pixels in the position and order shown in FIG.

FIG. 7 (e) shows a case where the frequency division ratio α of the PLL circuit 4 is the same and is further delayed by one pixel from the sampling position, that is, the pattern of FIG. The numbers 1, 2, 3
The output of the A / D converter (the waveform of FIG. 7 (a)) at the time of sampling in the order of is input to the thinning circuit 2,
Numerals 4, 8, 12,... Indicated by arrows in FIG.
4 shows the output of the thinning circuit 2 when thinning is performed every four pixels in the position and order shown in FIG.

Here, in FIGS. 7B, 7C, 7D and 7E, the horizontal synchronizing signal when the phase of the sampling clock of the A / D converter 1 is changed by the delay circuit 45 is shown. (Period a + b in FIG. 3)
The waveform output from the thinning circuit 2 in the image display area b of + c) keeps outputting the value of the waveform at the changed phase. For example, when a signal having a period of four pixels as shown in FIG. 7A is input, a constant value is taken during one pixel period, so that the phase of the sampling clock changes with respect to a clock that matches the period of the pixel of the video signal. The waveforms output from the thinning circuit 2 in the case of
(B), (c), (d) and (e).

Next, referring to FIG. 8, the dividing ratio α of the PLL circuit 4 will be described.
And a period corresponding to one cycle of the horizontal synchronizing signal (region a + in FIG. 3).
The relationship between the sampling phase and the detected maximum value when the difference of the number of pixels A + B + C of (b + c) is changed will be described.

FIG. 8A shows the difference between the frequency division ratio α of the PLL circuit 4 and the number of pixels A + B + C in the period (region a + b + c in FIG. 3) corresponding to one cycle of the horizontal synchronization signal of the input video signal. And the period corresponding to one cycle of the horizontal synchronizing signal from the maximum value detection circuit 3 in FIG. 1 (the area a + b + c in FIG. 3). Is the relationship of the maximum value of the video signal output at The difference between the frequency division ratio α of the PLL circuit 4 and the number of pixels A + B + C in the period corresponding to one cycle of the horizontal synchronization signal of the input video signal (the area a + b + c in FIG. 3) is the number of pixels in one cycle of the video signal pattern. In this case, the output of the thinning circuit 2 is as shown in FIG.
As shown in (d), (e), and FIGS. 4 (c), (d), and (e), a pattern approximating a 4-pixel period pattern of the input video signal and a waveform obtained by inverting the pattern from side to side, respectively,
Assuming that the absolute value of the difference between the division ratio α set in the PLL circuit 4 and the number of pixels A + B + C in the period corresponding to one cycle of the horizontal synchronization signal (region a + b + c in FIG. 3) is Z, the pattern of the video signal pattern for Z is 4 A constant value (Z
/ 4), the waveform of the four pixels of the video signal pattern exists at least once in a period corresponding to one cycle of the horizontal synchronization signal (region a + b + c in FIG. 3).
Therefore, the maximum value detection circuit 3 outputs the maximum value of the four pixels of the periodic pattern of the video signal even if the phase of the video signal of the input waveform changes in the pixel cycle.

For example, the input video signal waveform is shown in FIG.
5 (a), the total number of pixels A + B + C and PL during a period (region a + b + c in FIG. 3) corresponding to one period of the horizontal synchronizing signal of the input video signal.
When thinning is performed for every four pixels when the difference in the division ratio of the L circuit 4 is 8, two left and right inverted waveforms of a video signal having a pattern of four pixel cycles are input to the maximum value detection circuit 3. At this time, the phase of the input waveform in a 4-pixel cycle (1 pixel unit)
And a period corresponding to one cycle of the horizontal synchronizing signal (region a + in FIG. 3).
As shown in FIG. 8A, the relationship between the maximum values of (b + c) is a period corresponding to one cycle of the horizontal synchronizing signal of the input waveform (region a in FIG. 3).
+ B + c) indicates a constant value with respect to the phase in the pixel cycle of the video signal.

FIG. 8B shows the difference Z between the frequency division ratio α of the PLL circuit 4 and the number of pixels in a period (region a + b + c in FIG. 3) corresponding to one cycle of the horizontal synchronization signal of the input video signal. FIG. 8 is a diagram illustrating a relationship between a phase in a pixel cycle of a video signal and a maximum value of the video signal when the number of pixels is less than four pixels in one cycle. A period corresponding to the frequency division ratio α of the PLL circuit 4 and one cycle of the horizontal synchronization signal of the input video signal (region a + b + c in FIG. 3)
The difference between the number of pixels A + B + C is 4 in the pattern of the input video signal.
The output of the thinning circuit 2 when the number of pixels is smaller than the number of pixels is
As shown in (c), (d), (e), and (f), a waveform including a part of a waveform of a 4-pixel cycle of the input video signal appears. Therefore, when the phase in the pixel cycle of the video signal of the input waveform changes, the maximum value detection circuit 3 outputs the largest one among the outputs of the thinning circuit 2, and determines the maximum value of the four pixels of the pattern of the input video signal. Not always output.

The ratio of the display waveform to the four pixel period of the video signal pattern is determined by the division ratio α of the PLL circuit 4 and the total number of pixels in the period (region a + b + c in FIG. 3) corresponding to one period of the horizontal synchronization signal of the input video signal. The quotient of the absolute value Z of the difference from the number A + B + C and the four pixels of the pattern of the input video signal (Z /
4) multiplied by the quotient (B / (A + B + C)) of the number of pixels B in the video display area b and the total number of pixels A + B + C. For example, the input video signal waveform has a pattern of four pixel periods as in FIG. 6A, and a period corresponding to one horizontal synchronization signal period of the input video signal (region a + b in FIG. 3).
+ C), when the difference between the number of pixels A + B + C and the frequency division ratio α of the PLL circuit 4 is 3, the thinning is performed every four pixels, and the relationship between the phase and the maximum value in the four pixel cycle of the video signal pattern is four pixels Data of three pixels of the video signal of the periodic pattern appears, as shown in FIG.

FIG. 8C shows a video signal pattern when the frequency division ratio α of the PLL circuit 4 is equal to the number of pixels A + B + C in a period corresponding to one cycle of the horizontal synchronization signal of the input video signal (region a + b + c in FIG. 3). FIG. 9 is a diagram showing a relationship between a phase and a maximum value in a four-pixel cycle. The period corresponding to the frequency division ratio α of the PLL circuit 4 and one cycle of the horizontal synchronizing signal of the input video signal (FIG.
The output of the thinning circuit 2 when the number of pixels A + B + C in the area a + b + c) is equal to each other is shown in FIGS. 7 (b), (c), (d),
As shown in (e), data of one pixel of a video signal having a pattern of a 4-pixel cycle is output. If the phase (the number of pixels) of the four pixels of the pattern of the input video signal is changed from the same state, the sampling point will be shifted. The relationship is almost the same as the 4-pixel period pattern of the input waveform. For example, the input video signal waveform has a pattern of four pixel periods as in FIG. 7A, and the number of pixels A + B + C and the PLL in a period (region a + b + c in FIG. 3) corresponding to one period of the horizontal synchronization signal of the input video signal. When thinning is performed every four pixels when the difference in the division ratio α of the circuit 4 is equal, data for one pixel of a video signal having a pattern of a four-pixel cycle is output. At this time, the relationship between the phase and the maximum value in a 4-pixel cycle of the input video signal is shown in FIG.
As shown in (c), the waveform is similar to the waveform of the input video signal in the 4-pixel cycle (region d in FIG. 3).

Therefore, the relationship between the phase and the maximum value of the input waveform as shown in FIGS. 8A, 8B, and 8C in the four-pixel cycle is input to the determination unit 5, and the input value and the determination unit 5 Based on the relationship with the video signal data possessed, it is possible to determine whether the frequency division ratio α set in the PLL circuit 4 matches and whether the sampling clock phase is optimal. In the above description, the A / D converter 1
The sampling clock, which is the output of the PLL circuit 4, is input to the A / D converter 1, and the output of the A / D converter 1 is supplied to the thinning circuit 2. However, the frequency of the sampling clock of the PLL circuit 4 is divided to reduce the frequency in advance. A configuration in which the sampling clock is supplied to the A / D converter 1 and the subsequent thinning circuit 2 is omitted can be similarly implemented.

As described above, the video signal, which is an adjustment pattern composed of a periodic pattern having two or more pixels for one cycle, is sampled to obtain the frequency division ratio of the PLL circuit and one cycle of the horizontal synchronizing signal of the input video signal. If the number of pixels of each pixel matches, the waveform substantially the same as the input waveform of the pixel cycle is obtained from the relationship between the phase and the maximum value in the pixel cycle of the adjustment pattern of the input waveform,
In addition, it can be determined that the state in which the data amount of the waveform becomes maximum is optimal in terms of both the number of pixels and the phase in the pixel cycle of the input waveform, and a normal graphics video signal is sampled using the sampling clock. It is displayed on a display device (not shown).

For example, from VGA mode to XVGA mode, 640 × 480, 800 × 600, 1024 × 768
Using the respective adjustment patterns corresponding to the graphics mode, etc., the number of sampling clocks corresponding to each input video is 640, 800, and 1024, and the optimum sampling clocks of the sampling phases are generated. Mode images can be displayed.

[0050]

As described above, according to the sampling clock control device of the present invention, it is possible to automatically generate an optimal sampling clock with the number of clocks and the clock pulse phase corresponding to various display graphics modes. .

[Brief description of the drawings]

FIG. 1 is an overall block configuration diagram of a sampling clock control device according to an embodiment of the present invention.

FIG. 2 is a detailed block diagram of a PLL circuit according to the embodiment of the present invention.

FIG. 3 is a diagram schematically showing a video signal and a horizontal synchronization signal of an input signal according to the embodiment of the present invention.

FIG. 4 shows a case where the difference between the frequency division ratio and the number of pixels of the input video signal is equal to or greater than the number of pixels corresponding to one cycle of the pattern of the input video signal and the number of sampling clocks is larger than the number of pixels in the embodiment of the present invention. Diagram showing the relationship between sampling data amount and time

FIG. 5 illustrates a case where the difference between the frequency division ratio and the number of pixels of the input video signal is equal to or more than the number of pixels corresponding to one cycle of the pattern of the input video signal and the number of sampling clocks is smaller than the number of pixels in the embodiment of the present invention. Diagram showing the relationship between sampling data amount and time

FIG. 6 shows a relationship between sampling data amount and time when the difference between the frequency division ratio and the number of pixels of the input video signal is less than the number of pixels corresponding to one cycle of the pattern of the input video signal in the embodiment of the present invention. Figure showing

FIG. 7 is a diagram illustrating a relationship between a sampling data amount and time when the frequency division ratio and the number of pixels of an input video signal are equal in the embodiment of the present invention.

FIG. 8 is a diagram illustrating a relationship between a sampling data amount and a phase in a cycle of an input waveform according to the embodiment of the present invention.

FIG. 9 is a block diagram of a conventional sampling clock control device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 A / D converter 2 Thinning circuit 3 Maximum value detection circuit 4 PLL circuit 5 Judgment part 41 Divider 42 Phase comparator 43 LPF 44 VCO 45 Delay circuit

Claims (2)

[Claims] 1. An input video signal having a periodic pattern,
Means for A / D conversion with the sampling clock of the VCO output locked to the horizontal synchronization signal, thinning means for thinning out the A / D converted sampling video signal, and maximum for detecting the maximum value of the thinning signal for one horizontal synchronization period Value detecting means for controlling the sampling clock of the input video signal by changing the frequency and phase of the sampling clock so that the detected maximum value pattern becomes a predetermined pattern. Sampling clock control device. 2. An input video signal having a periodic pattern,
Means for A / D converting the input video signal with a sampling clock obtained by dividing a VCO output locked to a horizontal synchronizing signal by a frequency division ratio corresponding to the number of pixels for one cycle of the periodic pattern; A maximum value detecting means for detecting a maximum value of the converted sampled video signal for one horizontal synchronization period; changing a frequency and a phase of the sampling clock so that the detected maximum value pattern becomes a predetermined pattern; And controlling the sampling clock of the input video signal.