JPH11149705A - Reproducer and data storage method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability of reproducing data by normally conducting the addition in writing of data to a buffer memory at all times in a reproducer performing data buffering. SOLUTION: The result of the decision of sector-address definition is obtained on the basis of the continuity of a read sector address and the result of an IED(error detection) by utilizing the data contents of a sector-address region. The write place of a sector, where the result of the decision of sector-address definition is acquired lastly while retroacting to a time when a buffer memory is full is determined as a write-addition pointer Point-R, and write is conducted from sector data (N+3) corresponding to the write-addition pointer Point-R from the place at the time of write addition.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproducing apparatus having a data buffering function of reading data temporarily stored in a buffer memory and outputting it as reproduced data, for example, and a data storing method applied to such a reproducing apparatus. About.

[0002]

2. Description of the Related Art For example, in a data reproducing apparatus for reproducing data recorded on a disk-shaped recording medium (hereinafter, simply referred to as a disk) such as a CD player or a DVD player, a higher speed than a normal rate is obtained from a disk. Is temporarily stored in a buffer memory formed by, for example, a DRAM, and the data stored in the buffer memory is reproduced by reading the data at a predetermined data transfer rate lower than the reading rate from the recording medium. What is configured to output as data is known. By providing such a data buffering function, even if data is read from the recording medium intermittently, data read from the buffer memory can be given continuity.
For example, even if a read error occurs due to disturbances such as vibration applied to the playback device or a defect of the disk, by performing a read retry on the disk as long as the data is accumulated in the buffer memory, the read operation can be properly performed. Reproduction data can be obtained. That is, vibration resistance and defect resistance are improved.

By the way, as long as the write rate to the buffer memory is higher than the read rate, as long as data is read from the disk properly, the data capacity accumulated in the buffer memory at a certain point in time becomes full. State. In such a case, the reproducing apparatus suspends the reading of data from the disk, and during this time, if the storage capacity of the buffer memory in which the data reading is continued has a margin of a predetermined amount, access to the subsequent data recording position is performed. , The data reproduction is resumed, the data is transferred to the buffer memory, and this data is written at the end of the data on the buffer memory.

[0004]

By the way, when the data reproduced from the disk is written to the buffer memory as described above, the last data stored in the buffer memory and the data written following this data are written. It is necessary to check the logical continuity with the data to be connected. As a method of confirming the continuity of such data, for example, the content of the last written data is stored in the buffer memory in the playback device, and the content of the playback data is monitored during the writing splicing process. For example, if it is determined that the same reproduction data as the data content last written in the buffer memory is obtained, for example, a write pointer to the buffer memory is set so as to continue writing from the next data. I have. For the identification of the data content, for example, it is inserted for each predetermined data unit,
What is necessary is just to refer to the predetermined identification code which has the content which can judge the continuity of data.

However, the following problem may occur in the above-described data writing and linking method. For example, the data contents already stored in the buffer memory include, for example, an interpolation protection process performed at a stage before data transfer to the buffer memory even if a certain read error occurs when reading the disk. Thus, the data that cannot be read from the disk is actually interpolated. By such interpolation protection processing, for example, the interpolation processing is also performed on an identification code that is an element for determining data continuity. Here, it is assumed that, for example, as the last data written to the buffer memory, the data was not properly read as the actual reproduction data, and the interpolation processing was performed.

In this case, when the reproducing apparatus resumes the disc reproducing operation for writing, for example, first,
Access is made to the recording position of the last written data in the buffer memory. However, even if the disk is reproduced by accessing the recording position of the data which is assumed to be written last in the buffer memory, the data read at this recording position is still the same as the data read at the time of the previous data read. Similarly, there is a high possibility that a certain kind of error occurs in data reading. In this case, the playback device may not be able to determine that the content of the playback data matches the content of the last data written to the buffer memory, and accordingly, the It will not be possible to execute data writing.

[0007]

SUMMARY OF THE INVENTION In view of the above-mentioned problems, the present invention is designed to always perform appropriate data writing to a buffer memory regardless of, for example, the state of reading data from a disk. And to improve the reliability of data reproduction.

Therefore, data reproducing means for reproducing data from a predetermined type of recording medium, data storing means for storing reproduced data obtained by the data reproducing means,
Data writing / reading means for writing data to the data storage means at a predetermined write-compatible transfer rate and for reading data to the data storage means at a read-compatible transfer rate lower than the write-compatible transfer rate; A data extraction means for extracting the data whose contents are set according to a predetermined definition from the reproduced data, and outputting the extracted data as data for quality detection; and a data storage means by the data extraction means for quality detection. The quality detection data extracted from the playback data to be written is input,
Reproduction data quality determination means for determining the quality of the reproduction data in accordance with a predetermined rule based on the input quality detection data, and writing is performed on the data storage means based on the determination result of the reproduction data quality determination means. Based on the determination result of the writing data determination means for determining the logical start position of the reproduction data to be written, and the determination result of the reproduction data quality determination means, the writing connection start address when the writing is to be performed on the data storage means is set. And a determination unit for determining a writing start address. Then, at the time of starting the data writing, the data writing / reading means logically converts the reproduction data determined by the writing data determination means with respect to the writing connection start address determined by the writing connection address determining means. A playback device configured to execute data writing from a start position.

According to the above configuration, based on the determined quality of the reproduced data (accuracy of the reproduced data), the write start address at the time of writing and the data to be written and connected corresponding to the write start address are determined. The logical position is determined. Therefore, the write start address at the time of writing and the write start address at the time of reading should be connected in accordance with the data at the time of reading the recording medium having the quality higher than a required level. If the data position is determined, the possibility that the necessary write data is properly read out when the recording medium is re-accessed for the write connection is significantly increased.

[0010]

Embodiments of the present invention will be described below with reference to FIGS. The following description will be made in the following order. (1. First Embodiment (DVD-RW Player)) 1-a. Physical format of DVD-RW 1-b. Logical format of DVD-RW 1-c. DVD-RW player 1-d. Memory write / read control circuit (2. Second embodiment (CD player)) 2-a. Subcode format 2-b. CD player 2-c. Memory write / read control circuit

(1. First Embodiment (DVD-RW Player)) 1-a. Physical Format of DVD-RW The optical disc to which the first embodiment corresponds is a DVD-R
A rewritable optical disk (DVD-RW (ReWritable
). Therefore, first, the physical format (mainly the wobble address format) will be described with reference to FIGS.

Tracks are previously formed by grooves on the optical disk according to the present embodiment, and the physical addresses are expressed by wobbling the grooves. Although the detailed description is omitted here, the groove is wobbled by a signal obtained by FM-modulating the address, so that the reproduction information from the groove can be read out from the groove.
The absolute address can be extracted by performing M demodulation. The disk is driven to rotate by a CAV (constant angular velocity) method, and the absolute address included in the groove is CAV data accordingly.

In this optical disk, a groove recording method is used (lands are not used for recording), and the track pitch is from the center of a groove to the center of an adjacent groove in the track width direction. The data is recorded at a constant linear density (CLD). However, a certain width is set as the linear density range, and in practice, a very large number of zoning settings are performed, so that the disk as a whole has a state close to a constant linear density. In this specification, this is called zone CLD (Zoned
Constant Linear Density). As a modulation method of recording data, 8
-16 modulation is adopted, and mark edge recording on a phase change recording medium is performed.

FIG. 4 shows an example of the groove structure of the optical disk of this embodiment. As shown in FIG. 4A, in the groove area of the disk 1 of this example, a pre-group 100 is formed in a spiral shape from the inner periphery to the outer periphery in advance. Of course, the pre-group 100 can be formed concentrically.

The pre-group 100 is shown in FIG.
As shown in (b), a part thereof is enlarged, and the left and right side walls are wobbled corresponding to the address information. That is, the signal wanders at a predetermined cycle corresponding to the wobbling signal generated based on the address. A land 101 is formed between the groove 100 and the adjacent groove 100, and data is recorded on the groove 100. For example, in the disk 1, the wobble amplitude is actually set to, for example, about 12.5 nm, but the wobble amount is instantaneously increased at a certain period interval on the groove. The wobble amplitude is, for example, 25 to 30 nm.
About.

One track (one track) has a plurality of wobbling address frames. As shown in FIG. 5, the wobbling address frame is divided into eight parts in the direction of rotation of the disk, and each part is a servo segment (segment 0 to segment 7). One servo segment (hereinafter simply referred to as a segment) includes 48-bit information mainly including an absolute address, and wobbling per segment is 360 waves. Each segment (segment0 to seg
In each wobbling address frame as the ment 7), the wobble groove is formed by FM-modulating 48-bit wobble data.

The fine clock mark (Fine clock mark)
Clock Marks) are formed at equal intervals on the wobbling groove.
The fine clock marks, which are used for generation by the circuit, are formed in 96 pieces per one rotation of the disk, so that 12 fine clock marks are formed per segment.

Each segment (segment 0 to seg
Each wobbling address frame as the ment 7) has the configuration shown in FIG. In the 48-bit wobbling address frame, the first 4 bits are a synchronization signal (S) indicating the start of the wobbling address frame.
ync). This 4-bit synchronization pattern is 8
This is bi-phase data that forms 4-bit data using channel bits. The next 4 bits are layer information (Layer) indicating which layer of the plurality of recording layers or what kind of layer structure the disc has.

The next 20 bits are used as a track address (track number) as an absolute address on the disk. Further, the next 4 bits indicate a segment number. The segment number value is segment0 to segment
The segment number is a value of “0” to “7” corresponding to t7, that is, the segment number is a value indicating the circumferential position of the disk. The next two bits are reserved, and the last 14 bits of the wobbling address frame are an error detection code (C
RC) is formed.

As described above, fine clock marks are formed at equal intervals in the wobbling address frame. FIG. 6 shows the state of the fine clock mark. Assuming that 48 bits of data are recorded in each wobbling address frame and one bit is represented by seven waves (carriers) of a predetermined frequency signal as shown in FIG. , There will be 360 waves. Assuming that the disk 1 is rotated at 1939 revolutions per minute, the frequency of this carrier is 93.1 KHz.

As shown in FIG. 6, in the wobbling address frame shown in FIG. 7, one bit is allocated for every four bits of the address information for the fine clock mark. The fine clock mark is superimposed on one of the bits. The first one bit in units of four bits is a bit including a fine clock mark, and the remaining three bits are bits not including a fine clock mark. The bits including the fine clock mark are enlarged and shown in the lower part of FIG. 6, and as shown, the waveform as the fine clock mark FCK is included at the center position of the data bit length. As for the actual meandering shape of the groove 100 on the disk 1, the wobble amplitude instantaneously increases to, for example, about 30 nm in a portion corresponding to the fine clock mark FCK.

In one frame, twelve fine clock marks are recorded every three bits, so that 96 (= 12 × 8) fine clock marks are recorded in one rotation (one track). Be recorded. The fine clock mark (PLL clock generated from the fine clock mark in the recording / reproducing device) can be information that is finer than the segment number and indicates the circumferential position.

The carrier frequency of each data of 48 bits is a value corresponding to each data. Each data such as the track number is bi-phase modulated and then frequency-modulated, and the pre-groove is wobbled with this frequency-modulated wave.

1-b. Logical Format of DVD-RW Next, the logical format of the recording data will be described with reference to FIGS.
This will be described with reference to FIG. In the disk corresponding to the present embodiment, as shown in FIG.
It is composed of 2 Kbytes, and data is recorded in units of this cluster. The 32 Kbytes are also treated as an ECC block (hereinafter, simply referred to as a block). The block (ECC block) is a unit constituting an error correction block, and is a data unit of 32 Kbytes formed by adding an error correction code. One block is composed of 16 sectors.

As a sector structure, as shown in FIG.
2K bytes (2048 bytes) of data is extracted as data for one sector, and a 16-byte overhead is added thereto. The overhead includes a sector address, an error detection code for error detection, and the like.

The data of a total of 2064 (= 2048 + 16) bytes is represented by 12 × 17 bytes shown in FIG.
It is 2 (= 2064) bytes of data (one sector). Then, 16 pieces of data for one sector are collected, and 192 (= 12 × 16) × 172 bytes of data shown are constructed. For this 192 × 172 byte data, a 10-byte inner code (PI) and a 16-byte outer code (PO) are added as parity to each byte in the horizontal and vertical directions.

Further, a total of 2
08 × 182 bytes (= (192 + 16) × (172+
10) Among the data blocked in 16), 16 × 18
The 2-byte outer code (PO) is divided into 16 1 × 182-byte data, and as shown in FIG.
Data is added one by one below the 16 sector data of 82 bytes Nos. 0 to 15 and interleaved. Then, 13 (= 12 + 1) × 182 bytes of data is 1
This is the sector data.

Further, the data of 208 × 182 bytes shown in FIG. 11 is divided into two in the vertical direction as shown in FIG.
(Row) × 2 (frame) data. At the beginning of each data of the 208 × 2 frame, 13
A (row) × 2 (frame) linking section (link area data) is added. More precisely, the part of the data of the linking section for 26 frames is recorded at the end of the previous cluster, and the rest is recorded at the head of the current cluster.

At the beginning of the 91-byte frame data,
Further, a 2-byte frame synchronization signal (FS) is added. As a result, as shown in FIG. 12, one frame of data becomes a total of 93 bytes of data, and a total of 221 (ro
w) × 93 × 2 bytes, that is, data of a block of 442 frames. This is data for one cluster (block as a unit of recording). The size of the real data portion excluding the overhead portion is 82 Kbytes (= 2
048 × 16/1024 Kbytes).

As described above, in the case of this example, one cluster corresponds to one cluster.
One sector is composed of 26 frames.

FIG. 13 shows a data structure of one sector formed by 12 × 172 bytes in FIG. The first 4 bytes of the first row of the sector shown in this figure are ID
It has a data structure described later with reference to FIG. The following 2 byte area is an IED area, and the ID
The error detection code for the area is stored. In this specification, the 6-byte area including the ID area and the IED area is also referred to as a sector address area. The 6 bytes following the IED area are “Rese
reved "area, which is unused. For example," 0 "is set in all 6 bytes. Thereafter, 7 in the first row
In the area from the byte to the 168th byte in the 12th line,
Data is stored, and the last 4 bytes of the twelfth row are used as an EDC area for storing an error detection code for a sector unit.

ID area in a sector (4 bytes = 32
Bit) is, as shown in FIG.
It is formed of Sector Information and a sector number area of lower 24 bits. In the Sector Information area, the upper 1 bit is the sector format type, the upper 2 bits are the Sector Format Type, the upper 3 bits are the Tracking Method, and the upper 4 bits are the Reflectivi.
ty, the upper 5 bits and 6 bits of the 2-bit area are
The Area Type, the upper 7 bits are Data Type, and the upper 8 bits are Layer Number, and required values are stored according to the relationship between each definition and the actual format.

The sector number area for identifying the current sector, that is, information on the sector address, is stored in the sector number area of the lower 24 bits (3 bytes) in the ID area. The sector number is set to a different value for each sector, and the value is incremented for each sector in the direction recorded on the disk. Therefore, this sector number information can be used as information for specifying a data position in units of sectors read from the disk and identifying data continuity in units of sectors. That is, it can be used as data for detecting the quality of reproduced data described later.

1-c. DVD-RW Player FIG. 1 is a block diagram showing a main part of a recording / reproducing apparatus capable of performing recording / reproducing in accordance with the above-mentioned disk format.

The disk 1 is a recording medium in the format described above with reference to FIGS. 4 to 12, and is driven to rotate at a predetermined constant angular velocity (CAV) by the spindle motor 2 during a recording / reproducing operation. The rotation speed servo control of the spindle motor 2 is performed by a spindle servo circuit 17.
Done by

The rotating disk 1 is irradiated with a laser beam from the optical head 3. Optical head 3
For example, a laser light source such as a laser diode or a laser coupler, an optical system such as various lenses or a beam splitter, an objective lens serving as an output end of a laser beam, a detector detecting reflected light from a disk, and a tracking direction and an objective lens. A biaxial mechanism or the like for movably holding in the focus direction is provided, and a sled mechanism (not shown) for transporting the optical head 3 along the disk radial direction is provided.

The recording / reproducing apparatus of this embodiment employs the phase change recording method as described above as a recording method for a disk. For this reason, during recording, the optical head 3 irradiates a laser pulse obtained by combining a laser pulse having a predetermined recording level onto an erasing level of a predetermined level which is slightly smaller than the predetermined level, thereby applying a laser beam to the phase change type disk. I am made to record. At the time of reproduction, for example, laser light at a predetermined reproduction level lower than the above-mentioned erasing level is applied to the disk 1, and the reflected light is detected by a detector to obtain reproduction information.

The RF matrix amplifier 4 includes a current-voltage conversion circuit, an amplification circuit, a matrix operation circuit, and the like, and generates a necessary signal based on a detection signal from a detector of the optical head 3. For example, a reproduction RF signal P / RF as an analog signal as reproduction data, a focus error signal FE for servo control, and a tracking error signal TE are generated. Further, in the present embodiment, the wobbling reproduction signal P / WB including the wobbling address information and the fine clock mark formed on the wobbling are detected from the read information on the wobbling included in the detection signal from the detector of the optical head 3. The fine clock mark signal S · FCM obtained as described above is separated and generated.

The reproduced RF signal P / RF is input to the reproduced RF waveform processing circuit 5, where it performs asymmetry correction and binarization on the reproduced RF signal P / RF, and outputs it as reproduced RF data D / RF.

The reproduced RF data D / RF is an RF-PLL
The signal is branched and supplied to the circuit 6 and the 8-16 demodulation circuit 7. The RF-PLL circuit 6 generates a reproduction clock PLCK synchronized with the channel bit frequency of the input reproduction RF data D / RF. This reproduction clock PLC
K is used as a reference clock for signal processing and the like at the time of reproduction, and is input to, for example, the 8-16 demodulation circuit 7 as shown in the figure, and serves as a reference for signal processing timing in the 8-16 demodulation circuit 7. The 8-16 demodulation circuit 7 applies a so-called 8-1 to the input reproduced RF data D / RF.
6 demodulation processing is performed and supplied to the decoding circuit 8. DV
The D data decoding circuit 8 executes error correction processing on the 8-16 demodulated data on which the 8-16 demodulation processing has been performed, and also adapts data modulated in a format compatible with the DVD format to user data, for example. Executes the process of converting (demodulating) to the format, and
Output to the memory controller 19 as UD. D
The VD data decoding circuit 8 can supply required reproduction data processing information related to the reproduction data processing result and the like to the system controller 18.

In this case, the reproduced user data P · UD output from the DVD data decoding circuit 8 is temporarily stored in the buffer memory 2 under the control of the memory controller 19.
0 is stored. The reproduction user data P · UD read from the buffer memory 20 at a predetermined timing is
The data is transmitted to the interface circuit 9.

The buffer memory 20 is composed of a D-RAM or the like, and has a storage capacity sufficient to obtain a required data storage amount. Of course, a larger capacity may be used. It is not always necessary to use a D-RAM.

By performing the reproducing operation using the buffer memory 20 in this manner, an anti-vibration function (ESP function) can be obtained. That is, the rotation speed of the disk 1 by the spindle motor 2 is adjusted, and the DVD
The processing up to the data decoding circuit 8 is performed at a high rate, and the decoded reproduced user data P · UD is written into the buffer memory 20. On the other hand, reading from the buffer memory 20 is performed at a normal rate under the control of the memory controller 19, so that data is output at a normal prescribed transfer rate.

Here, due to the difference between the write bit rate and the read bit rate of the buffer memory 20, a certain amount of data is always stored in the buffer memory 20. Therefore, even if a track jump or a defect occurs due to a disturbance or the like, and the data reading from the disk 1 by the optical head 3 is temporarily stopped, the reading from the buffer memory 20 can be continued. Is output to In this case, the optical head 3 accesses an appropriate position and resumes data reading while the reproduction with the stored data is continued.

The interface circuit 9 is connected to a data processing device such as a host computer (not shown), and reproduces user data P • UD and recording user data RU between the recording / reproducing device and the host computer.
D is transmitted.

The wobble waveform processing circuit 10 performs necessary demodulation processing such as FM demodulation processing on the input wobbling reproduction signal P · WB, thereby obtaining the signal shown in FIG.
Wobble reproduction data D · W corresponding to the data shown in FIG.
B and a wobble reproduction data clock WBCK having a frequency synchronized with the wobbling cycle are generated and output to the reproduction / recording position management circuit 11. Reproduction / recording position management circuit 1
1 outputs the recording / reproducing position management information POS indicating the recording / reproducing position by performing a decoding process or the like on the wobble reproduction data D / WB using the wobble reproduction data clock WBCK as a processing clock. In this case, the recording / reproducing position management information POS includes at least track address information (r-coordinate information), segment address information, θ-coordinate information indicating an angular position on the disk, and recording / reproducing position management by (and θ = 0 signal). Information P
It is possible to output the OS. The recording / reproducing position management information POS is supplied to the system controller 18 and used for required recording / reproducing control. Here, for example, if the system controller 18 refers to at least the track address information (r coordinate information) and the θ coordinate information, the current recording / reproducing position information (r, θ) on the disk is specified. .

The recording clock generating circuit 12 is provided with a PLL circuit, and outputs a fine clock mark signal S.FC
By inputting M to the PLL circuit, a recording clock WTCK, which is a data recording clock, is generated and output. The recording clock WTCK is input to the 8-16 modulation circuit 14 and used as a reference clock for 8-16 modulation processing during recording. Further, the recording clock WTCK is also supplied to the reproduction / recording position management circuit 11, and is used for detection of the reproduction / recording position in the reproduction / recording position management circuit 11 during recording / reproduction.

At the time of recording, recording user data R · UD is input to the DVD data encoding circuit 13 from the interface circuit 9 shown in FIG. In the DVD data encoding circuit 13, the recording user data RU
D is encoded into a data format compatible with the DVD format, and is subjected to necessary signal processing such as addition of an error correction code.
To supply. The 8-16 modulation circuit 14 performs 8-16 modulation processing on the input data and supplies the data to the recording RF waveform generation circuit 15.

The recording RF waveform generation circuit 15, for example,
A timing pulse generating circuit for generating a timing pulse for controlling the timing of the light emission level of the laser beam based on the 16 modulation data, and a drive for driving the laser diode of the optical head 3 by inputting the timing pulse It is provided with a laser driver and the like for generating a signal. The optical head 3 emits laser light in accordance with the drive signal supplied from the recording RF waveform generation circuit 15, thereby performing data recording on the disk 1 by the phase change method.

The optical system servo circuit 16 generates a focus control signal based on the input focus error signal FE and outputs it to the optical head 3. As a result, the movement of the objective lens of the optical head 3 in the direction of coming and going to the disk is controlled, and the focus servo control is executed. A focus servo control for moving the objective lens in the radial direction of the disk according to tracking by generating a tracking control signal and a sled control signal based on the tracking error signal TE and outputting the generated signal to the optical head 3; The thread servo control for moving the head 3 itself in the disk radial direction is executed.

The spindle servo circuit 17 detects the rotation speed of the spindle motor 2 based on the FG pulse (frequency signal synchronized with the rotation speed) from the spindle motor 2 and the like. By comparing the information with the rotation speed of the spindle motor 2, the spindle motor 2 is accelerated or decelerated based on the error information, thereby realizing a disk rotation operation at a required rotation speed.

The system controller 18 is provided with, for example, a microcomputer, a ROM, a RAM, and the like, and controls each functional circuit unit so that required operations to be performed by the recording / reproducing apparatus are realized.

1-d. Memory Write / Read Control Circuit FIG. 2 is a block diagram showing a configuration example of a memory write / read control circuit provided in the recording / reproducing apparatus having the above-described configuration, for executing memory write / read control on the buffer memory 20. Each block shown in this figure is formed by a partial function circuit unit forming the DVD data decoding circuit 8 and a function circuit unit forming the memory controller 19.

In FIG. 2, the sector address fetch circuit 31 is provided, for example, in the DVD data decoding circuit 8, and inputs the 8-16 demodulated data input from the 8-16 demodulation circuit 7, and Is the sector address (the top 6 of the ID area and IED area shown in FIG. 14).
(A byte area) is extracted and output to the sector address check circuit 32 and the exclusive OR gate 34. The 8-16 demodulated data is branched and supplied to a predetermined signal processing circuit at the subsequent stage, and is stored in the buffer memory 20. In the sector address inspection circuit 32, based on the sector data input from the sector address fetching circuit 31 as described later, the quality of the reproduction data (accuracy and correctness of the reproduction data) obtained at the time of reading the disk is considered. Is inspected as described below. Then, based on the inspection result, if it is determined that the reproduced data at the time of reading the disk is proper, that is, it is determined that the sector has a proper data content, sector address determination determination information is written as the detection result. Connecting sector address register 33 and write connecting pointer register 36
Output to

The sector address from the sector address take-in circuit 31 is supplied to the write connection sector address register 33. The write connection sector address register 33 stores the sector address at the time when the sector address determination information is input. Address fetch circuit 31
Latch the sector address input from. That is,
As long as the data is properly read from the disk and the sector address determination determination information is output, the contents of the write-connected sector address register 33 are sequentially updated. The output of the write connection sector address register 33 is input to an exclusive OR gate 34. The output of the exclusive OR gate 34 is output to the memory access control circuit 35.

In the write link pointer register 36, the value of the write address to the buffer memory 20 generated by the write pointer 37 is fed back. The value of the write address at the time when the sector address determination determination information is input is also latched in the write connection pointer register 36.
When a memory full signal is supplied from the address control circuit 39 and indicates that the storage capacity of the buffer memory is full, the write pointer 37 changes the value of the write address output from the write connection pointer register 36. Load and capture. A read address is generated from the read pointer 38 and the address control circuit 39
Is input to

The address control circuit 39 generates a memory address for specifying an address at the time of writing and reading based on the write address and the read address input as described above. Data write and read positions are controlled. The address control circuit 39 compares the input write address with the read address, and outputs a memory full signal indicating that the buffer memory 20 is full as the load instruction signal as described above. Output to

The memory access control circuit 35 controls the resuming start timing of the writing to the buffer memory after the re-access to the disk is performed in accordance with the output of the exclusive OR gate 34.
That is, when the sector address currently latched in the write-connected sector address register 33 matches the contents of the sector address from the sector address fetch circuit 31, an access signal for requesting the buffer memory 20 to restart writing to the buffer memory is sent to the buffer memory 20. Output to

FIG. 3 shows the detection operation of the sector address check circuit 32 and the setting operation of the write connection pointer of the memory write / read control circuit shown in FIG. As described above, the sector address checking circuit 32 receives 6-byte data from the sector address fetching circuit 31, which is assumed to be located in the sector address area for each sector. Then, in the sector address inspection circuit 32, the next,.
Check the items shown in
From the check result of the item, whether the sector address has been determined as the item, that is, the quality from the viewpoint of whether or not the data in the sector unit has been reproduced with a level of accuracy higher than required at the time of reading the disk. Perform detection. The sector address inspection circuit 32 actually reads the sector number (sector address) in the sector address area and detects the contents of the actually read sector address. For each sector, information on an error detection result (hereinafter, also referred to as an IED result) using the IED in the sector address area is detected. Based on the inspection results of the above items, an inspection is performed as to whether or not continuity of the sector address (sector number) with the preceding sector is established. In this case, both the IED result, which is the check result of the item in the sector unit, and the check result of the item, are OK, and the logical product that the OK result is obtained for two consecutive sectors is obtained. Is OK as the result of the sector address determination. That is, it outputs sector address determination determination information indicating that the sector has been accurately read from the disk.

For example, in the case of FIG.
3 (a) and 3 (b) show the check results of each item.
FIG. 3D shows the result of the sector address determination determination shown in FIG. Note that FIG.
(E) shows a sector address (sector number) obtained by the interpolation protection processing. If the check result and the judgment result of each item are OK, a circle is added,
If it is not OK, it is marked with x. FIG. 3 (f)
2 shows data stored in the buffer memory 20 in sector units.

In the case shown in this figure, as shown in FIG. 3 (a), the sector numbers are continuously and properly (accurately) read from the sector numbers (N) to (N + 3), and the sector numbers (N + 3) are read out. Until FIG. 3 (b) (c)
As shown in the table, the IED result and the continuity check result with the preceding sector are also OK. Therefore, FIG.
The sector address determination determination shown in FIG.
It is OK until 3).

In the sector number (N + 4), as a check item, it is shown that the sector number (N + 4 was properly read, but the IED result was not OK. As a result, FIG. As the result of the sector address determination, it is determined that the result is not OK, and in the subsequent sector number (N + 5), both the IED result and the result of checking the continuity with the preceding sector are O.
It is K. However, the result of the sector address decision determination, which is the item at this time, is the IED
Both the result and the continuity check result of the preceding sector are OK
Is required, the sector address is determined not to be OK.

Further, in the sector that is originally the sector number (N + 6) following the sector number (N + 5), an incorrect sector number (shown as a value M in FIG. 3A) was obtained as a check item of FIG. The result of the continuity check with the preceding sector shown in FIG.
No longer. Here, a state is shown in which the IED result is not OK.

Thereafter, in the sector having the sector number (N + 7), the sector number (N + 7) is properly detected, but the result that the IED result is not OK is obtained. At this time, it is determined that the continuity with the preceding sector is not OK because the previous sector number is invalid. Then, the sector number (N +
8), an incorrect sector number (FIG. 3)
(Shown as a value P in (a)), while the IED result is OK. At this time, as a matter of course, the result of checking the continuity with the preceding sector is not OK. Then, in the sector having the sector number (N + 9), the sector number (N + 9) is properly detected.
The IED result is also OK. However, since the sector number of the preceding sector was incorrect, the result of the continuity check with the preceding sector is not OK. In this case, it is assumed that the buffer memory 20 becomes full at the time when the sector number (N + 9) is stored in the buffer memory as shown by an arrow B in FIG.

By the way, according to the circumstances so far, as a result, the sector address determination decision shown in FIG.
It is determined that the data up to the sector number (N + 3) is OK, and it is determined that the data is not OK after the subsequent sector number (N + 4). In other words, the quality of the reproduced data stored in the buffer memory 20 can be regarded as reliable up to the sector number (N + 3), but the data after the sector number (N + 4) is regarded as reliable. You will not be able to do it.

When the results of the determination so far correspond to the operation of the memory write / read control circuit shown in FIG. 2, the sector number (N + 9) is stored in the memory, and the memory full signal is written from the address control circuit 39. At the time of input to the pointer 37, the write connection pointer register 36 is in a state where the write address at the time of starting the writing of the sector of the sector number (N + 3) for which the final OK sector address determination was obtained is latched. The write address corresponding to the write start position of the sector having the sector number (N + 3) is loaded into the write pointer 37 by the memory full signal which is the load signal. In the present embodiment, at this time, the write address loaded in the write pointer 37 is designated as a write address when writing data obtained by the next disk reproducing operation to the buffer memory. That is, as indicated by the arrow A in FIG. 3F, the sector number (N +
The start address of 3) is determined as a write connection point Point · R which is a next data write connection address.

When the memory full signal is input from the address control circuit 39 to the write pointer 37,
The write connection sector address register 33 is in a state where the sector address of the sector number (N + 3) is latched.

For example, after the memory full signal is output by writing the sector number (N + 9) to the buffer memory 20, the data reading operation to the disk is interrupted and the data stored in the buffer memory 20 is stored in the sector number. That is, reading is performed according to the order. During this time, the memory write / read control circuit of FIG. 2 keeps the above-mentioned information value holding state while writing to the buffer memory 20 is stopped.

The data reading from the buffer memory 20 is performed for a certain period, so that the buffer memory 2
If it is determined at 0 that the data storage capacity is equal to or less than the predetermined amount, the reading of data from the disk D is restarted under the control of the system controller 18, for example. At this time, the system controller 18 determines, for example, the sector (N +) corresponding to the write connection point Point · R.
The access to the disk is controlled so that the data writing to the buffer memory 20 is restarted from 3). That is, for example, the sector (N
A signal read operation is executed by accessing from a recording position before a predetermined sector than (+3). For the access control, the sector to be reproduced is a sector (N +
It is necessary that the system controller 18 recognizes that 3).
Is, for example, when the memory full signal is output,
It is conceivable that the identification is performed from the sector address latched in the writing connection sector address register 33 shown in FIG.

When the reproduction of the disk is resumed as described above, the reproduced data is input to the sector address fetch circuit 31 of FIG. 2, and the sector address of the reproduced sector is exclusive from the sector address fetch circuit 31. The signal is input to the OR gate 34. In the memory access control circuit 35, when a signal corresponding to a state where the sector address from the sector address fetch circuit 31 matches the sector address latched in the write-connecting sector address register 33 is input from the exclusive OR gate 34. , And outputs an access control signal to the buffer memory 20. At this time, as described above, the sector address of the sector (N + 3) for which the sector address determination is finally obtained is latched in the write connection sector address register 33 as described with reference to FIG. Therefore, the memory access control circuit 35 restarts the write operation in the buffer memory at the timing when the sector address from the sector address fetch circuit 31 is set to the sector (N + 3). At this time, as described above, the initial value of the write address of the write pointer is the write connection pointer Point · R shown in FIG.
Data is written to the buffer memory 20 in such a manner that data after the sector (N + 3) read from the disk again is overwritten from the address position of the write connection pointer Point · R.

For example, if it is assumed that the writing of the reproduced data is performed from the position of the sector (N + 9) in FIG. 3 without performing the writing as described above, for example, according to the data detection result shown in FIG. Sector data after sector (N + 4) is relatively unlikely to be properly read from the disk, and even if a disk recording position corresponding to sector (N + 4) or later is accessed, an appropriate sector address is obtained. Likely to not be able to. That is, even if a retry operation is performed on the disk, the sector (N + 9)
It is highly probable that a sector to be connected to is not detected following the operation of the buffer memory 2 in the worst case.
The connection of writing data to 0 is not executed, and the data read from the buffer memory 20 is interrupted.

On the other hand, in the present embodiment, as described with reference to FIG. 3, data quality is detected by using the sector address by the sector address check circuit 32, and the reliability of data reading is determined in accordance with the detection result. The disk access is performed so as to trace back to the sector position which is considered to be highly likely, and data writing is performed. For this reason, the above-described inconvenience is solved, and an appropriate data writing operation to the buffer memory 20 can be obtained almost stably.

The method of detecting the data quality in the sector address inspection circuit 32 (criterion for determining the sector address determination) is not limited to the method described above with reference to FIG. The number of consecutive times that both the IED result as the check result of the item and the check result of the item are OK may be set arbitrarily according to the actual conditions and the like. It is also conceivable that the sector address determination is made based only on the IED result or the continuity result of the preceding sector. Further, regarding the continuity of the preceding sector, the condition of the number of continuous sectors until an OK result is output may be appropriately changed. These settings should be set depending on how much error in reproduced data poses a practical problem. In the description so far, the case of reproducing a disc as a DVD-RW has been taken as an example.
Since it is compatible with M, a sector address is inserted into data in the DVD-ROM according to the same structure. Therefore, the recording / reproducing apparatus of the present embodiment
It is possible to play back VD-ROMs,
Even when the VD-ROM is reproduced, the above-described writing and linking operation to the buffer memory is performed properly.

(2. Second Embodiment (CD Player)) 2-a. Subcode Format Next, a case where the present invention is applied to a CD player will be described as a second embodiment.
About subcode format in CD
This will be described with reference to FIG.

For example, as is well known, CD
The minimum unit of data recorded in (video CD, CD-DA, etc.) is one frame. One block is composed of 98 frames.

The structure of one frame is as shown in FIG.
One frame is composed of 588 bits. The first 24 bits are synchronous data, and the following 14 bits are a subcode data area. After that, data and parity are set.

One frame is composed of 98 frames, and the subcode data extracted from the 98 frames are collected to form one block as shown in FIG.
The subcode data of the block is formed. The first and second frames (frame 98n +
1, the subcode data from the frame 98n + 2) is a synchronization pattern. Then, from the third frame to the 98th frame (frames 98n + 3 to 98n +
Up to 98), 96-bit channel data, that is, P, Q, R, S, T, U, V, and W subcode data are formed.

Of these, P for managing access and the like
Channel and Q channel are used. However, the P channel only shows a pause portion between tracks, and more detailed control is performed for the Q channel (Q1 to Q1).
Q96). The 96-bit Q channel data is configured as shown in FIG.

First, the four bits Q1 to Q4 are used as control data, and are used for the number of audio channels, emphasis, identification of a CD-ROM, and the like. That is, the 4-bit control data is defined as follows. "0 ****" ... 2 channel audio "1 **" ... 4 channel audio "* 0 **" ... CD-DA "* 1 **" ... CD -ROM "** 0 *" ... Digital copy not possible "** 1 *" ... Digital copy possible "**** 0" ... No pre-emphasis "**** 1"・ With pre-emphasis

Next, the four bits Q5 to Q8 are used as addresses, which are control bits for the sub-Q data. When the address 4 bits are "0001", it indicates that the subsequent sub-Q data of Q9 to Q80 is audio Q data, and when it is "0100",
Subsequent Q data of Q9 to Q80 is video Q data. Q9 to Q80 form 72-bit sub-Q data, and the remaining Q81 to Q96 are CRC.

In the lead-in area, the sub-Q data recorded therein becomes the TOC information. That is, the 72-bit sub Q data of Q9 to Q80 in the Q channel data read from the lead-in area is:
It has information as shown in FIG. Sub Q
The data has data of 8 bits each.

First, the track number is recorded. In the lead-in area, the track number is fixed to “00”. Next, POINT (point) is described, and MIN (minute), SEC
(Second) and FRAME (frame number) are shown. Further, PMIN, PSEC, and PFRAME are recorded.
The meaning is determined by the value of NT.

When the value of POINT is "01" to "99", the value indicates the track number.
In IN, PSEC, and PFRAME, the start point (absolute time address) of the track of the track number is recorded as minute (PMIN), second (PSEC), and frame number (PFRAME).

When the value of POINT is "A0", PM
The track number of the first track is recorded in IN.
In addition, CD-DA, CD-I, C
A distinction is made between D-ROMs (XA specification). POINT
Is "A1", the track number of the last track is recorded in PMIN. If the value of POINT is "A
In the case of "2", the start point of the lead-out area is indicated as an absolute time address in PMIN, PSEC, and PFRAME.

In the tracks # 1 to #n and the lead-out area, the sub-Q data recorded therein has the information shown in FIG. First, the track number is recorded. That is, in each of tracks # 1 to #n, "01" to "9"
9 ”. In the lead-out area, the track number is "AA". Subsequently, information that allows each track to be further subdivided is recorded as an index.

Then, as the elapsed time in the track, MI
N (minute), SEC (second), FRAME (frame number)
Is shown. Furthermore, AMIN, ASEC, AFRAM
As E, the absolute time address is minutes (AMIN), seconds (A
SEC) and the frame number (AFRAME). As can be seen from this data structure, for example, C
If the data reproduced from D is identified for its continuity and the like, the data area (tracks # 1 to #
In n), it becomes possible by monitoring AMIN, ASEC, (and AFRAME) of the sub-Q data indicating the absolute time address. That is, it can be used for detecting the quality of reproduced data described later.

2-b. CD Player FIG. 15 is a block diagram showing a configuration of a main part of a CD player according to the present embodiment. The disk D inserted in the reproducing apparatus shown in this figure is loaded in the disk driver 201 and driven for reproduction. The disc driver 201 shown in FIG. 1 includes a loading mechanism for loading and unloading a disc, a spindle motor 202 as a disc rotation driving mechanism, and an optical head 203. The spindle motor 202 rotates the disc in a CAV or CLV format. In this state, laser light is emitted from the optical head 203, and a detection signal corresponding to the reflected light is obtained, whereby information from the disk D is read. The current signal, which is the detection information of the reflected light, is supplied from the optical head 203 to the RF matrix amplifier 204, where the current-voltage conversion,
Amplification, arithmetic processing, and the like are performed, and various signals are generated.

In the RF matrix amplifier 204, the reproduction R
An F signal, a focus error signal, a tracking error signal, and the like are generated.
04 is output to the binarization circuit 205 and the servo circuit unit 20.
8 is supplied.

The binarization circuit 205 binarizes the reproduced RF signal input from the RF matrix amplifier 204 and outputs the binarized signal to the EFM decoding / signal processing circuit 206. The EFM decoding / signal processing circuit 206 performs EFM demodulation processing, error correction processing, and other necessary signal processing on the input binary RF signal, and decodes information read from the disc into audio data. .
Further, based on the data signal obtained by the EFM demodulation, extraction of subcode and address data, extraction of rotation speed information, and the like are performed, and the information is supplied to the controller 207 and the servo circuit unit 208.

The audio signal data output from the EFM decode / signal processing circuit 206 is
9 is temporarily stored in the buffer memory 210. Then, the data is read from the buffer memory 210 at a predetermined timing and transmitted to the interface circuit 9.

The buffer memory 210 is constituted by a D-RAM or the like, and has a storage capacity sufficient to obtain a required data storage amount. In this case, a larger capacity may be used, and it is not always necessary to use a D-RAM.

Also in this case, as in the first embodiment, by performing a reproducing operation using the buffer memory 210, an anti-vibration function (ESP function) is obtained. That is, the processing from the optical head 203 to the EFM decoding / signal processing circuit 206 is performed at a high rate, and the signal processing data (reproduced sound data) is stored in the buffer memory 210.
Write to. On the other hand, reading from the buffer memory 210 is performed at a normal rate under the control of the memory controller 209. Data read from the memory controller 209 is converted into an analog signal by the D / A converter 211 according to the normal rate. And supplies the reproduced audio signal to the audio signal output terminal 210. As a result, a normal speed and pitch can be obtained as the audio signal output from the audio signal output terminal 212.

Also in this case, a certain amount of data is always accumulated in the buffer memory 210 due to the difference between the write bit rate and the read bit rate of the buffer memory 210. Even if the reading of data from the disk D by the head 203 is temporarily interrupted, the reading from the buffer memory 210 can be continued, so that the reproduced data is continuously output without interruption. Then, the optical head 203 accesses an appropriate position while the reproduction by the stored data is continued, and resumes the data reading.

The servo circuit unit 208 calculates the focus, tracking, thread, and spindle from the focus error signal and tracking error signal supplied from the RF matrix amplifier 204 and the spindle error signal supplied from the EFM decoding / signal processing circuit 6. Of the disk drive 1 to execute the servo operation related to the disk reproduction operation. The controller 207 includes a microcomputer, a RAM, and the like, and controls various playback operations of the playback device.

2-c. Memory Write / Read Control Circuit FIG. 16 is a block diagram showing a configuration example of a memory write / read control circuit that is provided in the CD player device having the above configuration and executes memory write / read control on the buffer memory 210. Each block shown in this figure is formed by a partial function circuit unit forming the EFM decoding / signal processing circuit 206 and a function circuit unit forming the memory controller 209. In this case, for example, the EFM demodulation circuit 220 and the subcode capture circuit 2
21 is provided in the EFM decoding / signal processing circuit 206, and other respective functional circuit units are provided in the memory controller 209.

In the EFM demodulation circuit 220, the binarization circuit 2
05, and performs EFM decoding processing to output the binary RF signal as EFM demodulated data. The EFM demodulated data is supplied to the subcode capture circuit 22.
1 is supplied. Further, the signal is branched and supplied to a predetermined signal processing circuit at the subsequent stage, and is stored in the buffer memory 210.

The sub code fetch circuit 221 has
FM demodulated data is input, and sub-Q data (see FIG. 19 and FIG. 20) is fetched and output for each block from this data, for example. Note that the subcode inspection circuit 2 provided in the memory controller 209 in FIG.
Each functional circuit unit from 22 to the address control circuit 229
For example, when compared with the functional circuit sections from the sector address check circuit 32 to the address control circuit 39 in the memory write / read control circuit shown in FIG. 2 as the first embodiment, it should be used to determine the quality of reproduced data. Except that the data is configured as sub-Q data instead of the sector address, the configuration is the same, and therefore the description is omitted here.

FIG. 17 shows the detection operation of the subcode inspection circuit 222 and the setting operation of the write connection pointer of the memory write / read control circuit shown in FIG. Also in this figure, the subcode determination determination method of the subcode check circuit 222 is based on the sector address determination determination method shown in FIG. 3 in the first embodiment. That is, the sub-code checking circuit 222 checks the following items based on the input sub-Q data, and, based on the check results of these items, the sub-Q data in block units Is detected, that is, whether or not the data in block units has been reproduced without error at the time of reading the disk. The sub code inspection circuit 222 reads the actually input sub Q data (absolute time) and detects the contents of the actually read sub Q data. CRC in each block unit (see FIG. 19B)
Error detection result (hereinafter also referred to as CRC result)
Is detected for the information. Based on the inspection result of the above items, an inspection is performed as to whether or not continuity of the sub Q data (absolute time) with the preceding block is established. In this case, both the CRC result, which is the check result of the item in the block unit, and the check result of the item are OK, and the logical product that the OK result is obtained for two consecutive blocks is obtained. Is OK as the subcode determination result. That is, sub Q
Based on the state of the data, indicates that the data in block units has been properly read from the disk,
Outputs subcode determination determination information.

In FIGS. 3 and 17, the quality of the reproduction data is determined based on the data contents shown in FIG. 19 instead of the sector address, and the reproduction data and the data stored in the buffer memory are used. 17 (a) to 17 (f), except that they are handled in block units instead of sector units.
3 (a) to 3 (f). Further, for the sake of convenience, the check results of the check items shown in FIGS. 17 (a) to 17 (d) and the subcode determination result are also shown in FIG. 3 (a) to FIG. 3 (d). Is the same as the check result and the sector address decision determination result. It should be noted that the sub-Q data read by the sub-code checking circuit 222 as shown in FIG. 17A is actually absolute time address information, but here, for convenience of explanation, the absolute time address as the sub-Q data is used. Is associated with the address (block number) of the block to which the absolute time address belongs.

As described above, a CD player can be configured to detect the quality of reproduced data based on sub-Q data as shown in FIGS. 16 and 17. When a subcode determination result as shown in FIG. 17 (d) is obtained, as in the case of the first embodiment described with reference to FIG. Before the full signal is obtained, the data of the block (N + 3) and subsequent blocks obtained by the operation of resuming the disk reproduction is written from the start address of the block (N + 3) where the subcode determination result was obtained last. You. As a result, the same operation and effect as in the first embodiment can be obtained. In the second embodiment as well, the method of detecting the quality of the reproduced data is appropriately determined in consideration of factors such as how much error in the reproduced data causes a problem in the writing operation to the buffer memory in practical use. It only has to be set.

The present invention is not limited to the configuration according to each of the above embodiments, but can be variously modified.
For example, the present invention can be applied to a reproducing apparatus corresponding to various recording media as long as it corresponds to a recording medium having a data structure in which data that can identify the continuity of reproduced data is inserted.

[0102]

As described above, according to the present invention, the quality of reproduced data to be written into the buffer memory is detected, and the write connection address corresponding to the reproduced data meeting a predetermined condition is determined. In this case, since the data to be written at the determined write connection address has a data quality of a predetermined level or higher, there is a possibility that the data will be read properly when reproduced from the recording medium. Very high. In other words, in the writing connection process to the buffer memory, the possibility that the process of reproducing necessary data by accessing the disk and writing it to the buffer memory is very likely to be executed without failure, and thus the reproduced data is increased accordingly. The effect of improving the reliability of is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a recording / reproducing apparatus according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a memory write / read control circuit according to the first embodiment;

FIG. 3 is an explanatory diagram showing an example of a sector address determination determination operation and an example of a writing link pointer setting operation in the first embodiment.

FIG. 4 is an explanatory diagram of a wobbling pre-groove of a disc corresponding to the first embodiment.

FIG. 5 is an explanatory diagram of a CAV format of a wobbling address corresponding to the first embodiment.

FIG. 6 is an explanatory diagram of a segment of a wobbling address of a disk corresponding to the first embodiment.

FIG. 7 is an explanatory diagram of a frame structure of a wobbling address of a disk corresponding to the first embodiment.

FIG. 8 is an explanatory diagram showing a data structure recorded on a disc corresponding to the first embodiment.

FIG. 9 is an explanatory diagram of a sector format.

FIG. 10 is an explanatory diagram of a data configuration of 32 Kbytes.

FIG. 11 is an explanatory diagram of a state where outer codes are interleaved.

FIG. 12 is an explanatory diagram of a configuration of block data.

FIG. 13 is an explanatory diagram showing a sector structure.

FIG. 14 is an explanatory diagram showing the structure of a sector address area in a sector.

FIG. 15 is a block diagram illustrating a configuration of a CD player according to a second embodiment.

FIG. 16 shows a memory write / memory according to the second embodiment.
FIG. 3 is a block diagram illustrating a configuration of a read control circuit.

FIG. 17 is an explanatory diagram illustrating an example of a sector address determination determination operation and an example of a writing link pointer setting operation according to the first embodiment.

FIG. 18 is an explanatory diagram of a frame structure of a disk.

FIG. 19 is an explanatory diagram of a subcode data structure.

FIG. 20 is an explanatory diagram of sub-Q data.

[Explanation of symbols]

1 disk, 2 spindle motor, 3 optical head, 4 RF matrix amplifier, 5 RF waveform processing circuit, 6 RF-PLL circuit, 78-16 demodulation circuit, 8
DVD data decoding circuit, 9 interface circuit, 10 wobble waveform processing circuit, 11 playback / recording position management circuit, 12 recording clock generation circuit, 13 DVD
Data encoding circuit, 148-16 modulation circuit, 15
Recording RF waveform generation circuit, 16 optical system servo circuit,
17 spindle servo circuit, 18 system controller, 19 memory controller, 20 buffer memory, 31 sector address take-in circuit, 32 sector address inspection circuit, 33 write connection sector address register, 35 memory access control circuit, 36 pointer register, 37 write pointer, 38 read pointer, 39 address control circuit, 100 pregroup, 101 land, 201 disk driver, 20
2 spindle motor, 203 optical head, 204
RF matrix amplifier, 205 binarization circuit, 206
EFM decoding / signal processing circuit, 207 controller,
208 servo circuit section, 209 memory controller,
210 buffer memory, 212 audio signal output terminal, 2
11 D / A converter, 220 EFM demodulation circuit, 2
21 Subcode capture circuit, 222 Subcode inspection circuit, 226 Write connection pointer register, 227
Write pointer, 228 Read pointer, 229
Address control circuit

Claims (2)

[Claims] 1. A data reproducing means for reproducing data from a predetermined type of recording medium; a data storing means for storing reproduced data obtained by the data reproducing means; Data writing / reading means for writing data to the data storage means and reading data from the data storage means at a read-compatible transfer rate lower than the write-compatible transfer rate; Extracting the data whose contents are set according to the above, and extracting the extracted data as the data for the quality detection, from the reproduction data written to the data storage means by the data extraction means for the quality detection The extracted quality detection data is entered. A reproduction data quality determining means for determining the quality of the reproduction data according to a predetermined rule based on the input quality detection data; and a writing connection to the data storage means based on the determination result of the reproduction data quality determination means. Writing data determining means for determining a logical start position of reproduced data to be performed, and writing when writing is to be performed on the data storage means based on the determination result of the reproduced data quality determining means. A writing start address determining means for determining a connection start address, wherein the data writing / reading means, at the start of the data writing connection, the write connection start address determined by the writing connection start address determining means. The data writing is started from the logical start position of the reproduction data determined by the writing connection data determining means. A playback device configured to execute recording. 2. A data write / read control process for writing data to a data storage area at a predetermined write transfer rate and reading data from the data storage area at a read transfer rate lower than the write transfer rate. From the reproduced data, extracting data whose content is set in accordance with a predetermined definition, and extracting the extracted data as data for detecting quality, and extracting the data for quality detection. A reproduction data quality determination process for acquiring the quality detection data extracted from the reproduction data written to the data storage area and determining the quality of the reproduction data according to a predetermined rule based on the acquired quality detection data; Based on the judgment result of the judgment process, the above data A write splicing data determination process for determining a logical start position of reproduced data to be written and spliced to the product region; and a write splicing process to the data storage region based on a determination result of the reproduced data quality determination process. And a write connection start address determination process for determining a write connection start address when data writing is to be performed. As the data write / read process, at the start of data write connection, the write connection start address determination is performed. Data storage, characterized in that data writing is executed from the logical start position of the reproduction data determined by the above-described write connection data determination processing to the write connection start address determined by the processing. Method.