JPH11135907A - Wiring circuit board structure equipped with test electrode - Google Patents
Wiring circuit board structure equipped with test electrodeInfo
- Publication number
- JPH11135907A JPH11135907A JP29984097A JP29984097A JPH11135907A JP H11135907 A JPH11135907 A JP H11135907A JP 29984097 A JP29984097 A JP 29984097A JP 29984097 A JP29984097 A JP 29984097A JP H11135907 A JPH11135907 A JP H11135907A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- test
- wiring circuit
- circuit board
- test electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、半導体装置や配線
回路基板の導通検査をするために用いられる検査治具基
板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inspection jig substrate used for conducting a continuity inspection of a semiconductor device or a printed circuit board.
【0002】[0002]
【従来技術】従来の半導体装置や配線回路基板の導通検
査に用いられている検査電極を有する配線回路基板構造
は、配線回路基板上に検査電極が配置されており、被検
査体の検査電極に押し当てることによって導通検査を行
っていた。2. Description of the Related Art In a conventional printed circuit board structure having test electrodes used for testing the continuity of a semiconductor device or a printed circuit board, the test electrodes are arranged on the printed circuit board, and the test electrodes of the object to be tested are used as test electrodes. The continuity test was performed by pressing.
【0003】従来の検査電極を有する配線回路基板構造
では検査電極を被検査体の電極に押し当てて電気的導通
を取っていたが、検査電極は被検査体の電極に垂直に押
し当てられるだけであるため、被検査体の電極がアルミ
や銅などの酸化し易い材質で形成されている場合には、
被検査体の電極の酸化膜を破ることができず、検査時に
接触不良が発生するという問題がある。In the conventional printed circuit board structure having test electrodes, the test electrodes are pressed against the electrodes of the device under test to establish electrical continuity. However, the test electrodes are only pressed perpendicularly to the electrodes of the device under test. Therefore, if the electrode of the test object is formed of easily oxidizable material such as aluminum or copper,
There is a problem that the oxide film of the electrode of the test object cannot be broken, and a contact failure occurs during the test.
【0004】[0004]
【発明が解決しようとする課題】本発明は上記問題点に
鑑みなされたもので、アルミや銅などの表面が酸化し易
い材質で形成されている被検査体の電極の導通検査を行
う際検査電極と被検査体の電極との電気的導通が確実に
行える検査電極を有する配線回路基板を提供することで
ある。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has been made in consideration of a continuity test of an electrode of a test object whose surface is formed of a material such as aluminum or copper which is easily oxidized. An object of the present invention is to provide a printed circuit board having an inspection electrode capable of reliably performing electrical conduction between an electrode and an electrode of a device under test.
【0005】[0005]
【課題を解決するための手段】本発明において上記課題
を解決するため、請求項1においては、絶縁基板の片面
に検査電極が、もう一方の面に配線回路パターンが形成
された配線回路基板であって、前記検査電極は絶縁基板
を介して前記配線回路パターンと電気的に接続されてお
り、前記検査電極基端部の片側のみで配線回路パターン
と接続され、且つ前記検査電極基端部及び配線回路パタ
ーンが形成されている面の前記絶縁基板上に所定厚の絶
縁層が形成されていることを特徴とする検査電極を有す
る配線回路基板構造としたものである。In order to solve the above-mentioned problems in the present invention, according to a first aspect of the present invention, there is provided a printed circuit board having a test electrode formed on one surface of an insulating substrate and a printed circuit pattern formed on the other surface. The inspection electrode is electrically connected to the wiring circuit pattern via an insulating substrate, is connected to a wiring circuit pattern only on one side of the inspection electrode base end, and the inspection electrode base end and An insulating layer having a predetermined thickness is formed on the insulating substrate on a surface on which a wiring circuit pattern is formed.
【0006】[0006]
【発明の実施の形態】図1に本発明の検査電極を有する
配線回路基板構造を示す部分断面図を、図2に本発明の
検査電極を有する配線回路基板構造を用いて被検査体の
電極に所定の荷重を架けて導通検査を行っている状態を
示す模式断面図を、それぞれ示す。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a partial cross-sectional view showing the structure of a printed circuit board having test electrodes of the present invention. FIG. 1 is a schematic cross-sectional view showing a state in which a continuity test is being performed with a predetermined load applied to each of them.
【0007】本発明の検査電極を有する配線回路基板構
造は図1に示すように、検査電極19と配線回路パター
ン17が絶縁基板11を介して電気的に接続されてお
り、検査電極基端部19bの片側のみで配線回路パター
ン17と接続され、さらに検査電極基端部19bと配線
回路パターン17が形成されている面の絶縁基板11上
に絶縁層18が形成されている。As shown in FIG. 1, the printed circuit board structure having test electrodes according to the present invention has a structure in which a test electrode 19 and a printed circuit pattern 17 are electrically connected to each other through an insulating substrate 11, and a test electrode base end portion. The insulating layer 18 is formed on the insulating substrate 11 on the surface on which the test electrode base end 19b and the wiring circuit pattern 17 are formed, being connected to the wiring circuit pattern 17 only on one side of the wiring substrate 19b.
【0008】図2に示すように、検査電極19と被検査
体21の電極22との間に所定の荷重をかけると、検査
電極19の基端部19bは配線回路パターン17のない
絶縁層18に沈み込み、検査電極19の先端部19aは
配線回路パターン17と反対方向に傾きながら被検査体
21の電極22表面を擦るように動く。これにより被検
査体21の電極22表面の酸化膜が破られ、検査電極1
9と被検査体21の電極22との確実な電気的導通をと
ることができる。As shown in FIG. 2, when a predetermined load is applied between the inspection electrode 19 and the electrode 22 of the device under test 21, the base end 19 b of the inspection electrode 19 becomes the insulating layer 18 without the wiring circuit pattern 17. The tip 19 a of the test electrode 19 moves so as to rub the surface of the electrode 22 of the device under test 21 while tilting in the opposite direction to the wiring circuit pattern 17. As a result, the oxide film on the surface of the electrode 22 of the test object 21 is broken, and the test electrode 1
9 and the electrode 22 of the device under test 21 can be reliably electrically connected.
【0009】以下、本発明の検査電極を有する配線回路
基板構造の形成法について述べる。まず、絶縁基板11
上にレジスト層12を形成し金属基板13を貼りつける
(図3(a)参照)。絶縁基板11としては絶縁性、耐
熱性を有するポリイミドフィルム等が、レジスト層12
は厚みの均一なドライフィルムレジストが好適である。
さらに、金属基板13としては後工程を考慮した場合ス
テンレス基板が好都合である。ここで、レジスト層12
としてドライフィルムレジストを使用した場合接着層と
しての機能も有しているため、容易に金属基板13を積
層できるメリットを有する。Hereinafter, a method for forming a printed circuit board structure having an inspection electrode according to the present invention will be described. First, the insulating substrate 11
A resist layer 12 is formed thereon, and a metal substrate 13 is attached (see FIG. 3A). As the insulating substrate 11, a polyimide film or the like having insulating properties and heat resistance is used.
Is preferably a dry film resist having a uniform thickness.
Furthermore, a stainless steel substrate is advantageous as the metal substrate 13 in consideration of a post-process. Here, the resist layer 12
In the case where a dry film resist is used, it also has a function as an adhesive layer, and thus has an advantage that the metal substrate 13 can be easily laminated.
【0010】次に、絶縁基板11及びレジスト層12の
所定位置にレーザ加工機を用いて開口部14を形成する
(図3(b)参照)。レーザ加工機としてはエキシマレ
ーザ加工機或いは炭酸ガスレーザ加工機を用いることが
できる。Next, openings 14 are formed at predetermined positions of the insulating substrate 11 and the resist layer 12 by using a laser processing machine (see FIG. 3B). An excimer laser machine or a carbon dioxide laser machine can be used as the laser machine.
【0011】次に、開口部14に電解めっきにて導体電
極15を形成する(図3(c)参照)。電解めっきは電
極の材質によって異なるが、電解銅めっきや電解ニッケ
ルめっきなどを用いて導体電極を形成することができ
る。ここで、導体電極の厚さはレジスト層12の厚さと
絶縁基板11の1/2の厚さを合計した値が好適であ
る。Next, a conductor electrode 15 is formed in the opening 14 by electrolytic plating (see FIG. 3C). Electrolytic plating differs depending on the material of the electrode, but the conductor electrode can be formed by using electrolytic copper plating, electrolytic nickel plating, or the like. Here, the thickness of the conductor electrode is preferably a value obtained by summing the thickness of the resist layer 12 and half the thickness of the insulating substrate 11.
【0012】次に、絶縁基板11及び導体電極15上に
スパッタ装置を用いて3000Å厚の銅の薄膜導体層を
形成する。さらに、セミアディティブ法にて配線回路パ
ターンを形成するためのレジストパターン16を形成す
る(図3(d)参照)。Next, a copper thin film conductor layer having a thickness of 3000 mm is formed on the insulating substrate 11 and the conductor electrode 15 by using a sputtering apparatus. Further, a resist pattern 16 for forming a wiring circuit pattern is formed by a semi-additive method (see FIG. 3D).
【0013】次に、電解銅メッキにてレジストパターン
16をマスクにして薄膜導体層上に15μm厚の銅の導
体層を形成し、専用の剥離液でレジストパターン16を
剥離した後レジストパターン16の下部にあった薄膜導
体層をエッチングで除去し、導体電極15と電気的に接
続された配線回路パターン17を作製する(図3(e)
参照)。Next, a copper conductor layer having a thickness of 15 μm is formed on the thin film conductor layer by electrolytic copper plating using the resist pattern 16 as a mask. The thin film conductor layer at the lower portion is removed by etching to produce a wiring circuit pattern 17 electrically connected to the conductor electrode 15 (FIG. 3E).
reference).
【0014】次に、熱硬化型のエポキシ樹脂又はポリイ
ミド樹脂をスクリーン印刷あるいはスピンコートによっ
て塗布し、加熱硬化して絶縁層18を形成する(図3
(f)参照)。Next, a thermosetting epoxy resin or a polyimide resin is applied by screen printing or spin coating, and is cured by heating to form an insulating layer 18 (FIG. 3).
(F)).
【0015】最後に、苛性ソーダ溶液に基板を浸せき
し、金属基板13及びレジスト層12を除去することに
より、本発明の電極を有する配線回路基板を形成するこ
とができる(図3(g)参照)。Finally, the printed circuit board having the electrodes of the present invention can be formed by immersing the substrate in a caustic soda solution and removing the metal substrate 13 and the resist layer 12 (see FIG. 3 (g)). .
【0016】[0016]
【実施例】以下実施例により本発明を図面を用いて詳細
に説明する。まず、25μm厚のポリイミドフィルムか
らなる絶縁基板11上に50μm厚のドライフィルムレ
ジスト(DFR:日立化成工業(株)製)をラミネータ
を使用して貼り付け、レジスト層12を形成した。さら
に、レジスト層12を接着層として0.3mm厚のステ
ンレス板からなる金属基板13を貼り付けた(図3
(a)参照)。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings. First, a 50 μm-thick dry film resist (DFR: manufactured by Hitachi Chemical Co., Ltd.) was attached on an insulating substrate 11 made of a 25 μm-thick polyimide film using a laminator to form a resist layer 12. Further, a metal substrate 13 made of a stainless steel plate having a thickness of 0.3 mm was attached using the resist layer 12 as an adhesive layer (FIG. 3).
(A)).
【0017】次に、絶縁基板11及びレジスト層12の
所定位置にエキシマレーザ加工機を用いて40μmφの
開口部14を形成した(図3(b)参照)。エキシマレ
ーザ加工機の加工条件は、エネルギ密度1.5J/cm
2 で行った。Next, an opening 14 having a diameter of 40 μm was formed at a predetermined position of the insulating substrate 11 and the resist layer 12 by using an excimer laser processing machine (see FIG. 3B). The processing conditions of the excimer laser processing machine are the energy density of 1.5 J / cm
2 went.
【0018】次に、金属基板13をめっき電極とし電解
Niめっきによって開口部14に63μm厚のニッケル
金属からなる導体電極15を形成した(図3(c)参
照)。Next, a conductive electrode 15 made of nickel metal having a thickness of 63 μm was formed in the opening 14 by electrolytic Ni plating using the metal substrate 13 as a plating electrode (see FIG. 3C).
【0019】次に、絶縁基板11及び導体電極15上に
スパッタ装置を用いて3000Å厚の銅の薄膜導体層を
形成した。さらに、セミアディティブ法にて配線回路パ
ターンを形成するためのレジストパターン16を形成し
た(図3(d)参照)。Next, a thin copper conductor layer having a thickness of 3000 mm was formed on the insulating substrate 11 and the conductor electrodes 15 by using a sputtering apparatus. Further, a resist pattern 16 for forming a wiring circuit pattern was formed by a semi-additive method (see FIG. 3D).
【0020】次に、電解銅メッキにてレジストパターン
16をマスクにして薄膜導体層上に15μm厚の銅の導
体層を形成し、レジストパターン16を専用剥離液にて
剥離し、レジストパターン16の下部にあった薄膜導体
層をエッチングにて除去し、導体電極15と電気的に接
続された配線回路パターン17を作製した(図3(e)
参照)。Next, a copper conductor layer having a thickness of 15 μm is formed on the thin film conductor layer by electrolytic copper plating using the resist pattern 16 as a mask, and the resist pattern 16 is peeled off with a dedicated peeling liquid. The thin film conductor layer underneath was removed by etching to produce a wiring circuit pattern 17 electrically connected to the conductor electrode 15 (FIG. 3E).
reference).
【0021】次に、熱硬化型のエポキシ樹脂溶液をスク
リーン印刷によって塗布し、加熱硬化して絶縁層18を
形成した(図3(f)参照)。Next, a thermosetting epoxy resin solution was applied by screen printing, and heat-cured to form an insulating layer 18 (see FIG. 3F).
【0022】最後に、上記基板を10%の苛性ソーダ溶
液に浸せきし、金属基板13及びレジスト層12を除去
することにより、本発明の検査電極を有する配線回路基
板を得ることができた(図3(g)参照)。Finally, the substrate was immersed in a 10% caustic soda solution, and the metal substrate 13 and the resist layer 12 were removed to obtain a printed circuit board having the test electrodes of the present invention (FIG. 3). (G)).
【0023】本発明の検査電極を有する配線回路基板を
用いてシリコンウェハ上に形成されたAl電極の導通検
査を行ったところ、従来の電極構造では導通が行えなか
った1電極当たり5g程度の荷重でも十分電気的導通が
得られることが確認された。When a continuity test was performed on an Al electrode formed on a silicon wafer using the printed circuit board having the test electrode of the present invention, a load of about 5 g per electrode, which could not be conducted with the conventional electrode structure, was obtained. However, it was confirmed that sufficient electrical continuity was obtained.
【0024】[0024]
【発明の効果】本発明の検査電極を有する配線回路基板
を用いることにより、被検査体の電極が容易に酸化する
材質であっても電極先端部が酸化膜を破るように動作す
るため、従来の測定荷重よりも少ない荷重で電気的導通
を得ることができ、問題となっていた接触不良を大幅に
改善することができる。また、測定時の荷重が減少する
ため電極の潰れや変形が発生しにくくなり、電極寿命を
延ばす効果も生まれる。さらに検査基板の寿命も向上す
るため、検査コストの低減が計れる。By using the printed circuit board having the inspection electrode of the present invention, the tip of the electrode operates so as to break the oxide film even if the electrode of the object to be inspected is made of a material which is easily oxidized. , Electrical conduction can be obtained with a load smaller than the measured load, and the problem of poor contact can be greatly improved. Further, since the load at the time of measurement is reduced, the electrode is less likely to be crushed or deformed, and the effect of extending the electrode life is also produced. Furthermore, since the life of the inspection board is also improved, the inspection cost can be reduced.
【図1】本発明の検査電極を有する配線回路基板の構成
を示す模式断面図である。FIG. 1 is a schematic sectional view showing the configuration of a printed circuit board having an inspection electrode according to the present invention.
【図2】本発明の検査電極を有する配線回路基板を用い
て被検査体の電極に所定の荷重をかけて導通検査を行っ
ている状態を示す模式断面図である。FIG. 2 is a schematic cross-sectional view showing a state where a continuity test is performed by applying a predetermined load to an electrode of a device under test using a printed circuit board having a test electrode of the present invention.
【図3】(a)〜(g)は、本発明の検査電極を有する
配線回路基板の製造工程を示す部分断面図である。3 (a) to 3 (g) are partial cross-sectional views showing steps of manufacturing a printed circuit board having an inspection electrode according to the present invention.
11……絶縁基板 12……レジスト層 13……金属基板 14……開口部 15……導体電極 16……レジストパターン 17……配線回路パターン 18……絶縁層 19……検査電極 19a……検査電極基端部 19b……検査電極先端部 21……被検査体 22……電極 11 insulating substrate 12 resist layer 13 metal substrate 14 opening 15 conductive electrode 16 resist pattern 17 wiring circuit pattern 18 insulating layer 19 inspection electrode 19a inspection Electrode base end 19b ... Test electrode tip 21 ... Test object 22 ... Electrode
Claims (1)
面に配線回路パターンが形成された配線回路基板であっ
て、前記検査電極は絶縁基板を介して前記配線回路パタ
ーンと電気的に接続されており、前記検査電極基端部の
片側のみで配線回路パターンと接続され、且つ前記検査
電極基端部及び配線回路パターンが形成されている面の
前記絶縁基板上に所定厚の絶縁層が形成されていること
を特徴とする検査電極を有する配線回路基板構造。1. A printed circuit board having test electrodes formed on one surface of an insulating substrate and a printed circuit pattern formed on the other surface, wherein the test electrodes are electrically connected to the printed circuit pattern via the insulating substrate. An insulating layer having a predetermined thickness connected to a wiring circuit pattern only on one side of the test electrode base end, and having a predetermined thickness on the insulating substrate on a surface where the test electrode base end and the wiring circuit pattern are formed; A printed circuit board structure having a test electrode, wherein a printed circuit board is formed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29984097A JPH11135907A (en) | 1997-10-31 | 1997-10-31 | Wiring circuit board structure equipped with test electrode |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29984097A JPH11135907A (en) | 1997-10-31 | 1997-10-31 | Wiring circuit board structure equipped with test electrode |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH11135907A true JPH11135907A (en) | 1999-05-21 |
Family
ID=17877568
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP29984097A Pending JPH11135907A (en) | 1997-10-31 | 1997-10-31 | Wiring circuit board structure equipped with test electrode |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH11135907A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005026598A (en) * | 2003-07-01 | 2005-01-27 | Tokyo Electron Ltd | Member for multilayer wiring substrate, its manufacturing method and multilayer wiring substrate |
CN110519916A (en) * | 2019-08-14 | 2019-11-29 | 云谷(固安)科技有限公司 | A kind of flexible circuit board and compression bonding apparatus |
-
1997
- 1997-10-31 JP JP29984097A patent/JPH11135907A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005026598A (en) * | 2003-07-01 | 2005-01-27 | Tokyo Electron Ltd | Member for multilayer wiring substrate, its manufacturing method and multilayer wiring substrate |
CN110519916A (en) * | 2019-08-14 | 2019-11-29 | 云谷(固安)科技有限公司 | A kind of flexible circuit board and compression bonding apparatus |
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