JPH11135532A - Semiconductor chip and semiconductor device - Google Patents
Semiconductor chip and semiconductor deviceInfo
- Publication number
- JPH11135532A JPH11135532A JP9314228A JP31422897A JPH11135532A JP H11135532 A JPH11135532 A JP H11135532A JP 9314228 A JP9314228 A JP 9314228A JP 31422897 A JP31422897 A JP 31422897A JP H11135532 A JPH11135532 A JP H11135532A
- Authority
- JP
- Japan
- Prior art keywords
- drain
- gate
- source
- electrodes
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、電力用のＳｉＦＥ
ＴやＧａＡｓＦＥＴ等のＦＥＴチップ、及びそれらのＦ
ＥＴチップを実装基板に取り付けて構成した半導体装置
に関する。TECHNICAL FIELD The present invention relates to a power SiFE.
FET chips such as T and GaAs FETs and their F
The present invention relates to a semiconductor device configured by attaching an ET chip to a mounting substrate.
【０００２】[0002]
【従来の技術】従来、電力用のＳｉＦＥＴ、ＧａＡｓＦ
ＥＴ等では、電流を大きくとるためにくし形構造のもの
が広く用いられている。2. Description of the Related Art Conventionally, power SiFET, GaAsF
In ET and the like, a comb-shaped structure is widely used to obtain a large current.
【０００３】図６に、従来の電力用ＦＥＴ半導体素子の
電極配線、外部への配線接続の一例を示す。FIG. 6 shows an example of electrode wiring of a conventional power FET semiconductor device and wiring connection to the outside.
【０００４】図中、１はＳｉＦＥＴ、ＧａＡｓＦＥＴ等
の半導体チップを示す。ドレイン、ゲート、ソースの各
電極はそれぞれ複数個の単位電極２、３、４により構成
されており、これら単位電極はくし形に交互に配列され
ている。In FIG. 1, reference numeral 1 denotes a semiconductor chip such as a SiFET or a GaAs FET. Each of the drain, gate, and source electrodes is constituted by a plurality of unit electrodes 2, 3, and 4, and these unit electrodes are alternately arranged in a comb shape.
【０００５】５、６及び７はそれぞれ単位電極２、３及
び４に接続された金属薄膜よりなるドレイン引出し配線
部、ゲート引出し配線部及びソースの引出し配線部であ
り、ドレイン引出し配線部５とゲート引出し配線部６と
は二層配線構造により交差している。Reference numerals 5, 6, and 7 denote a drain lead wiring portion, a gate lead wiring portion, and a source lead wiring portion made of a metal thin film connected to the unit electrodes 2, 3, and 4, respectively. The lead wiring part 6 intersects with the lead wiring part 6 by a two-layer wiring structure.
【０００６】外部回路への引出しは、上記引出し配線部
５、６、７を接続端子とし、それらに金線８をボンディ
ングして行われる。The lead-out to an external circuit is carried out by using the lead-out wiring parts 5, 6, 7 as connection terminals and bonding gold wires 8 to them.
【０００７】また、電力用ＦＥＴでは、発生する熱の伝
導をよくするため、半導体基板の裏面を薄く（例えば１
００μｍ以下に）削り、そこに金、銀等を厚メッキして
密着性のよい放熱電極（ＰＨＳ：ｐｌａｔｅｄ ｈｅａ
ｔ ｓｉｎｋ）を形成させたものも用いられている。In the power FET, the back surface of the semiconductor substrate is made thin (for example, 1 inch) in order to improve conduction of generated heat.
(Less than 00 μm), thickly plated with gold, silver, etc., and heat-sinking electrode (PHS: plated head) with good adhesion
(t sink) is also used.
【０００８】[0008]
【発明が解決しようとする課題】図６に例示したような
従来のＦＥＴの外部接続構造では、金属薄膜配線部分、
特に金線部分の寄生抵抗や寄生インダクタンスが大きく
なり、ＦＥＴの特性を悪化させる一因となっている。In a conventional FET external connection structure as illustrated in FIG. 6, a metal thin film wiring portion,
In particular, the parasitic resistance and the parasitic inductance of the gold wire portion increase, which is one of the causes of deteriorating the characteristics of the FET.
【０００９】また、放熱効果を上げるために半導体基板
を薄く削る方法をとると、その後の工程で割れの発生を
生じ易く、作業性が悪くなるという問題があった。Further, when a method of shaving a semiconductor substrate to reduce the thickness in order to enhance the heat radiation effect is employed, cracks are liable to occur in the subsequent steps, and the workability is deteriorated.
【００１０】本発明は、上記問題点を解消し、寄生抵抗
や寄生インダクタンスが小さく、放熱特性が改善された
ＦＥＴ半導体チップ及び半導体装置を提供しようとする
ものである。An object of the present invention is to provide an FET semiconductor chip and a semiconductor device which solve the above problems, have small parasitic resistance and parasitic inductance, and have improved heat dissipation characteristics.
【００１１】[0011]
【課題を解決するための手段】本発明は、上記問題点を
解消するために、半導体基板の一表面にドレイン、ゲー
ト、ソースの各複数個の単位電極をくし形に配列してな
るＦＥＴを設けた半導体チップにおいて、前記ドレイン
／又はソース、及びゲートのそれぞれの同種単位電極を
接続する金属薄膜よりなる引出し配線部を設け、該引出
し配線部及び各前記単位ソース電極／又は単位ドレイン
電極にそれぞれボンディング用バンプを設けた。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides an FET in which a plurality of unit electrodes of a drain, a gate, and a source are arranged in a comb on one surface of a semiconductor substrate. In the provided semiconductor chip, an extraction wiring portion made of a metal thin film for connecting the same type of unit electrode of each of the drain / or source and the gate is provided, and the extraction wiring portion and each of the unit source electrode / or the unit drain electrode are respectively provided. A bonding bump was provided.
【００１２】前記半導体チップのボンディング用バンプ
として、金バンプ等の比較的硬質のバンプ、又は該バン
プの上面に錫、ハンダ等の低融点金属材料を被覆したも
のを用いた。As the bonding bump of the semiconductor chip, a relatively hard bump such as a gold bump or a bump whose upper surface is coated with a low melting point metal material such as tin or solder is used.
【００１３】また、前記ドレイン用、ゲート用及びソー
ス用の各バンプは、それぞれ整列して互いに並列となる
ように配置させた。The drain, gate, and source bumps are arranged so as to be aligned and in parallel with each other.
【００１４】更に、前記半導体チップを、フリップチッ
プ方式で実装基板にボンディングし、小型パッケージ組
み込みの半導体装置とした。Further, the semiconductor chip is bonded to a mounting substrate by a flip chip method to obtain a semiconductor device incorporated in a small package.
【００１５】前記実装基板として窒化アルミニウム基板
を用い、また、実装基板に設けるドレイン用、ゲート用
及びソース用の各配線は、それぞれ金属薄膜よりなる一
体化した配線として設けた。An aluminum nitride substrate was used as the mounting substrate, and the drain, gate, and source wirings provided on the mounting substrate were provided as integrated wirings each made of a metal thin film.
【００１６】[0016]
【発明の実施の形態】図１に、本発明の半導体チップの
一実施例の平面図、図２に、その右側面図を示す。FIG. 1 is a plan view of one embodiment of a semiconductor chip of the present invention, and FIG. 2 is a right side view thereof.
【００１７】半導体チップ１の一表面に、ドレイン、ゲ
ート、ソースの各複数個の単位電極２、３、４がくし形
に交互に配列されており、単位ドレイン電極２同志及び
単位ゲート電極３同志は、それぞれ金属薄膜よりなるド
レイン引出し配線部５、ゲート引出し配線部６により接
続されている。On one surface of the semiconductor chip 1, a plurality of unit electrodes 2, 3, 4 each of a drain, a gate, and a source are alternately arranged in a comb shape, and the unit drain electrodes 2 and the unit gate electrodes 3 Are connected by a drain lead-out wiring part 5 and a gate lead-out wiring part 6 each made of a metal thin film.
【００１８】これら引出し配線部５、６にはそれぞれ複
数個のボンディング用のドレインバンプ９、ゲートバン
プ１０が整列して設けられ、単位ソース電極の各々に
は、電極と同一形状の短冊状のソースバンプ１１が設け
られている。A plurality of bonding drain bumps 9 and gate bumps 10 are provided in alignment on each of the extraction wiring portions 5 and 6, and each of the unit source electrodes has a rectangular source having the same shape as the electrodes. A bump 11 is provided.
【００１９】これらのバンプは、熱圧着、超音波圧着等
によるボンディングの際の高温、圧力にくずれるおそれ
のない比較的硬質の金バンプ等を用いるか、又は図３に
示したように、金バンプ等をコアバンプ１２とし、その
上面に錫、ハンダ等の低融点金属材料の皮膜１３を設け
たものを用いる。後者の場合、加熱のみでのボンディン
グが可能となる。For these bumps, use is made of a relatively hard gold bump or the like which is not likely to be damaged by high temperature and pressure during bonding by thermocompression bonding, ultrasonic compression bonding, or the like, or as shown in FIG. And the like are used as the core bumps 12, and the upper surface thereof is provided with a coating 13 of a low melting point metal material such as tin or solder. In the latter case, bonding can be performed only by heating.
【００２０】図４は、上記半導体チップを実装基板に接
着して構成した半導体装置の一実施例の平面図、図５
は、右側面図である。FIG. 4 is a plan view showing one embodiment of a semiconductor device in which the above-mentioned semiconductor chip is bonded to a mounting substrate.
Is a right side view.
【００２１】実装基板１４には、予めその一表面の上記
バンプに対応する部分及び側面の一部（図５参照）には
幅広の金属薄膜よりなるドレイン配線１５、ソース配線
１７、ゲート配線１６を形成しておき、その上に半導体
チップをフェイスダウンして載せ、いわゆるフリップチ
ップ方式で、両者を接着する。On the mounting substrate 14, a drain wiring 15, a source wiring 17, and a gate wiring 16 made of a wide metal thin film are previously formed on a part of one surface corresponding to the bump and a part of the side surface (see FIG. 5). A semiconductor chip is mounted face down on the semiconductor chip, and both are bonded by a so-called flip chip method.
【００２２】実装基板１４には、上記のようにドレイン
配線１５、ソース配線１７、ゲート配線１６がその上
面、側面及び下面の一部に形成されているので、それら
の所要箇所を外部接続用の端子として構成することによ
り、小型パッケージの半導体装置として仕上げることが
できる。As described above, the drain wiring 15, the source wiring 17, and the gate wiring 16 are formed on the upper surface, the side surface, and a part of the lower surface of the mounting substrate 14, so that necessary portions for external connection are formed. By configuring as a terminal, a semiconductor device having a small package can be completed.
【００２３】本発明の半導体装置は上記のようにしては
作られ、半導体チップが実装基板にコンパクトなバンブ
で接続されるので、寄生抵抗や寄生インダクタンスを小
さく、放熱特性が改善されたＦＥＴ半導体装置が得られ
る。The semiconductor device of the present invention is manufactured as described above, and since the semiconductor chip is connected to the mounting substrate with a compact bump, the FET semiconductor device has reduced parasitic resistance and parasitic inductance and improved heat dissipation characteristics. Is obtained.
【００２４】実装基板としては、アルミナ基板等も利用
できるが、熱伝導率が同基板に比べ数倍高い窒化アルミ
ニウム基板を用いることで、放熱効果はより改善され
る。As a mounting substrate, an alumina substrate or the like can be used, but by using an aluminum nitride substrate having a thermal conductivity several times higher than that of the same substrate, the heat radiation effect is further improved.
【００２５】なお、上述の実施例の説明では、半導体チ
ップのボンディング用バンプを設ける箇所について、ド
レイン及びゲートのそれぞれの（金属薄膜よりなる）引
出し配線部と各単位ソース電極に設けた例のみについて
述べたが、本発明の対象とするＦＥＴは、一般にドレイ
ン部とソース部は対称的に同一構造に形成されるので、
ドレインをソース、ソースをドレインと読み替えた構成
の半導体チップ、及び該半導体チップを実装基板に取り
付けて構成した半導体装置も可能であり、本発明の一形
態をなすものである。In the above description of the embodiment, only the example where the bonding bumps of the semiconductor chip are provided on the lead wiring portions (made of a metal thin film) of the drain and the gate and the unit source electrodes are provided. As described above, in the FET to which the present invention is applied, the drain portion and the source portion are generally symmetrically formed in the same structure.
A semiconductor chip in which a drain is read as a source and a source is read as a drain, and a semiconductor device in which the semiconductor chip is attached to a mounting substrate are also possible, and form one embodiment of the present invention.
【００２６】[0026]
【発明の効果】以上説明したように、本発明のくし形構
成のＦＥＴ半導体チップは、ドレイン／又はソース、及
びゲートのそれぞれの同種単位電極を接続する金属薄膜
よりなる引出し配線部を設け、該引出し配線部及び各前
記単位ソース電極／又は単位ドレイン電極にそれぞれボ
ンディング用バンプを設けた構造としたので、この半導
体チップを、フリップチップ方式により実装基板に直接
ボンディングすることにより、小型パッケーシの半導体
装置とすることができ、特性悪化の一因となる寄生抵抗
や寄生インダクタンスの小さい、ＦＥＴ特性が改善され
たＦＥＴ半導体装置を実現できる。As described above, the comb-shaped FET semiconductor chip of the present invention is provided with a lead-out wiring portion made of a metal thin film for connecting the same type of unit electrodes of the drain / source and the gate. Since the bonding bump is provided on each of the extraction wiring portion and each of the unit source electrodes and / or the unit drain electrodes, the semiconductor chip is directly bonded to a mounting substrate by a flip-chip method, thereby providing a small package semiconductor device. Thus, it is possible to realize an FET semiconductor device having an improved FET characteristic, having a small parasitic resistance and a small parasitic inductance which contribute to the deterioration of the characteristic.
【００２７】また、バンプによる接続構造により、ＦＥ
Ｔにより発生する熱はボンディング部を通して熱抵抗小
さく実装基板側へ放熱されるので、半導体基板を薄く削
る等の必要がなく、作業性が向上する。また、実装基板
として窒化アルミニウム基板を用いることにより、放熱
効果は更に高められる。The connection structure using bumps allows the FE
Since the heat generated by T is radiated to the mounting substrate side with small thermal resistance through the bonding portion, there is no need to thinly cut the semiconductor substrate, and the workability is improved. Further, the use of an aluminum nitride substrate as the mounting substrate further enhances the heat radiation effect.
【００２８】また、半導体チップに設けるドレイン用、
ゲート用及びソース用の各バンプは、それぞれ整列して
互いに並列となるように配置させ、ボンディングされる
実装基板に設けるドレイン用、ゲート用及びソース用の
各配線は、上記配置に対応しそれぞれ金属薄膜よりなる
一体化した配線とすることにより、配線をコンパクトに
まとめることができ、特性改善効果を高めることができ
る。For a drain provided on a semiconductor chip,
The bumps for the gate and the source are arranged so as to be aligned and in parallel with each other, and the wirings for the drain, the gate and the source provided on the mounting substrate to be bonded are made of metal corresponding to the above arrangement. By forming an integrated wiring made of a thin film, the wiring can be compacted and the effect of improving characteristics can be enhanced.
【００２９】また、半導体チップのボンディング用バン
プとして、金バンプ等の比較的硬質のバンプ、又は該バ
ンプの上面に錫、ハンダ等の低融点金属材料を被覆した
ものを用いることにより、バンプ間ショートの生じない
安定したボンディングが可能となる。In addition, a relatively hard bump such as a gold bump or a bump whose upper surface is coated with a low melting point metal material such as tin or solder is used as a bonding bump for a semiconductor chip, so that a short between bumps can be obtained. This enables stable bonding without generation of cracks.
【００３０】また、本発明の半導体チップは、ソース電
極用の引出し配線部を設けないので、半導体チップを小
さくできる利点をもっている。Further, the semiconductor chip of the present invention has an advantage that the semiconductor chip can be reduced in size because no lead wire portion for the source electrode is provided.
【００３１】また、本発明の半導体チップは、バンプ形
成のための工程が必要となる反面、電極引出し配線の交
差部をもたないので、複雑な二層配線部形成の工程が不
要となる。Further, the semiconductor chip of the present invention requires a step for forming a bump, but does not have a crossing portion of an electrode lead-out wiring, so that a complicated step for forming a two-layer wiring part is not required.
【図１】本発明の半導体チップの一実施例の平面図であ
る。FIG. 1 is a plan view of one embodiment of a semiconductor chip of the present invention.
【図２】同上実施例の右側面図である。FIG. 2 is a right side view of the embodiment.
【図３】バンプの構成説明図である。FIG. 3 is an explanatory diagram of a configuration of a bump.
【図４】本発明の半導体装置の一実施例の平面図であ
る。FIG. 4 is a plan view of one embodiment of the semiconductor device of the present invention.
【図５】同上実施例の右側面図である。FIG. 5 is a right side view of the embodiment.
【図６】ＦＥＴ半導体チップの従来例の平面図である。FIG. 6 is a plan view of a conventional example of an FET semiconductor chip.
１：半導体チップ ２：単位ドレイン電極 ３：単位ゲート電極 ４：単位ソース電極 ５：ドレイン引出し配線部 ６：ゲート引出し配線部 ７：ソース引き出し配線部 ８：金線 ９：ドレインバンプ １０：ゲートバンプ １１：ソースバンプ １２：コアバンプ １３：溶着用金属皮膜 １４：実装基板 １５：ドレイン配線 １６：ゲート配線 １７：ソース配線。 1: semiconductor chip 2: unit drain electrode 3: unit gate electrode 4: unit source electrode 5: drain lead wiring section 6: gate lead wiring section 7: source lead wiring section 8: gold wire 9: drain bump 10: gate bump 11 : Source bump 12: Core bump 13: Metal film for welding 14: Mounting substrate 15: Drain wiring 16: Gate wiring 17: Source wiring.
Claims (6)
ト、ソースの各複数個の単位電極をくし形に配列してな
るＦＥＴを設けた半導体チップにおいて、前記ドレイン
／又はソース、及びゲートのそれぞれの同種単位電極を
接続する金属薄膜よりなる引出し配線部を設け、該引出
し配線部及び各前記単位ソース電極／又は単位ドレイン
電極にそれぞれボンディング用バンプを設けたことを特
徴とする半導体チップ。In a semiconductor chip provided with an FET in which a plurality of unit electrodes of a drain, a gate, and a source are arranged in a comb on one surface of a semiconductor substrate, each of the drain / source and the gate is provided. A semiconductor chip comprising: a lead wiring portion made of a metal thin film for connecting unit electrodes of the same kind; and a bonding bump provided on each of the lead wiring portion and each of the unit source electrode and / or the unit drain electrode.
等の比較的硬質のバンプ、又は該バンプの上面に錫、ハ
ンダ等の低融点金属材料を被覆したものを用いたことを
特徴とする請求項１の半導体チップ。2. The bonding bump according to claim 1, wherein a relatively hard bump such as a gold bump or a bump whose upper surface is coated with a low melting point metal material such as tin or solder is used. Semiconductor chip.
バンプは、それぞれ整列して互いに並列となるように配
置させたことを特徴とする請求項１の半導体チップ。3. The semiconductor chip according to claim 1, wherein the drain bumps, the gate bumps, and the source bumps are aligned and arranged in parallel with each other.
フリップチップ方式で実装基板にボンディングしてなる
ことを特徴とする半導体装置。4. The semiconductor chip according to claim 1, 2 or 3,
A semiconductor device characterized by being bonded to a mounting substrate by a flip chip method.
用いることを特徴とする請求項４の半導体装置。5. The semiconductor device according to claim 4, wherein an aluminum nitride substrate is used as a mounting substrate.
及びソース用の各配線は、それぞれ金属薄膜よりなる一
体化した配線として設けることを特徴とする請求項４の
半導体装置。6. The semiconductor device according to claim 4, wherein each of the drain, gate and source wirings provided on the mounting substrate is provided as an integrated wiring made of a metal thin film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9314228A JPH11135532A (en) | 1997-10-30 | 1997-10-30 | Semiconductor chip and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9314228A JPH11135532A (en) | 1997-10-30 | 1997-10-30 | Semiconductor chip and semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11135532A true JPH11135532A (en) | 1999-05-21 |
Family
ID=18050834
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9314228A Pending JPH11135532A (en) | 1997-10-30 | 1997-10-30 | Semiconductor chip and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11135532A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100439409B1 (en) * | 2002-07-16 | 2004-07-09 | 삼성전기주식회사 | Semiconductor device for chip size packaging and method of producing the same |
| CN1315195C (en) * | 2000-02-10 | 2007-05-09 | 国际整流器有限公司 | Vertical conduction flip chip device with bump contacts on single surface |
| JP2007194305A (en) * | 2006-01-18 | 2007-08-02 | Renesas Technology Corp | Semiconductor device |
| CN102376681A (en) * | 2010-08-06 | 2012-03-14 | 联发科技股份有限公司 | Package substrate |
-
1997
- 1997-10-30 JP JP9314228A patent/JPH11135532A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1315195C (en) * | 2000-02-10 | 2007-05-09 | 国际整流器有限公司 | Vertical conduction flip chip device with bump contacts on single surface |
| KR100439409B1 (en) * | 2002-07-16 | 2004-07-09 | 삼성전기주식회사 | Semiconductor device for chip size packaging and method of producing the same |
| JP2007194305A (en) * | 2006-01-18 | 2007-08-02 | Renesas Technology Corp | Semiconductor device |
| CN102376681A (en) * | 2010-08-06 | 2012-03-14 | 联发科技股份有限公司 | Package substrate |
| US8390119B2 (en) | 2010-08-06 | 2013-03-05 | Mediatek Inc. | Flip chip package utilizing trace bump trace interconnection |
| US8502377B2 (en) | 2010-08-06 | 2013-08-06 | Mediatek Inc. | Package substrate for bump on trace interconnection |
| US10354970B2 (en) | 2010-08-06 | 2019-07-16 | Mediatek Inc. | Flip chip package utilizing trace bump trace interconnection |
| US10707183B2 (en) | 2010-08-06 | 2020-07-07 | Mediatek Inc. | Flip chip package utilizing trace bump trace interconnection |
| US11121108B2 (en) | 2010-08-06 | 2021-09-14 | Mediatek Inc. | Flip chip package utilizing trace bump trace interconnection |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6975023B2 (en) | Co-packaged control circuit, transistor and inverted diode | |
| TWI450373B (en) | Dual side cooling integrated power device package and module and methods of manufacture | |
| US8698289B2 (en) | Semiconductor device, a method of manufacturing the same and an electronic device | |
| US12040301B2 (en) | Semiconductor device | |
| US20080054425A1 (en) | Power electronic package having two substrates with multiple electronic components | |
| KR20170086828A (en) | Clip -bonded semiconductor chip package using metal bump and the manufacturing method thereof | |
| JP3390661B2 (en) | Power module | |
| JP3971568B2 (en) | Semiconductor package and semiconductor package manufacturing method | |
| JPH06302653A (en) | Semiconductor device | |
| JP4327096B2 (en) | Semiconductor device having clip for external connection | |
| JP2022143166A (en) | semiconductor equipment | |
| JP4023032B2 (en) | Mounting structure and mounting method of semiconductor device | |
| JP3336982B2 (en) | Semiconductor device and method of manufacturing the same | |
| JPH0444347A (en) | Semiconductor device | |
| US20220310409A1 (en) | Method to connect power terminal to substrate within semiconductor package | |
| JPH11135532A (en) | Semiconductor chip and semiconductor device | |
| JP2002329804A (en) | Semiconductor device | |
| JP2003068975A (en) | Semiconductor device and its manufacturing method | |
| JPH07176664A (en) | Semiconductor device and fabrication thereof | |
| JP2022143168A (en) | Semiconductor device | |
| JP3314574B2 (en) | Method for manufacturing semiconductor device | |
| JPH08148647A (en) | Semiconductor device | |
| JPH09213877A (en) | Multi-chip module semiconductor device | |
| WO2022196232A1 (en) | Semiconductor apparatus and method for manufacturing semiconductor apparatus | |
| JP4047572B2 (en) | Power semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20040723 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20040803 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20041207 |