JPH11122533A - Semiconductor amplifier circuit and solid-state image pickup element using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an excellent image automatically by providing a low resistance electrode layer between a signal read line and a substrate and connecting the layer to a power supply having a stable output voltage characteristic so as to fix/stabilize a voltage applies to the signal read line and also to a stray capacitance of a photo diode thereby stabilizing and uniformizing the output characteristic over entire pixels. SOLUTION: A contact region 6 made of a low resistance material is formed on an inter-layer film 5, and the contact region 6 connects electrically to a drain 4c of a MOS transistor 4 through a hole 7 made to the inter-layer film 5. An electrode layer 8 made of a low resistance material is formed on the inter-layer film 5 separately from the contact region 6. A signal read line 10 on an insulation layer 9 on the semiconductor substrate 1 connects electrically to the contact region 6 through a hole 11 made to the insulation layer 9 so as to be overlapped with the electrode layer 8. Then the electrode layer 8 in the actual operation connects to a constant voltage source at the outside of a pixel region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor amplifier circuit and a solid-state image pickup device using the same, and more particularly to a solid-state image pickup device having a CMOS type signal readout circuit and having stable signal readout characteristics over the entire pixel region. It is about.

[0002]

2. Description of the Related Art As a solid-state imaging device, a CM using a CMOS transistor (FET) for a signal readout circuit is used.
A so-called OS imager is known. This C
Since the MOS imager uses a CMOS process used for manufacturing various integrated circuits, the MOS imager can be used for other functional circuits such as an AD converter on the same substrate.
A signal compression circuit and the like can be incorporated, and high-performance elements can be provided at a low price.

Further, all the circuits manufactured in this way can be driven by the operating voltage of CMOS,
The following low-voltage operation is possible, and in the pixel region of the CMOS imager, the circuit only needs to operate a circuit for reading out signals. It has the feature that power consumption can be reduced, and has great potential as an image reading device for small portable devices that mainly operate on batteries.

Several methods are known as a signal reading method (circuit) for such a CMOS imager. Among them, a method using a circuit as shown in FIG. 7 is known. . However, for simplicity of the following explanation,
Only the basic configuration of the main parts related to the present invention is shown. In this signal readout circuit, a photodiode 101 is used as a photoelectric conversion element that converts received light into an electric signal. One terminal of the photodiode 101 is connected to the ground, and the other terminal selects a signal readout pixel. To the source 102a of the MOS transistor 102 as a switch for performing the operation. The drain 102b of the MOS transistor 102 is connected to a signal read line 104.

In FIG. 7, for simplification, only a circuit corresponding to one pixel (photodiode) is shown. However, as shown in FIG.
A plurality of photodiodes 31 are connected via the OS transistor 32. The signal read line 104 is connected to the integration circuit 110. The signal read line 104
Corresponds to the signal readout line 34 in FIG.
0 is provided in the horizontal scanning circuit and the output amplification circuit 39 in FIG.

In the signal reading circuit shown in FIG. 7, at least three capacitors, a stray capacitor 101a (capacitance: C1) of the photodiode 101, and a stray capacitor 103 (capacitance: C) of the wiring 104 are provided.
2), feedback capacitance 106 of integration circuit 110 (capacity: C3)
And the feedback capacitance 106 is intentionally formed in the integration circuit, whereas the stray capacitances 101a and 103 are automatically formed as the circuit is formed. In such a circuit configuration, a signal generated when the photodiode 101 receives light is output to the output 108 of the integrating circuit 110 by the following operation (this output is usually not shown separately. Connected to the circuit).

The operation of the signal read circuit will be described below. Note that the operation of the circuit is assumed to be ideal because the purpose is to explain the principle matters. FIG. 5 shows the progress of the operation in the signal readout circuit. The + input terminal 105a of the operational amplifier 105 is always connected to the reference voltage V
ref. In that state, first, in order to form a reference state for generating a signal corresponding to the light intensity, the transistors 102 and 107 are turned on, and the entire area of the circuit shown here is set to the reference potential Vref. Reset to. Next, the transistors 102 and 107 are turned off, and carriers generated in the photodiode 101 are transferred to the stray capacitance 101 of the photodiode 101.
a. At this time, the voltage of this portion, that is, FIG.
Of the photodiode 1 from the reference voltage Vref
Assuming that the voltage change amount ΔV1 corresponds to the charge amount ΔQ1 generated in 01, the voltage change amount ΔV1 = ΔQ1 / C1.

In order to read a signal, the carrier generation / accumulation state is held for a certain period of time, and then a predetermined voltage is applied to the gate 102c of the transistor 102 to turn on the transistor 102. ,
Since the negative terminal 105b of the operational amplifier 105 is at the reference voltage Vref due to the ideal operation of the operational amplifier 105,
With this operation, the voltage V1 of the photodiode 101 becomes
It will return to the reference voltage Vref. The wiring 10
4, that is, the voltage V2 in FIG.
The same reference voltage Vref as at the time of reset is maintained.

Therefore, the capacitances stored in the floating capacitances 101a and 103 at this time are the same as those at the time of completion of the reset operation. In this state, the carrier connected to the negative side terminal 105b of the operational amplifier 105 is closed, so that all the carriers generated in the photodiode 101 are accumulated in the feedback capacitor 106.
= Q / C, the output of the operational amplifier 105 changes from the voltage in the reset state to the voltage change amount ΔV3 = −ΔQ1 / C
It will change by three. Normally, the signal read time is sufficiently shorter than the carrier accumulation time, and thus, for simplicity, the charge generated in the photodiode 101 during this signal read period is ignored.

That is, the voltage change ΔV1 = ΔQ1 / C1 due to the light absorption of the photodiode 101 gives a change in the output voltage by the voltage change ΔV3 = −ΔQ1 / C3. In an actual image sensor, signals from a plurality of pixels are read out by one amplifier circuit, so that the reset operation and the signal readout operation described above are repeated to sequentially read out the signals from the plurality of pixels. Then, in such an ideal state, the same operation state is obtained for all the pixels. Therefore, when light of the same intensity is irradiated, the same output is obtained over the entire pixel region.

[0011]

FIG. 8 shows an example of a cross-sectional structure near the photodiode of one pixel of a conventional solid-state imaging device having the circuit configuration shown in FIG. FIG.
8A is a cross-sectional view of a region including a MOS transistor (102 in FIG. 7) as a switch for turning on / off signal reading, and FIG. 8B is a cross-sectional view of a region not including a MOS transistor. .

In this conventional example, the p-type semiconductor substrate 1
An n-type region 2 is formed thereon by ion implantation, thereby forming a photodiode 3 as a photoelectric conversion region. Part of the n-type region 2 of the photodiode 3 is continuously connected to the source 4a of the MOS transistor 4 functioning as an on / off switch for signal reading and reset operation. In the MOS transistor 4, a gate 4b made of poly-Si or the like is formed adjacent to the source 4a via a gate oxide film (not shown). On the opposite side of the source region 4a across the gate 4b, The drain 4c is formed. A field oxide film 12 is formed as a pixel isolation region around one pixel region where the photodiode 3 and the MOS transistor 4 are formed.

As described above, the photodiode 3 and the MOS
On the semiconductor substrate 1 on which the transistor 4 and the field oxide film 12 are formed, a PSG (poly silicate
An interlayer film 5 made of glass or the like is laminated. A signal read line 20 made of a low-resistance material such as a metal material is formed on the interlayer film 5.
Through the hole 17 formed in the MOS transistor 4
Electrically connected to the drain 4c. Signal read line 2
0 is formed on the semiconductor substrate 1 on which an insulating layer 9 made of SiO ₂ or the like is laminated.
A silicon nitride film or the like is formed.

In such an element structure, the photodiode 3 has a pn junction formed therein, and the signal readout line 20 has a floating capacitance with the semiconductor substrate 1 (101a and 103 in FIG. 7, respectively). Is formed. Then, as shown in FIG.
Is wired so that signals of a large number of pixels (actually hundreds) can be read, and therefore requires a considerably long wiring. Therefore, the stray capacitance (103 in FIG. 7) of the signal read line 34 has a considerably large value.

FIG. 10 shows a more realistic circuit diagram. The floating capacitance 101a of the photodiode 101 and the floating capacitance 103 of the signal readout line 104 are connected to the ground of the power supply via the semiconductor substrate. actually,
Although the resistance value connected to the stray capacitance 101a and the resistance value connected to the stray capacitance 103 are different, for the sake of simplicity in the following description, it is assumed that they are connected to the same resistor 109. Under the influence of the potential fluctuation, a current flows through the substrate, so that a potential Vx corresponding to the position is generated at each point on the substrate.

In such a state, if the potential is temporally stable and maintains a constant value, the voltage applied to the floating capacitance 101a and the floating capacitance 103 in the consideration of FIG. Resistance 10 against the voltage considered in
The voltage of the photodiode 101 generated in response to the light absorption / carrier generation of the photodiode 101 although the amount of charge stored therein decreases according to the voltage Vx applied to the portion 9 The change amount ΔV1 and the voltage change amount ΔV3 of the output 108 are the same as those described with reference to FIG.

However, during the actual circuit operation, the current flowing in the substrate changes every moment due to the horizontal and vertical scanning circuits and the clock operation for the amplifier operation of the output system. The potential at each point varies depending on the position and time, and the output voltage is greatly affected by the potential. The effect will be described below.

In FIG. 10, the floating capacitance 103 and the substrate /
The potential Vx at the connection point 112 of the wiring resistance is a function of time, and this is the potential Vxo at the reset operation end time t = t1 immediately before the signal reading of the pixel from which the signal is to be read.
And In this case, the charge Q10 stored in the floating capacitance 101a of the photodiode 101 is: Q10 = C1 · (Vref−Vxo) The charge Q20 stored in the floating capacitance 103 of the signal readout line 104 is Q20 = C2 · ( Vref−Vxo) The charge Q30 stored in the feedback capacitor 106 is
Since both the voltages at both ends of the feedback capacitor 106 are the reference voltage Vref, the voltage is zero.

In this state, the MOS transistor 102
Is turned off and the photodiode 1
01 generates a carrier, which is stored in the stray capacitance 101 a of the photodiode 101. t = t2
It is assumed that the amount of charge generated by the photodiode 101 is ΔQ1 and the potential Vx at the connection point 112 between the stray capacitance 103 and the substrate / wiring resistance has changed (increased) from Vxo by ΔVx by the time of the signal readout. When the switch by the MOS transistor 102 is turned on and the signal reading is started, the potential of the signal reading line becomes the reference voltage Vref after a certain time. Therefore, when t = t2, the potential is accumulated in the floating capacitance 101a of the photodiode 101. Charge Q11
Q11 = C1 · (Vref−Vxo− △ Vx) = Q10−
C1 △ Vx Charge Q stored in the floating capacitance 103 of the signal readout line 104
21, Q21 = C2 · (Vref−Vxo− △ Vx) = Q20−
C2 · △ Vx.

From the above, the electric charge Q31 stored in the feedback capacitor 106 at this time is as follows: Q31 = △ Q31 + (C1 + C2) · △ Vx, and the voltage change ΔV3 of the output 108 of the corresponding circuit is ΔV3 =-△ Q1 / C3- (C1 + C2) △△ Vx / C
3 and the change amount is larger by (C1 + C2) ΔVx / C3 than when the change amount ΔVx of the potential Vx is 0. Here, looking at the relationship between the capacitances C1, C2, and C3 in the capacitance (C1 + C2) / C3 of the stray capacitances 101a and 103 and the feedback capacitance 106, generally, C1 <<
Basically, the amount of change largely depends on the capacitance C2 of the stray capacitance 103 of the signal readout line 104 because it is C2.
Further, when this circuit is formed on a semiconductor substrate, increasing the capacitance C3 of the feedback capacitor 106 requires a large area for this purpose, so that usually C2>
> C3, the potential V
A small change in the change amount ΔVx of x causes a large change in the output voltage, that is, instability of the characteristics. More realistically, even if the potential change amounts ΔVx1 and ΔVx2 of the capacitance C1 of the stray capacitance 101a of the photodiode 101 and the capacitance C2 of the stray capacitance 103 of the wiring 104 are different in principle, they are the same.

In the element, it is considered that the potential change amount ΔVx differs depending on (the position of) the signal readout line due to the resistance component of the semiconductor substrate and the current flowing therethrough, and the output voltage value differs depending on the signal readout line. become. For example, assuming that the capacitance C2 is 1 pF and the capacitance C3 is 0.1 pF, assuming that the potential change ΔVx of one signal read line is 1 mV and the potential change ΔVx of another signal read line is 2 mV, the difference is as follows. Although it is 1 mV, each output gives an output difference of 10 mV, which is a value sufficient to impair image quality.

In fact, in the solid-state imaging device manufactured by using the circuit shown in FIG. 7, the in-plane distribution of the output voltage as shown in FIG. 11 and the fixed pattern noise (FPN) well known in CMOS imagers are shown. Appearance had greatly impaired image quality. Therefore, in order to obtain good image quality, in other words, to stabilize the voltage change amount ΔV3 of the output 108 of the circuit,
The potential change amount ΔVx is reduced. This means that it is necessary to stabilize the voltage across the stray capacitance. It is considered that the potential change ΔVx can be reduced by stabilizing the potential of the stray capacitance of the signal readout line on the substrate side in terms of location and time. In order to further improve the characteristics, it is desirable to stabilize the potential of the floating capacitance of the photodiode on the substrate side.

[0023]

According to the present invention, there is provided a solid-state imaging device comprising a low-resistance electrode layer provided between a signal readout line and a substrate;
This is characterized in that it is connected to a power supply having stable output voltage characteristics. The circuit diagram is as shown in FIG.
The voltage across the stray capacitance is the reference voltage Vref and the output voltage V
a. However, Va = 0, that is, the electrode layer may be connected to a stable ground potential. Also,
Another feature is that after taking such measures, the potential of the photodiode in the light receiving area on the ground side is stabilized.

According to the present invention, even when the potential of the substrate changes spatially and temporally, the voltages at both ends of the stray capacitance of the signal readout line are respectively equal to the reference voltage Vref and the newly provided electrode layer. Is fixed / stabilized, the amount of charge stored in the stray capacitance of the signal readout line is stabilized, and the output characteristics of the circuit, that is, the image quality of the CMOS imager is greatly improved. Further, by fixing / stabilizing the ground potential of the stray capacitance of the photodiode, the amount of charge accumulated in the stray capacitance of the photodiode during signal reading is also stabilized, and the image quality of the imager is further improved. Become.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the solid-state imaging device of the present invention will be described below in detail with reference to the drawings. [Embodiment 1] FIG. 1 schematically shows a sectional structure view of one pixel portion (and its periphery) according to Embodiment 1 of the solid-state imaging device of the present invention. FIG. 1A shows that signal reading is on / off.
FIG. 1B is a cross-sectional view of a region including a MOS transistor (102 in FIG. 4) as a switch that performs f. FIG. 1B is a cross-sectional view of a region not including the MOS transistor.

In this embodiment, an n-type region 2 is formed on a p-type semiconductor substrate 1 by ion implantation, thereby forming a photodiode 3 as a photoelectric conversion region. A part of the n-type region 2 of the photodiode 3 has a source 4 of a MOS transistor 4 functioning as an on / off switch for signal reading and reset operation.
a. The MOS transistor 4 has a gate oxide film (not shown) adjacent to the source 4a.
, A gate 4b made of poly-Si or the like is formed, and a drain c4c is formed on the opposite side of the source region 4a across the gate 4b. A field oxide film 12 is formed as a pixel isolation region around one pixel region where the photodiode 3 and the MOS transistor 4 are formed.

As described above, the photodiode 3 and the MOS
On the semiconductor substrate 1 on which the transistor 4 and the field oxide film 12 are formed, an interlayer film 5 made of PSG (polysilicate glass) or the like is laminated. A contact region 6 made of a low-resistance material such as a metal material is formed on the interlayer film 5, and the contact region 6 is formed through a hole 7 formed in the interlayer film 5 through a MOS transistor 4.
Electrically connected to the drain 4c. An electrode layer 8 made of a low-resistance material such as a metal material is formed on the interlayer film 5 separately from the contact region 6.

In this embodiment, the width of the electrode layer 8 is made equal to the width of the signal readout line 10 in a region where the MOS transistor 4 is not provided, as shown in FIG.
The width of the electrode layer 8 is not limited to this. However, when the overlap between the electrode layer 8 and the signal readout line 10 is reduced, the effect of the electrode layer 8 is reduced. The width of the electrode layer 8 needs to be at least 50% of the width of the signal read line 10 in consideration of the displacement between the signal read line 10 and the signal read line 10.

An insulating layer 9 made of SiO ₂ or the like is formed on the semiconductor substrate 1 on which the contact region 6 and the electrode layer 8 are formed.
Are stacked, and a signal readout line 10 is provided on the insulating layer 9.
Is formed so as to overlap with the electrode layer 8 and to be electrically connected to the contact region 6 through the hole 11 formed in the insulating layer 9. As described above, a silicon nitride film or the like is formed as the protective film 13 on the semiconductor substrate 1 on which the components are formed. In the configuration described above, during the actual operation, the electrode layer 8 is connected to the constant voltage power supply 36 outside the pixel region, as indicated by reference numeral 35 in FIG.

Next, a method for manufacturing this solid-state image sensor will be described with reference to FIG. First, as shown in FIG.
A field oxide film 12 serving as a pixel isolation region is formed on a p-type semiconductor substrate 1 by selective thermal oxidation. Next, after a thin gate oxide film (not shown) is formed in a region other than the field oxide film 12 region of the semiconductor substrate 1, poly-Si or the like to be the gate 4b of the MOS transistor 4 is laminated on the entire surface of the semiconductor substrate 1. Then, as shown in FIG. 3B, a gate 4b is formed using a photolithography method or the like.

Next, as shown in FIG. 3C, the n-type region 2 of the photodiode 3 and M
The source 4a and the drain 4c of the OS transistor 4 are formed. These n-type regions can be formed simultaneously. Thereafter, as shown in FIG. 3D, an interlayer film 5 is formed on the surface of the semiconductor substrate 1, and a hole 7 for connecting the contact region 6 and the drain 4c is formed by photolithography or the like. A metal material to be the contact region 6 and the electrode layer 8 is deposited thereon, and the contact region 6 and the electrode layer 8 are formed again by using the photolithography method or the like.

As shown in FIG. 3E, an insulating film 9 made of an oxide film or the like is formed on the interlayer film 5, and the signal read line 10 and the contact region 6 are connected by using a photolithography method or the like. Is formed, a metal material to be the signal readout line 10 is deposited, and the signal readout line 10 is formed again by photolithography or the like so as to overlap the electrode layer 8. Finally, a protective film 13 made of a silicon nitride film or the like is formed. Although the above steps describe a method for manufacturing a pixel region, a vertical scanning circuit, a horizontal scanning circuit, an output amplification circuit, and the like around the pixel region are simultaneously manufactured in the same process.

In this embodiment, the voltage applied to the stray capacitance of the signal readout line is fixed to the difference between the reference voltage Vref and the output voltage Va applied to the electrode layer 8, so that the potential of the pixel region on the substrate fluctuates. Even in such a case, it does not affect the output characteristics, and stable output characteristics, that is, good image quality can be obtained.

Note that the wiring structure of the signal readout line portion of the present embodiment has a structure in which an output signal of a circuit connected to the integrating circuit 110 is provided as shown in FIG. The same effect can be obtained in a circuit system that is a low-level analog signal. This is because when the ratio of the capacitance C3 of the feedback capacitance 106 for forming the integration circuit 110 to the capacitance C4 of the floating capacitance 115 of the signal line 116 connected to the input of the integration circuit 110 is C4 / C3> 1. Great effect.

[Embodiment 2] In Embodiment 2, as shown in FIG. 6, the basic structure of Embodiment 1 is used, and the ground wiring 20 is connected to the ground so that the substrate region of each pixel region is connected to the ground with low resistance. A ground contact 21 is formed. The ground wiring 20 is connected to the power supply ground with low resistance. This ground contact 21
May be formed in each pixel region, but in that case, the light receiving area is reduced accordingly, and the overall sensitivity characteristics are reduced. As can be seen from FIG. 6, each ground contact 21 is connected via the substrate 1, and the object of connecting the photodiode to the ground with low resistance is achieved without forming the ground contact 21 in each pixel region. . For example, if the ground contact 21 is formed in a certain pixel, it is considered that the pixel and the pixel surrounding the pixel are connected to the ground with sufficiently low resistance.

This embodiment can be manufactured by the same procedure as the manufacturing method of the first embodiment. According to the present embodiment, in addition to fixing / stabilizing the voltage applied to the stray capacitance of the signal readout line, the voltage applied to the stray capacitance of the photodiode is also fixed / stabilized. Output characteristics more stable than 1 are realized.

[0037]

As described above, according to the present invention, C
By fixing / stabilizing the voltage applied to the signal readout line and the stray capacitance of the photodiode in the MOS solid-state imaging device, the output characteristics are stabilized and uniformed over the entire pixel. Thereby, good image characteristics are achieved.

[Brief description of the drawings]

FIGS. 1A and 1B are cross-sectional structural views of a vicinity of one pixel unit according to a first embodiment of a solid-state imaging device of the present invention, and FIG.
A region including the S transistor, and (b) is a region not including the MOS transistor.

FIG. 2 is an overall configuration diagram of Embodiment 1 of the solid-state imaging device of the present invention.

FIG. 3 is a manufacturing process diagram of one pixel unit according to Embodiment 1 of the solid-state imaging device of the present invention.

FIG. 4 is a diagram illustrating one pixel unit and a signal readout circuit thereof according to an embodiment of the solid-state imaging device of the present invention.

FIG. 5 shows a conventional example and a signal reading procedure of the solid-state imaging device of the present invention.

FIGS. 6A and 6B are cross-sectional structural diagrams of a vicinity of one pixel portion according to a second embodiment of the solid-state imaging device of the present invention, and FIG.
A region including the S transistor, and (b) is a region including the ground contact.

FIG. 7 is an ideal example of a signal reading system circuit according to the solid-state imaging device of the present invention.

FIGS. 8A and 8B are cross-sectional structural views of a conventional solid-state imaging device in the vicinity of one pixel portion, where FIG. 8A is a region including a switching MOS transistor, and FIG. 8B is a region not including the switching MOS transistor.

FIG. 9 is an overall configuration diagram of a conventional solid-state imaging device.

FIG. 10 is a practical circuit diagram for explaining a problem of a conventional solid-state imaging device.

FIG. 11 is a characteristic example of a conventional solid-state imaging device.

FIG. 12 is a circuit diagram of a signal readout system according to an embodiment of the semiconductor amplifier circuit of the present invention.

[Description of Signs] 31 Photodiode 32 MOS transistor 33 Horizontal drive line 34 Signal readout line 35 Electrode layer 36 Constant voltage power supply 37 Floating capacitance formed between signal readout line and electrode layer 111 Electrode layer and constant voltage power supply Connection point 115 stray capacitance 116 signal readout line 117 constant voltage power supply

Claims (9)

[Claims] 1. A semiconductor amplification circuit integrated on a semiconductor substrate, comprising: a wiring for transmitting an analog signal; and a circuit including an integration circuit having a feedback capacitance directly connected to the wiring. Is formed on the upper surface of the semiconductor substrate, and between the wiring and the semiconductor substrate, a low-resistance electrode layer is formed in an insulated state from the wiring, and during operation of the semiconductor amplifier circuit, A semiconductor amplifier circuit, wherein a constant voltage is applied to the electrode layer. 2. The semiconductor amplifier circuit according to claim 1, wherein said electrode layer is formed in an insulated state with respect to a semiconductor substrate. 3. The semiconductor amplifier circuit according to claim 1, wherein a voltage applied to the electrode layer is equal to or higher than a ground voltage of the semiconductor substrate and equal to or lower than a maximum voltage supplied to the semiconductor substrate for driving the circuit. A semiconductor amplifier circuit characterized by the following. 4. The semiconductor amplifier circuit according to claim 1, wherein a width of said electrode layer is at least 50% of a width of said wiring, and said electrode layer has a region at least partially overlapping said wiring. A semiconductor amplifier circuit comprising: 5. A plurality of photoelectric conversion regions formed on a semiconductor substrate, and formed near each of the plurality of photoelectric conversion regions.
A plurality of switching elements that are connected one-to-one with the photoelectric conversion area and selectively read out signals of the photoelectric conversion area; a plurality of signal readout lines that connect the plurality of switching elements in column units; A plurality of signal readout amplifier circuits connected one-to-one to the signal readout line, wherein a portion of the amplifier circuit connected to the signal readout line is formed by an integrating circuit. A low-resistance electrode layer is formed between the signal read line and the semiconductor substrate in an insulated state from the signal read line, and a constant voltage is applied to the electrode layer during circuit operation A solid-state imaging device characterized by the above-mentioned. 6. The solid-state imaging device according to claim 5, wherein said electrode layer is insulated from said semiconductor substrate. 7. The solid-state imaging device according to claim 5, wherein a voltage applied to the electrode layer is equal to or higher than a ground voltage of the semiconductor substrate and a maximum voltage supplied to the semiconductor substrate for driving a circuit. A solid-state imaging device characterized by the following. 8. The solid-state imaging device according to claim 5, wherein a width of the electrode layer is 50% or more of a width of the signal readout line, and the electrode layer is formed of the signal readout line and at least the signal readout line. A solid-state imaging device having an overlap region in part. 9. The solid-state imaging device according to claim 5, further comprising a low-resistance ground wiring electrically connected to a ground of a power supply circuit of the solid-state imaging device at a low resistance on a surface of the semiconductor substrate. A solid-state imaging device wherein each of the plurality of photoelectric conversion regions has a ground region connected to the low-resistance ground wiring or is adjacent to the ground region.