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JPH11121761A - Thin-film transistor - Google Patents

Thin-film transistor

Info

Publication number
JPH11121761A
JPH11121761A JP18343898A JP18343898A JPH11121761A JP H11121761 A JPH11121761 A JP H11121761A JP 18343898 A JP18343898 A JP 18343898A JP 18343898 A JP18343898 A JP 18343898A JP H11121761 A JPH11121761 A JP H11121761A
Authority
JP
Japan
Prior art keywords
layer
active layer
film transistor
thin film
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18343898A
Other languages
Japanese (ja)
Inventor
Konshu Ri
根 洙 李
Kokushin Jo
國 賑 徐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hyundai Electronics Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Industries Co Ltd filed Critical Hyundai Electronics Industries Co Ltd
Publication of JPH11121761A publication Critical patent/JPH11121761A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a thin-film transistor whose field-effect mobility is improved, whose leakage current is decreased at the same time and whose display characteristics of an AM-LCD(active matrix liquid crystal display) is improved. SOLUTION: A transparent insulating substrate 30 on the upper part of which a gate electrode is formed is provided. A gate insulating film 32 is formed on this substrate 30. An active layer 33 is formed on the gate insulating film 32 in such a way as to face a gate electrode 31. The active layer 33 comprises a double films where a microcrystalline silicon (μc-Si) layer and an amorphous silicon (a-Si: H(Cl) layer containing chlorine are sequentially formed. An etching stopper 34 is formed on the active layer 33 at the upper part of the gate. Ohmic layers 35-1 and 35-2 which expose the upper surface of the etching stopper 34 are formed on both sides of the etching stopper 34 and the active layer 33. Source and drain electrodes 36-1 and 36-2 are formed on the gate insulating film 32 and the ohmic layers 35-1 and 35-2.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は薄膜トランジスタに
関し、 特にアクティブマトリクス型液晶表示装置に用い
られる薄膜トランジスタに関する。The present invention relates to a thin film transistor, and more particularly to a thin film transistor used for an active matrix type liquid crystal display device.

【０００２】[0002]

【従来の技術】一般的に、アクティブマトリクス型液晶
表示装置(active matrix-typeliquidcrystal display ;
AM-LCD)は、奥行き方向を薄く形成可能なことから、多
様な表示装置に用いられている。このようなAM-LCD装置
において、薄膜トランジスタ(thin film transistor ;
TFT)が各画素に対するスイッチング素子として提供さ
れ、 個々の画素電極が独立的に駆動されるため、デュー
ティ(duty)比の減少に起因するコントラストが減少せ
ず、またディスプレイ容量が増加してライン数が増加さ
れる際にも視野角を確保できる特徴を持つ。2. Description of the Related Art Generally, an active matrix liquid crystal display (active matrix-type liquid crystal display;
AM-LCD) is used for various display devices because it can be formed thin in the depth direction. In such an AM-LCD device, a thin film transistor (thin film transistor;
(TFT) is provided as a switching element for each pixel, and the individual pixel electrodes are driven independently, so that the contrast due to the decrease in the duty ratio does not decrease and the display capacity increases and the number of lines increases. It has the feature that the viewing angle can be secured even when is increased.

【０００３】図１は、AM-LCD装置に用いられる一般のTF
T を示した断面図である。図１を参照すれば、 ガラスの
ような透明な絶縁基板１０上にゲート電極１１が形成さ
れ、このゲート電極１１が形成された絶縁基板１０上に
ゲート絶縁膜１２が形成される。ゲート絶縁膜１２上に
アクティブ層１３がゲート電極１１に対向して形成され
る。ゲート電極１１の上部のアクティブ層１３上にエッ
チストッパ１４が形成される。 エッチストッパ１４の上
面を露出させるソースおよびドレイン電極１６−１，１
６−２がエッチストッパ１４の両側、アクティブ層１３
及びゲート絶縁膜１２上に形成される。アクティブ層１
３とソース及びドレイン電極１６−１，１６−２との間
には、ドーピングされた非晶質シリコンからなるオーミ
ック層１５−１，１５−２が介在される。FIG. 1 shows a general TF used in an AM-LCD device.
It is sectional drawing which showed T. Referring to FIG. 1, a gate electrode 11 is formed on a transparent insulating substrate 10 such as glass, and a gate insulating film 12 is formed on the insulating substrate 10 on which the gate electrode 11 is formed. Active layer 13 is formed on gate insulating film 12 so as to face gate electrode 11. An etch stopper 14 is formed on the active layer 13 above the gate electrode 11. Source and drain electrodes 16-1 and 16-1 exposing the upper surface of the etch stopper 14
6-2 are both sides of the etch stopper 14, the active layer 13
And on the gate insulating film 12. Active layer 1
Ohmic layers 15-1 and 15-2 made of doped amorphous silicon are interposed between 3 and the source and drain electrodes 16-1 and 16-2.

【０００４】[0004]

【発明が解決しようとする課題】前述した従来のTFT に
おいて、アクティブ層１３は水素化した非晶質シリコン
(Hydrogenated amorphous silicon; a-Si : H)や微結晶
シリコン(microcrystalsilicon; μc-Si) で形成され
る。しかし、a-Si:Hがアクティブ層１３で形成される
と、a-Si:Hの低い電界効果移動度と高い光伝導度によ
り、オン電流が減少され、光に起因する漏洩電流が引き
起こされるという問題がある。反面、μc-Siがアクティ
ブ層１３で形成されると、μc-Siの高い電界効果移動度
によりオン電流が増加されるという長所はあるが、オフ
電流も増加されるという問題もある。これに伴い、スイ
ッチング素子として前述したTFT が用いられるAM-LCD装
置の表示特性が低下する。In the conventional TFT described above, the active layer 13 is made of hydrogenated amorphous silicon.
(Hydrogenated amorphous silicon; a-Si: H) and microcrystal silicon (μc-Si). However, when a-Si: H is formed in the active layer 13, the on-current is reduced due to the low field-effect mobility and high photoconductivity of a-Si: H, and light-induced leakage current is caused. There is a problem. On the other hand, when μc-Si is formed in the active layer 13, there is an advantage that on-current is increased due to high field-effect mobility of μc-Si, but there is also a problem that off-current is increased. Along with this, the display characteristics of an AM-LCD device using the above-described TFT as a switching element are degraded.

【０００５】従って、本発明の目的は、前述した従来の
問題点を解決するためのもので、電界効果移動度を向上
させると同時に漏洩電流を減少させ、AM-LCDの表示特性
を向上させることのできる薄膜トランジスタを提供する
ことにある。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-mentioned conventional problems, and to improve the field effect mobility, reduce the leakage current, and improve the display characteristics of the AM-LCD. It is to provide a thin film transistor that can be used.

【０００６】[0006]

【課題を解決するための手段】前述した本発明の目的を
達成するため、本発明にかかる薄膜トランジスタは、上
部にゲート電極が形成された透明な絶縁基板を含む。基
板上にゲート絶縁膜が形成され、アクティブ層がゲート
電極に対向しながら前記ゲート絶縁膜上に形成される。
ここで、アクティブ層は微結晶シリコン (μc-Si) 層と
塩素を含んだ非晶質シリコン(a-Si:H(Cl))層とが順次的
に積層された２重膜からなる。エッチストッパがゲート
の上部のアクティブ層上に形成され、エッチストッパと
アクティブ層の両側上にエッチストッパの上面を露出さ
せるオーミック層が形成される。また、ソース及びドレ
イン電極がゲート絶縁膜及び前記オーミック層上に形成
される。 微結晶シリコン層はチャンネルとして作用す
る。In order to achieve the above-mentioned object of the present invention, a thin film transistor according to the present invention includes a transparent insulating substrate having a gate electrode formed thereon. A gate insulating film is formed on the substrate, and an active layer is formed on the gate insulating film facing the gate electrode.
Here, the active layer is composed of a double film in which a microcrystalline silicon (μc-Si) layer and an amorphous silicon (a-Si: H (Cl)) layer containing chlorine are sequentially laminated. An etch stopper is formed on the active layer above the gate, and an ohmic layer exposing the upper surface of the etch stopper is formed on both sides of the etch stopper and the active layer. In addition, source and drain electrodes are formed on the gate insulating film and the ohmic layer. The microcrystalline silicon layer acts as a channel.

【０００７】本実施の形態において、塩素の含んだ非晶
質シリコン層は、Clを含んだガスを利用するPECVD によ
り形成された層である。望ましくは、Clを含んだガスは
SiH２Cl２とSiH４との混合ガス、 SiHCl３とSiH４との混合ガス、及びSiCl４ とSiH４との
混合ガスからなるグループから選択される一つの混合ガ
スである。また、塩素を含んだ非晶質シリコン層のCl含
量を調節してアクティブ層の光伝導度を調節する。In the present embodiment, the chlorine-containing amorphous silicon layer is a layer formed by PECVD using a gas containing Cl. Preferably, the gas containing Cl is
This is one mixed gas selected from the group consisting of a mixed gas of SiH 2 Cl 2 and SiH 4 , a mixed gas of SiHCl 3 and SiH 4, and a mixed gas of SiCl 4 and SiH 4 . Further, the photoconductivity of the active layer is controlled by controlling the Cl content of the amorphous silicon layer containing chlorine.

【０００８】[0008]

【発明の実施の形態】以下に、添付の図面を参照しなが
ら本発明の実施の形態を説明する。図２は本発明の実施
の形態による薄膜トランジスタを示した断面図である。
図２に示したように、本発明では、アクティブ層３３
が、μc-Si層３３Aと塩素を含んだ非晶質シリコン(a-S
i:H(Cl))層３３B との２重膜で形成される。ここで、μ
c-Si層３３A は高い電界効果移動度を有する。a-Si:H(C
l)層３３Bは、a-Si:H層より低い光伝導度を有する。Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 2 is a cross-sectional view illustrating a thin film transistor according to an embodiment of the present invention.
As shown in FIG. 2, in the present invention, the active layer 33 is formed.
Is the μc-Si layer 33A and chlorine-containing amorphous silicon (aS
i: H (Cl)) layer 33B. Where μ
The c-Si layer 33A has a high field effect mobility. a-Si: H (C
l) Layer 33B has a lower photoconductivity than a-Si: H layer.

【０００９】図２を参照して、前述したTFT の製造方法
を説明する。ガラスのような透明な絶縁基板３０上に、M
oTa，MoW 及びCrからなるグループから選択される一つ
の金属膜が蒸着，パターニングされてゲート電極３１が
形成される。ゲート電極３１が形成された基板上にゲー
ト絶縁膜３２が形成される。ここで、ゲート絶縁膜３２
は、SiO２膜、SiON膜、 及びSiNx膜が順次的に積層された
３重膜からなる。その後、ゲート絶縁膜３２上にμc-Si
層３３A とa-Si:H(Cl)層３３B とが順次的に蒸着され
る。この時、a-Si:H(Cl)層３３B は、Clを含んだガスを
利用してPECVD(Plasma Enhanced Chemical Vapor Depos
ition)により蒸着される。望ましくは、Clを含んだガス
は、SiH２Cl２とSiH４との混合ガス、SiHCl３とSiH４と
の混合ガス、及びSiCl４とSiH４との混合ガスからなる
グループから選択される一つの混合ガスである。Referring to FIG. 2, a method of manufacturing the above-described TFT will be described. On a transparent insulating substrate 30 such as glass,
One metal film selected from the group consisting of oTa, MoW and Cr is deposited and patterned to form the gate electrode 31. A gate insulating film 32 is formed on the substrate on which the gate electrode 31 has been formed. Here, the gate insulating film 32
Consists of a triple film in which an SiO 2 film, a SiON film, and a SiNx film are sequentially laminated. After that, the μc-Si
Layer 33A and a-Si: H (Cl) layer 33B are sequentially deposited. At this time, the a-Si: H (Cl) layer 33B is made of PECVD (Plasma Enhanced Chemical Vapor Depos) using a gas containing Cl.
)). Preferably, the gas containing Cl is selected from the group consisting of a mixed gas of SiH 2 Cl 2 and SiH 4 , a mixed gas of SiHCl 3 and SiH 4, and a mixed gas of SiCl 4 and SiH 4. Gas mixture.

【００１０】その後、a-Si:H(Cl)層３３B 上に、公知の
方法によりエッチストッパ３４が形成され、 結果物構造
の上部にドーピングされた非晶質シリコン層が蒸着され
る。次に、ドーピングされた非晶質シリコン層、a-Si:H
(Cl)層３３B とμc-Si層３３A とがパターニングされ、
エッチストッパ３４の上面を露出させるオーミック層３
５−１、３５−２と、μc-Si層３３A とa -Si:H(Cl) 層
３３B の２重膜からなるアクティブ層３３とが形成され
る。オーミック層３５−１、３５−２の物質として、ド
ーピングされた非晶質シリコン層の代りに、ドーピング
された微結晶シリコン層が用いられる。[0010] Thereafter, an etch stopper 34 is formed on the a-Si: H (Cl) layer 33B by a known method, and a doped amorphous silicon layer is deposited on the resultant structure. Next, a doped amorphous silicon layer, a-Si: H
(Cl) layer 33B and μc-Si layer 33A are patterned,
Ohmic layer 3 exposing the upper surface of etch stopper 34
5-1 and 35-2 and an active layer 33 composed of a double film of a μc-Si layer 33A and an a-Si: H (Cl) layer 33B are formed. As the material of the ohmic layers 35-1, 35-2, a doped microcrystalline silicon layer is used instead of the doped amorphous silicon layer.

【００１１】次に、結果物構造の上部にソース及びドレ
イン用金属膜が蒸着された後パターニングされ、オーミ
ック層３５−１、３５−２及びゲート絶縁膜３２上にソ
ース及びドレイン電極３６−１、３６−２が形成され
る。Next, source and drain metal films are deposited and patterned on the resultant structure, and the source and drain electrodes 36-1 and 36-1 are formed on the ohmic layers 35-1 and 35-2 and the gate insulating film 32. 36-2 is formed.

【００１２】前記のように、図３は従来のTFT の電圧−
電流特性を示したグラフで、図４は本発明に係るTFT の
電圧−電流特性を示したグラフである。図３及び図４か
ら、ゲート電圧VGが０V である時、それぞれのドレイン
電流IDを比較してみると、本発明のTFT が従来より約１
／１００程度と小さく現れる。As described above, FIG. 3 shows a conventional TFT voltage-
FIG. 4 is a graph showing current-voltage characteristics of the TFT according to the present invention. 3 and 4, when the gate voltage VG is 0 V, the drain current ID is compared.
It appears as small as about / 100.

【００１３】なお、本発明は前記実施の形態に限定され
ず、本発明の技術的思想から逸脱しない範囲内で多様に
変形させて実施可能であるのはいうまでもない。It is needless to say that the present invention is not limited to the above-described embodiment, but can be implemented with various modifications without departing from the technical idea of the present invention.

【発明の効果】前述したTFT において、ゲート電極３１
に一定電圧が印加されると、アクティブ層３３のμc-Si
層３３A にチャンネルが形成され、μc-Si層３３Aの高
い電界効果移動度によりオン電流が増加される。また、
アクティブ層３３のa-Si:H(Cl)層３３B 層の低い光伝導
度により、チャンネル上部に引き起こされる光に起因す
る漏洩電流が防止されオフ電流が減少される。又、a-S
i:H(Cl)層３３BのClの含量に従って水素量を調節し、活
性層３３の光伝導度を低くすることにより、光に起因す
る漏洩電流が一層効果的に防止される。According to the TFT described above, the gate electrode 31
When a constant voltage is applied to the active layer 33, the μc-Si
A channel is formed in the layer 33A, and the on-current is increased by the high field effect mobility of the μc-Si layer 33A. Also,
The low photoconductivity of the a-Si: H (Cl) layer 33B of the active layer 33 prevents leakage current due to light generated above the channel and reduces off current. Also, aS
By adjusting the amount of hydrogen according to the Cl content of the i: H (Cl) layer 33B and lowering the photoconductivity of the active layer 33, leakage current caused by light is more effectively prevented.

【００１４】また、前述したように、アクティブ層が高
い電界効果移動度を有するμc-Si層と、低い光伝導度を
有するa-Si:H(Cl)層との２重膜で形成され、 μc-Si層に
よりオン電流が増加され、a-Si:H(Cl)層によりオフ電流
が減少される。これに伴い、前述したTFT がスイッチン
グ素子として用いられるAM-LCDの表示特性が向上する。Further, as described above, the active layer is formed of a double film of a μc-Si layer having high field effect mobility and an a-Si: H (Cl) layer having low photoconductivity, The ON current is increased by the μc-Si layer, and the OFF current is reduced by the a-Si: H (Cl) layer. Along with this, the display characteristics of the AM-LCD in which the above-described TFT is used as a switching element are improved.

【図面の簡単な説明】[Brief description of the drawings]

【図１】従来の薄膜トランジスタを示した断面図であ
る。FIG. 1 is a cross-sectional view illustrating a conventional thin film transistor.

【図２】本発明の実施の形態による薄膜トランジスタを
示した断面図である。FIG. 2 is a cross-sectional view illustrating a thin film transistor according to an embodiment of the present invention.

【図３】従来のTFT の電圧−電流特性を示したグラフで
ある。FIG. 3 is a graph showing voltage-current characteristics of a conventional TFT.

【図４】本発明の実施の形態によるTFT の電圧−電流特
性を示したグラフである。FIG. 4 is a graph showing voltage-current characteristics of a TFT according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

３０ 絶縁基板 ３１ ゲート電極 ３２ ゲート絶縁膜 ３３Ａ μc-Si層 ３３Ｂ a-Si:H(Cl)層 ３３ アクティブ層 ３４ エッチストッパ ３５−１，３５−２ オーミック層 ３６−１，３６−２ ソース及びドレイン電極 Reference Signs List 30 Insulating substrate 31 Gate electrode 32 Gate insulating film 33A μc-Si layer 33Ba-Si: H (Cl) layer 33 Active layer 34 Etch stopper 35-1, 35-2 Ohmic layer 36-1, 36-2 Source and drain electrode

Claims (6)

【特許請求の範囲】[Claims] 【請求項１】 上部にゲート電極が形成された透明な絶
縁基板；前記基板上に形成されたゲート絶縁膜；及び、
前記ゲート電極に対向しながら前記ゲート絶縁膜上に形
成され、微結晶シリコン (μc-Si) 層と塩素を含んだ非
晶質シリコン(a-Si:H(Cl))層とが順次的に積層された２
重膜からなるアクティブ層を含むことを特徴とする薄膜
トランジスタ。A transparent insulating substrate having a gate electrode formed thereon; a gate insulating film formed on the substrate;
A microcrystalline silicon (μc-Si) layer and an amorphous silicon (a-Si: H (Cl)) layer containing chlorine are sequentially formed on the gate insulating film while facing the gate electrode. Stacked 2
A thin film transistor comprising an active layer made of a heavy film. 【請求項２】 前記微結晶シリコン層は、チャンネルと
して作用することを特徴とする請求項１記載の薄膜トラ
ンジスタ。2. The thin film transistor according to claim 1, wherein the microcrystalline silicon layer functions as a channel. 【請求項３】 前記塩素を含んだ非晶質シリコン層は、
Clを含んだガスを利用するPECVD により形成された層で
あることを特徴とする請求項１記載の薄膜トランジス
タ。3. The amorphous silicon layer containing chlorine,
2. The thin film transistor according to claim 1, wherein the thin film is a layer formed by PECVD using a gas containing Cl. 【請求項４】 前記Clを含むガスは、SiH２Cl２とSiH２
との混合ガス、SiHCl３とSiH４との混合ガス、及びSiCl
４とSiH４との混合ガスからなるグループから選択され
る一種の混合ガスであることを特徴とする請求項３記載
の薄膜トランジスタ。4. The gas containing Cl includes SiH 2 Cl 2 and SiH 2
Mixed gas, SiHCl 3 and SiH 4 mixed gas, and SiCl
4 a thin film transistor according to claim 3, wherein a from a group consisting of a gas mixture of SiH 4 is a gas mixture of one selected. 【請求項５】 前記塩素を含んだ非晶質シリコン層のCl
含量を調節して前記アクティブ層の光伝導度を調節する
ことを特徴とする請求項３記載の薄膜トランジスタ。5. The method according to claim 1, wherein said chlorine-containing amorphous silicon layer comprises Cl
4. The thin film transistor according to claim 3, wherein the content is adjusted to adjust the photoconductivity of the active layer. 【請求項６】 前記ゲート上部のアクティブ層上に形成
されたエッチストッパ；前記エッチストッパとアクティ
ブ層の両側上に形成され前記エッチストッパの上面を露
出させるオーミック層；及び、前記ゲート絶縁膜及び前
記オーミック層上に形成されたソース及びドレイン電極
を更に含むことを特徴とする薄膜トランジスタ。6. An etch stopper formed on an active layer above the gate; an ohmic layer formed on both sides of the etch stopper and the active layer to expose an upper surface of the etch stopper; A thin film transistor further comprising a source and a drain electrode formed on the ohmic layer.
JP18343898A 1997-06-30 1998-06-30 Thin-film transistor Pending JPH11121761A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1997/P30434 1997-06-30
KR1019970030434A KR100257158B1 (en) 1997-06-30 1997-06-30 Thin film transistor and method for manufacturing the same

Publications (1)

Publication Number Publication Date
JPH11121761A true JPH11121761A (en) 1999-04-30

Family

ID=19513100

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18343898A Pending JPH11121761A (en) 1997-06-30 1998-06-30 Thin-film transistor

Country Status (3)

Country Link
JP (1) JPH11121761A (en)
KR (1) KR100257158B1 (en)
TW (1) TW376588B (en)

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