JPH11121757A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to obtain a high breakdown voltage of a MOSFET and to make it possible to simplify the production process of the MOSFET, by a method wherein a second insulating film on a high-resistance semiconductor layer and a first conductivity type semiconductor layer, which are held between a source layer and a drain layer, is formed thikcer than a second insulating film at other region. SOLUTION: Low-impurity concentration first conductivity type semiconductor layers 6 and 7 are respectively formed between an n<+> source layer 4 and a p<-> layer 3 and between an n<+> drain layer 5 and the layer 3. A gate electrode 9 is formed on the layer 3 held between the layers 4 and 5 via a gate insulating film 8, which is used as a second insulating film. That is, a thermal oxide film of a thickness of 50 nm or thereabouts is formed on the layer 3 to use the thermal oxide film as the film 8 and the electrode 9 is formed on this film 8. Moreover, a mask of an area wider than that of the electrode 9 is used on the electrode 9, the insulating film 8 at the region other than the mask is peeled off, and an insulating film 8 of a thickness which is thinner than the thickness of the film 8 and is 10 nm or thereabouts is again formed on the region peeled off the film 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a thin film semiconductor device having a high breakdown voltage and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 10 is a sectional view of a conventional lateral n-type MOSFET using dielectric isolation. In the figure, reference numeral 101 denotes a silicon substrate, and an insulating film 10 is formed on the silicon substrate 101.
2 is formed, and a high-resistance p-type layer 1
03 is formed. These silicon substrates 101,
The SOI (Sili) is formed by the insulating film 102 and the p-type layer 103.
A con On Insulator substrate is formed. An n-type source layer 104 and an n-type drain layer 105 having a high impurity concentration are formed so as to sandwich the p-type layer 103. An n-type drain layer 1 is formed between the n-type source layer 104 and the p-type layer 103.
05 and the p-type layer 103, respectively.
04, n-type LDD (Lightly Doped Drain) layers 106 and 107 having a lower impurity concentration than the n-type drain layer 105 are formed.

The n-type source layer 104 and the n-type drain layer 10
5 on the p-type layer 103 sandwiched between
A gate electrode 109 is formed via the gate electrode 109. Also, n
A source electrode 110 is provided on the type source layer 104, and a drain electrode 111 is provided on the n-type drain layer 105.

Silicon nitride films 114 and 115 are formed on both side walls of gate electrode 109, and interlayer insulating film 1 is formed so as to cover gate electrode 109 and silicon nitride films 114 and 115.
12 are formed.

[0005] This MOSFET is manufactured as follows. After forming gate electrode 109, n-type LDD layer 1
Ion implantation / diffusion for forming 06 and 107 is performed. Further, a silicon nitride film 114 is formed on a side wall of the gate electrode 109,
Then, ion implantation and diffusion for forming the n-type source layer 104 and the n-type drain layer 105 are performed.

[0006]

A MOSFET in which silicon nitride films 114 and 115 are formed on the side wall of a gate electrode 109 as shown in FIG. 10 is used in a low breakdown voltage MOSFET, but has the following problems. was there.

First, after ion implantation and diffusion for forming the n-type LDD layers 106 and 107 are performed, silicon nitride films 114 and 115 are formed, and ion implantation and diffusion are further performed to form the n-type source layer 104 and the n-type Since the drain layer 105 is formed, the number of steps increases and the manufacturing process becomes complicated.

In order to increase the breakdown voltage of the element, n
Although it is necessary to widen the opening widths of the LDD layers 106 and 107, the silicon nitride film 114
The method of forming 115 can only cope with an opening width of about 100 nm.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device capable of obtaining a high breakdown voltage and simplifying a manufacturing process, and a method of manufacturing the same.

[0010]

[Means for Solving the Problems]

In order to solve the above-mentioned problems, the present invention is directed to a first aspect of the present invention, which is a substrate, a first insulating film formed on the substrate, and a first insulating film formed on the first insulating film. A high-resistance semiconductor layer, a first conductivity type source layer formed on the surface of the high-resistance semiconductor layer, and a drain layer formed at a predetermined distance from the source layer on the surface of the high-resistance semiconductor layer. A first impurity layer having a lower impurity concentration than the source layer and the drain layer formed between the high-resistance semiconductor layer and the source layer and between the high-resistance semiconductor layer and the drain layer;
A conductive semiconductor layer, a second insulating film formed on the high-resistance semiconductor layer, and a second insulating film on the high-resistance semiconductor layer sandwiched between the source layer and the drain layer. A gate electrode formed, a source electrode provided on the source layer, and a drain electrode provided on the drain layer, the high-resistance semiconductor layer sandwiched between the source layer and the drain layer, and A semiconductor device is provided, wherein the second insulating film on the first conductivity type semiconductor layer is thicker than the second insulating film in another region.

According to a third aspect of the present invention, there is provided an SOI substrate having a substrate, a first insulating film formed on the substrate, and a high resistance semiconductor layer formed on the first insulating film. Forming a second insulating film, forming a gate electrode on the second insulating film, and preparing a mask having a larger area than the gate electrode on the gate electrode, Removing the second insulating film;
Forming the second insulating film again in a region other than the lower portion of the mask so as to be thinner than the second insulating film in the lower region of the mask; and implanting ions through the second insulating film, A drain layer and a first conductivity type source layer are formed in a region other than the lower portion, and a first conductivity type semiconductor layer having a lower impurity concentration than the source layer and the drain layer is formed in a region other than below the gate electrode under the mask. And providing a source electrode on the source layer and a drain electrode on the drain layer.

(Operation) According to the present invention, the thickness of the second insulating film under and around the gate electrode is larger than the thickness of the second insulating film in other regions. Therefore, by implanting ions through the second insulating film, the first conductive type semiconductor layer is simultaneously formed in the region around the gate electrode, and the drain layer and the first conductive type source layer are simultaneously formed in the region where the second insulating film is thin. Can be formed, and the manufacturing process is simplified. Further, since the region where the second insulating film is thick can be set arbitrarily, a high withstand voltage can be obtained by widening the region around the gate electrode where the second insulating film is thick. Note that when a polycrystalline semiconductor is used for the high-resistance semiconductor layer, a semiconductor device can be manufactured at low cost.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a cross-sectional view of a high breakdown voltage lateral n-type MOSFET according to a first embodiment of the present invention.

In the figure, 1 is a single crystal silicon substrate,
A first insulating film 2 using an oxide film is formed on a silicon substrate 1, and a p-type layer 3 as a high-resistance semiconductor layer using polycrystalline silicon of a polycrystalline semiconductor is formed on the insulating film 2. I have. These silicon substrate 1, insulating film 2, p-type layer 3
Thus, an SOI substrate is formed. A high impurity concentration n-type source layer 4 and an n-type drain layer 5 as a first conductivity type source layer are formed so as to sandwich the p-type layer 3.
Between the n-type drain layer 5 and the p-type layer 3 and between the n-type drain layer 5 and the p-type layer 3 as a first conductivity type semiconductor layer having a lower impurity concentration than the n-type source layer 4 and the n-type drain layer 5, respectively. n-type LDD
Layers 6 and 7 are formed.

Polycrystalline silicon is formed on the p-type layer 3 sandwiched between the n-type source layer 4 and the n-type drain layer 5 via a gate insulating film 8 as a second insulating film using an oxide film. The used gate electrode 9 is formed. Also, the n-type source layer 4
Are provided with a source electrode 10 using Al, and a drain electrode 11 also using Al on the n-type drain layer 5.

In this MOSFET, the drain side is positive and the source side is negative, and a voltage higher than the threshold voltage with respect to the source is applied to the gate electrode 9 by applying a voltage to the gate electrode 9.
An n-type channel is formed on the surface of the lower p-type layer 3, and the element is turned on. In this ON state, if the voltage applied to the gate electrode 9 is reduced below the threshold, the n-type channel disappears,
The element is turned off.

The n-type LDD layers 6 and 7 are provided in order to prevent a change in threshold voltage with time and deterioration of mutual conductance due to hot carriers, and extend the electric field in the drain pinch-off region to the n-type LDD layer 7. This can reduce the maximum electric field and suppress generation of hot carriers. The position where the maximum electric field is reached is the gate electrode 9.
Therefore, even if hot carriers are generated, the generated hot carriers are not injected into the insulating film. Therefore, as compared with the case where the n-type LDD layers 6 and 7 are not formed, the element can be operated even if the channel length is short, and a higher breakdown voltage can be obtained.

Next, the manufacturing process of this MOSFET is shown in FIG.
4 to FIG. 4. First, FIG.
As shown in FIG.
BOX oxidation for about 100 min.
A thermal oxide film having a thickness of about 00 nm is formed to form an insulating film 2. Instead of forming a thermal oxide film, a CVD oxide film may be deposited. Further, the thickness of the insulating film 2 may be about 100 to 500 nm. On this insulating film 2, a thickness of 150 to 200 nm
A degree of amorphous silicon layer 3 'is deposited.

Next, as shown in FIG. 2B, B ions are implanted into the amorphous silicon layer 3 'at an acceleration voltage of 30 Ke.
V, at a dose of 5 × 10 ¹² / cm ² . After this 600
Annealing is performed by heat treatment at about 800 ° C. for about 2 to 20 hours, so that the amorphous silicon layer is polycrystallized, and a high-resistance p-type layer 3 is formed. In order to improve transistor characteristics by increasing the crystal grain size, a step of performing a heat treatment at 1100 ° C. or more after annealing is added. Either the ion implantation or the annealing may be performed first, but better characteristics are obtained by performing the annealing after the ion implantation. Further, non-doping may be performed without performing ion implantation.

Subsequently, as shown in FIG. 2C, the p-type layer 3
A thermal oxide film having a thickness of about 50 nm is formed thereon by performing 10% HCl oxidation at about 900 ° C. for about 120 minutes to form a gate insulating film 8. In order to obtain a high withstand voltage, the thickness of the gate insulating film 8 is preferably thick, but generally the range is about 20 to 50 nm.

Thereafter, as shown in FIG. 2D, polycrystalline silicon is deposited on the gate insulating film 8 and patterned to have a thickness of 200 nm, a gate width of 10 μm, and a gate length of 0.
A gate electrode 9 having a thickness of about 15 to 2 μm is formed.

Further, as shown in FIG. 3E, a mask 13 having a larger area than the gate electrode 9 is prepared on the gate electrode 9, and the gate insulating film 8 in a region other than the lower portion of the mask 13 is formed using NH ₄ F. It is peeled off by wet etching.

Next, as shown in FIG.
By performing a heat treatment for 15 minutes, an insulating film 8 having a thickness of about 10 nm, which is thinner than the gate insulating film 8, is formed again in a region where the insulating film 8 is peeled off. This functions as a protective film for avoiding damage to the silicon surface during the subsequent ion implantation step.

Subsequently, as shown in FIG. 3 (g), As ions are implanted at an acceleration voltage of 30 KeV and a dose of 3 × 10 ¹⁴ to 3 × 10 ¹⁴ .
It is performed at 5 × 10 ¹⁵ / cm ² . Note that P ions may be implanted instead of As ions. Since the polycrystal is made amorphous by the ion implantation, the polycrystal is
RTA (Rapid Theo) for 30 seconds or 900 ° C for 30 seconds
rmal Anneal) to perform polycrystallization.

As a result, as shown in FIG. 3H, an n-type LDD layer 6 having an impurity concentration of 1 × 10 ¹⁸ / cm ³ and a width of about 0.5 μm is formed in a portion of the lower portion of the mask other than immediately below the gate electrode 9. 7 has an impurity concentration of 1.times.
An n-type source layer 4 and an n-type drain layer 5 of about 10 ²⁰ / cm ³ are formed. These impurity concentrations are obtained when the dose is 3 × 10 ¹⁵ / cm ² . The width of the n-type LDD layers 6 and 7 may be about 0.5 to 10 μm. The difference in impurity concentration between the n-type LDD layers 6 and 7 and the n-type source layer 4 and the n-type drain layer 5 is that the n-type LDD layers 6 and 7 have different impurity concentrations.
This is because the thickness of the insulating film 8 is different between the upper part of the N-type LDD layers 6 and 7 and the upper part of the n-type LDD layers 6 and 7. Therefore, the depth at which the impurity reaches the p-type layer 3 is small, and the amount of the impurity is small. If the width of the n-type LDD layers 6 and 7 is about 0.5 μm, a withstand voltage of about 10 V can be obtained.

Further, as shown in FIG.
D (Chemical Vapor Deposition)
An interlayer insulating film 12 is formed by depositing a CVD oxide film having a thickness of about 300 nm by using the method n).

Thereafter, as shown in FIG. 4 (k), the interlayer insulating film 12 and the insulating film 8 are peeled off by etching using the SiO ₂ -RIE method to form the n-type source layer 4 and the n-type drain layer 5. A source electrode 10 and a drain electrode 11 that contact each other are formed.

Then, the interlayer insulating film 12, the source electrode 10,
An interlayer insulating film (not shown) is further formed on the drain electrode 11 to a thickness of about 1 μm, and the upper portions of the source electrode 10 and the drain electrode 11 of the interlayer insulating film (not shown) are formed of SiO ₂ −
Peeling is performed by etching using the RIE method, and a second-layer source electrode and a drain electrode (not shown) that are in contact with the source electrode 10 and the drain electrode 11 are formed in this portion, thereby completing the device.

According to the present embodiment, by using a relatively thick gate insulating film 8 for obtaining a high breakdown voltage and a relatively thin insulating film 8 functioning as a protective film at the time of ion implantation, one As ion , The n-type LDD layers 6, 7 and the n-type source layer 4, n-type drain layer 5 can be formed simultaneously.
Therefore, ion implantation for forming an n-type LDD layer and n
MOS as shown in FIG. 10 which requires two ion implantations for forming a source layer and an n-type drain layer.
The manufacturing process can be simplified as compared with the FET.

Here, it is assumed that an element as shown in FIG. 5 is formed in which the thickness of the insulating film 8 above the n-type LDD layer is smaller than the thickness of the insulating film 8 below the gate electrode. The drain side is positive,
In an off state of an element in which the source side is negative and the gate voltage is equal to or lower than the threshold, a large potential difference is applied between the gate and the drain. At this time, the thickness of the insulating film 8 formed of the thermal oxide film on the n-type LDD layers 6 and 7 is thin, and the interlayer insulating film formed by the CVD oxide film extends to a portion below the gate electrode 9 above the n-type LDD layers 6 and 7. In the device having the film 12 as shown in FIG. 5, breakdown of the device is likely to occur due to the presence of the CVD oxide film having a lower film quality than the thermal oxide film.

On the other hand, in the device of this embodiment, n
Since the portion below the gate electrode above the type LDD layers 6 and 7 is composed of only a thermal oxide film having a better film quality than the CVD oxide film, breakdown is less likely to occur as compared with the device of FIG. .

(Second Embodiment) FIG. 6 shows a second embodiment of the present invention.
1 is a cross-sectional view of a high withstand voltage, lateral n-type MOSFET according to the embodiment. The same parts as those in FIGS. 1 to 5 are denoted by the same reference numerals, and detailed description is omitted.

The MOSFET according to the present embodiment is the MO shown in FIG.
The difference from the SFET is that the width of the n-type LDD layers 6 and 7 is 3 μm.
m. Thereby, a withstand voltage of about 50 V can be obtained.

Since the width of the n-type LDD layers 6 and 7 can be increased only by using a mask having a large area, the width of the n-type LDD layers 6 and 7 can be arbitrarily formed, and a desired breakdown voltage can be easily obtained. Element can be obtained.

(Third Embodiment) FIG. 7 shows a third embodiment of the present invention.
1 is a cross-sectional view of a high withstand voltage, lateral n-type MOSFET according to the embodiment.

The MOSFET according to the present embodiment corresponds to the MO shown in FIG.
The difference from the SFET is that the n-type LDD on the n-type source layer 4 side
The point is that the width differs between the layer 6 and the n-type LDD layer 7 on the n-type drain layer 5 side. More specifically, the width of the n-type LDD layer 6 is set to 0.
5 μm, and the width of the n-type LDD layer 7 is 3 to 4 μm. In order to obtain a high withstand voltage, the width of the LDD layer on the drain side may be increased. According to the present invention, the width of the n-type LDD layer can be arbitrarily formed. It also becomes easier. In addition, by increasing only the width of the LDD layer on the drain side, the element area can be reduced even with an element having the same withstand voltage as compared with the related art.

(Fourth Embodiment) FIG. 8 shows a fourth embodiment of the present invention.
1 is a cross-sectional view of a high withstand voltage, lateral n-type MOSFET according to the embodiment.

The MOSFET according to the present embodiment is the MO shown in FIG.
The difference from the SFET is that the thickness of the p-type layer 3 is as thick as about 500 nm and the n-type source layer 4, the n-type drain layer 5, and the n-type L
The point is that the thickness of the DD layers 6 and 7 is about 350 nm and does not reach the insulating film 2. The n-type source layer 4 and the n-type drain layer 5 each have a LOCOS (Local) for element isolation.
Oxidation of Silicon oxide films 14 and 15 are adjacent to each other.

Although not shown, the LOCOS oxide films 14 and 15 are also formed in the devices shown in FIGS. 1, 6 and 7. At the time of the wet etching shown in FIG.
The LOCOS oxide film 1 as well as the upper part of the gate electrode 9
A mask is also provided on the upper portions of the LOCOS oxide films 14 and 15 to prevent the LOCOS oxide films 14 and 15 from being etched.

By adopting such a structure in which the n-type source layer 4, the n-type drain layer 5, and the n-type LDD layers 6, 7 do not reach the insulating film 2, the n-type source layer 4, the n-type drain layer 5, n
When ion implantation for forming the LDD layers 6 and 7 is performed, a crystal portion remains under the n-type source layer 4, the n-type drain layer 5, and the n-type LDD layers 6 and 7, and the crystal portion is used as a seed. The n-type source layer 4, the n-type drain layer 5,
Good crystallinity is obtained as compared with the devices of FIGS. 1, 6, and 7 in which the n-type LDD layers 6 and 7 reach the insulating film 2, and as a result, interface scattering is suppressed and current characteristics are improved. Become.

(Fifth Embodiment) FIG. 9 shows a fifth embodiment of the present invention.
1 shows a cross-sectional view of a semiconductor device according to an embodiment. This semiconductor device has a vertical IGBT (Ins
ullated GateBipolar Transi
Stor) or MOSFET 16 and an intelligent power element in which MOSFET 17a and a bipolar transistor 17b of a control circuit that controls the MOSFET 16 are integrated, and the MOSFETs of the first to fourth embodiments are used as the MOSFET 17a of the control circuit.

First, a vertical IGBT (MOSFET) 16
Will be described. An n-type buffer layer 1 having a higher impurity concentration is formed on one surface of an n-type single-crystal silicon substrate 1.
8 are formed, and a p-type or n-type drain layer 19 is formed on the surface of the n-type buffer layer 18. IGBT when the drain layer 19 is p-type, and MO when the drain layer 19 is n-type.
An SFET will be formed. On the drain layer 19, a drain electrode 20 is provided.

On the other surface of the substrate 1, a p-type base layer 21 is formed.
Are selectively formed, and an n-type source layer 22 is selectively formed on the surface of the p-type base layer 21. Further, a p-type contact layer 23 is selectively formed adjacent to the n-type source layer 22.

A gate electrode 25 is formed on a p-type base layer 21 sandwiched between an n-type source layer 22 and an n-type substrate 1 with a gate insulating film 24 interposed therebetween.
6 are provided.

The n-type source layer 22 and the p-type contact layer 23 have a source electrode 2 in contact with them.
7 are provided. Next, the MOSFET 17a will be described.

As described above, the MOSFETs 17a employ the MOSFETs of the first to fourth embodiments, and the MOSFET 17a is formed on the insulating film 2 formed on the substrate 1. 28 denotes an electrode on the gate electrode 9 and 29 denotes an interlayer insulating film. Although only an n-type MOSFET is shown in the figure for convenience, a p-type MOSFET is actually formed, and CM
An OS is formed.

Next, the bipolar transistor 17b will be described. This bipolar transistor is of an npn type. An n-type emitter layer 30 and a p-type base layer 3 using the same polycrystalline silicon as the MOSFET 17a on the insulating film 2.
1. An n-type collector layer 32 and an n-type collector layer lead-out region 33 are formed adjacent to each other. A collector electrode 36 is formed in each of the collector layer lead-out regions 33. pnp
It is a matter of course that a transistor of the type may be formed.

A control circuit can be formed by using a BiCMOS in which the bipolar transistor 17b and the above-mentioned CMOS are combined. In this embodiment, the same effects as those of the first to fourth embodiments can be obtained for the MOSFET of the control circuit,
Polycrystalline silicon used for the FET and the bipolar transistor can be formed simultaneously, and an intelligent power element can be easily formed.

The embodiment of the present invention has been described above.
The present invention is not limited to the above embodiment.
It is also possible to reverse all the conductivity types of the above embodiments. If a p-type drain layer is formed instead of the n-type drain layer 5, an IGBT can be formed. Further, single crystal silicon or amorphous silicon may be used as the high resistance semiconductor layer instead of polycrystalline silicon. In the case of using single crystal silicon, an SOI substrate using direct bonding or an SOI substrate using SIMOX can be used. In this case, B ion is about 3 × 10 ¹³ / cm ² ,
The dose of s ions may be about 3 × 10 ¹⁵ / cm ² .

[0050]

As described above, according to the present invention, it is possible to provide a semiconductor device capable of obtaining a high breakdown voltage and simplifying the manufacturing process, and a method of manufacturing the same.

[Brief description of the drawings]

FIG. 1 shows a MOSFE according to a first embodiment of the present invention.
Sectional drawing of T.

FIG. 2 is a diagram showing a MOSFE according to the first embodiment of the present invention;
T manufacturing process sectional drawing.

FIG. 3 is a diagram showing a MOSFE according to the first embodiment of the present invention;
T manufacturing process sectional drawing.

FIG. 4 is a diagram showing a MOSFE according to the first embodiment of the present invention;
T manufacturing process sectional drawing.

FIG. 5 is a diagram showing a MOSFE according to the first embodiment of the present invention;
Sectional drawing of MOSFET compared with T.

FIG. 6 shows a MOSFE according to a second embodiment of the present invention.
Sectional drawing of T.

FIG. 7 shows a MOSFE according to a third embodiment of the present invention;
Sectional drawing of T.

FIG. 8 shows a MOSFE according to a fourth embodiment of the present invention.
Sectional drawing of T.

FIG. 9 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 10 is a cross-sectional view of a conventional MOSFET.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Substrate 2, 8 ... Insulating film 3 ... High resistance p-type layer 4 ... n-type source layer 5 ... n-type drain layer 6, 7 ... n-type LDD layer 9 ... gate electrode 10 ... source electrode 11 ... drain electrode 12 ... Interlayer insulating film 13: Mask

Claims (4)

[Claims] A first insulating film formed on the substrate; a high-resistance semiconductor layer formed on the first insulating film; and a high-resistance semiconductor layer formed on a surface of the high-resistance semiconductor layer. A source layer of a first conductivity type; a drain layer formed on the surface of the high-resistance semiconductor layer at a predetermined distance from the source layer; a high-resistance semiconductor layer and the source layer; a high-resistance semiconductor layer; A first conductivity type semiconductor layer having a lower impurity concentration than the source layer and the drain layer formed between the drain layer and the drain layer, a second insulating film formed on the high resistance semiconductor layer, the source layer and the drain layer A gate electrode formed on the high-resistance semiconductor layer interposed therebetween through the second insulating film; a source electrode provided on the source layer; and a drain electrode provided on the drain layer. Become The high-resistance semiconductor layer sandwiched between the source layer and the drain layer and the second insulating film on the first conductivity type semiconductor layer are thicker than the second insulating film in another region. Semiconductor device. 2. The semiconductor device according to claim 1, wherein said high-resistance semiconductor layer uses a polycrystalline semiconductor. 3. A second insulating film is formed on an SOI substrate including a substrate, a first insulating film formed on the substrate, and a high-resistance semiconductor layer formed on the first insulating film. Forming a gate electrode on the second insulating film; preparing a mask having a larger area than the gate electrode on the gate electrode; and forming a second insulating film in a region other than the lower portion of the mask. Peeling off; forming the second insulating film again in a region other than the lower portion of the mask so as to be thinner than the second insulating film in the lower region of the mask; and ionizing the ions through the second insulating film. Is implanted, and a drain layer and a first conductivity type source layer are formed in a region other than below the mask, and a first conductive type having a lower impurity concentration than the source layer and the drain layer is formed in a region other than below the gate electrode under the mask. Type semiconductor layer The method of manufacturing a semiconductor device comprising the steps of forming, that the source electrode on the source layer and a step of providing a drain electrode on said drain layer. 4. The method according to claim 3, wherein the high resistance semiconductor layer uses a polycrystalline semiconductor layer.