JPH11121608A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which expands the margin of etching time for the chemical-mechanical polishing and stably reduce steps at embedded element isolating regions. SOLUTION: This manufacturing method comprises forming an SiO2 film 302 on an Si substrate 301, forming a first protective film 303 on the SiO2 film, etching the protective film 303, SiO2 film 302 and a substrate 301 through lithography and dry etching to form trenches 304 for forming element isolating regions, forming a second protective film 307 on an insulator in the trenches, planarizing the substrate surface to form embedded element isolating regions inside, after the formation of the film 307. At this time, relations t1+t2<t3+t4 and t2<t3 are made to be satisfied where t1, t4 are the thicknesses of the protective films 303, 307, t2 is the depth of the trench, and t3 is the thickness of the insulator 306.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a buried element isolation region of a semiconductor device.

[0002]

2. Description of the Related Art With the recent demand for higher integration of semiconductor elements and flattening of the semiconductor surface, conventional local selective oxidation (LOC) has been required.
Development of a new element isolation method that replaces the (OS) method is in progress. For example, the buried device isolation (STI) method in which an insulator is filled in a narrow deep groove formed in a silicon substrate to form a buried device isolation region is to reduce the area of the device isolation region as compared with the conventional LOCOS method. Can be
This is advantageous for miniaturization and high integration of elements.

Here, a conventional buried element isolation method will be described with reference to FIG. First, a groove 104 for forming an element isolation region is formed in, for example, a silicon (silicon) substrate 101. At this time, first, a region where an element is to be formed on the Si substrate 101 (for example, the source, drain,
A thin thermal oxide film (silicon oxide film; SiO ₂ film) for protecting the gate formation region) is formed, and a first protective film (stopper material; for example, a polycrystalline silicon film) 103 is formed for the same purpose. accumulate.

Next, the polycrystalline silicon film 10 is formed by photolithography and dry etching.
3, the thermal oxide film and the silicon substrate 101 are sequentially etched to form a trench 104 for forming an element isolation region.

Next, a thermal oxide film (SiO _{2) is formed} on the entire surface of the substrate.
After the film 102 is formed, an insulator 106 such as silicon oxide is deposited on the entire surface of the substrate in order to form an element isolation region by filling the inside of the groove 104 with an insulator.

Next, in order to prevent a decrease in the thickness of the insulator 106 inside the trench 104 (field region), a polycrystalline Si film is formed on the entire surface of the substrate at the same height as the first protective film 103. After that, patterning is performed by a photolithography method, a dry etching method, or the like, and a second process is performed on a part of the insulator 106 inside the groove 104.
Of the protective film (stopper material) 107 is formed.

Next, CMP (Chemical Mechanical Poli)
A buried element isolation region is obtained inside the trench 104 by flattening the surface on the semiconductor substrate by a shing (chemical mechanical polishing) method.

When the surface on the substrate is flattened by the CMP method as described above, the polishing rate varies depending on the unevenness corresponding to the underlying pattern. In particular, the polishing rate depends on the stress distribution of the polishing cloth (cloth) of the CMP apparatus. The feature is that a phenomenon (hereinafter, referred to as dishing) occurs in which the etching rate is increased in a wide pattern formation region or a pattern interval region (sousse region).

That is, when the conventional buried element isolation method is applied, for example, as shown in FIG. 4, when the first stopper material 203 in a wide area is formed on the semiconductor substrate 201, as described above. When the surface on the substrate is flattened by the CMP method, the first stopper material 103 is quickly polished by dishing. In FIG. 4,
202 is a thermal oxide film, 205 is a region where an element is to be formed, 206
Is an insulator.

This phenomenon narrows the margin of the etching time by the CMP method, causes overetching of the first stopper material 103 in the region where the element is to be formed, and reduces the absolute step between the buried element isolation region and the region where the element is to be formed. There are problems such as inability to reduce.

As a result, the electrical characteristics and reliability of the device are degraded, such as an increase in leakage current and variation in characteristics. Therefore, in order to realize a high-performance and high-reliability semiconductor device, the film structure before CMP is
A structure (a structure capable of reducing the effect of dishing) taking into account dishing during polishing by the P method is required.

However, the conventional method of forming the buried element isolation region as described above does not propose a film structure that takes into account dishing at the time of polishing by the CMP method. Since the margin of the etching time by the CMP method is narrow, it is difficult to stably form the buried element isolation region having a low step with good reproducibility, which is not practical.

[0013]

As described above, the conventional method for forming the buried element isolation region does not employ a structure capable of reducing the influence of dishing, so that the margin of etching time by the CMP method is narrow and low. There is a problem that it is difficult to stably form the buried element isolation region of the step with good reproducibility.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a method of manufacturing a semiconductor device capable of expanding a margin of an etching time by a CMP method and stably reducing a step of a buried element isolation region. The purpose is to do.

[0015]

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a silicon oxide film on a semiconductor substrate; forming a first protective film on the silicon oxide film; Forming a groove for forming an element isolation region by sequentially etching the first protective film, the silicon oxide film, and the semiconductor substrate by using a lithography method and a dry etching method; and forming the groove on the semiconductor substrate after forming the groove. Depositing an insulator on the insulator, forming a second protective film on the insulator inside the groove, and chemically mechanically polishing the surface of the semiconductor substrate after the second protective film is formed. Forming a device isolation region inside the groove,
The thickness t1 of the first protective film, the depth t2 of the groove, the thickness t3 of the insulator, and the thickness t4 of the second protective film satisfy the following relationships: t1 + t2 <t3 + t4, t2 <t3. It is characterized by the following.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings. 1 and 2 show a part of a step of forming a buried element isolation region according to a first embodiment of a method of manufacturing a semiconductor device of the present invention.

First, as shown in FIG. 1, a trench 30 having a high aspect ratio and a depth t 2 for forming an element isolation region is formed in an Si substrate 301 having, for example, an N-type (100) crystal plane.
4 is formed.

At this time, first, a thin thermal oxide film (for example, a 20 nm SiO ₂ film) for protecting a region where an element is to be formed on the Si substrate 301 (for example, a source / drain / gate formation region of a MOS transistor) is formed. Further, for the same purpose, a first protective film (stopper material) having a thickness of t1.
As 303, a polycrystalline Si film is deposited by, for example, a CVD (chemical vapor deposition) method.

Next, the polycrystalline Si film 303 is formed by using a photolithography method, a dry etching method or the like.
, The SiO ₂ film and the Si substrate 301 are sequentially etched to form a groove 304.

Next, a thermal oxide film (SiO _{2) is formed} on the entire surface of the substrate.
After forming the film) 302, in order to form the inner element isolation region filled with insulating material of the groove 304, an insulator 306, such as SiO ₂ film having a thickness of t3 by the substrate over the entire surface, for example, CVD method accumulate.

Next, in order to prevent a decrease in the thickness of the insulator 306 inside the trench 304 (field region), a polycrystalline Si film having a thickness of t4 is deposited on the entire surface of the substrate by, for example, a CVD method. The groove 304 is patterned by a lithography method and a dry etching method.
A second protective film (stopper material) 307 is formed on a part of the insulator 306 inside the substrate.

Next, as shown in FIG. 2, a buried element isolation region is obtained inside the groove 304 by flattening the surface on the substrate by the CMP method. At this time, as shown in FIG. 1, the film structure of the element formation planned region 305 and the element isolation region (field region) 306 before CMP is such that the thickness t1 of the first protective film 303 and the depth of the groove 304 t2
The thickness t3 of the insulator 306 and the thickness t4 of the second protective film 307 are t1 + t2 <t3 + t4, t2 <
The relationship of t3 is satisfied.

That is, since the surface height of the second protective film 307 is set higher than the surface height of the first protective film 303, the surface on the substrate is flattened by the CMP method as shown in FIG. In this case, it is possible to reduce the effect of a phenomenon (dishing) in which the etching rate is increased in a wide buried element isolation region or a wide element formation region due to stress distribution of a polishing cloth of a CMP apparatus.

Therefore, over-etching of the first protective film 303 during polishing by the CMP method can be prevented, and a sufficient margin for the etching time can be secured. Thereafter, after removing the protective film 307, heat treatment for injecting and activating impurities into a channel / well region (not shown) in a region where an element is to be formed, forming a gate electrode of the element (MOS transistor), and forming an element ( MOS transistor)
The device is formed by forming a drain / gate electrode and the like.

That is, according to the method of forming the buried element isolation region of the above embodiment, the height position of the protective film before the CMP is defined, thereby reducing (relaxing) the influence of dishing during polishing by the CMP method. CM
The margin of the etching time at the time of polishing by the P method can be expanded.

This makes it possible to form a buried element isolation region having a low step with good reproducibility. Therefore, it is possible to sufficiently suppress the deterioration of the electrical characteristics and the reliability of the element, such as an increase in leakage current and an increase in variation in characteristics, and to provide a semiconductor device with high performance and high reliability with good reproducibility. It can be realized.

The first protective film 303 is not limited to the polycrystalline Si film, but may be made of another material such as Si or Si.
Or a conductive film of a metal such as silicon nitride (SiN), titanium nitride (TiN), carbon C or a metal containing carbon C, or tungsten W. good.

Similarly, the second protective film 307 is not limited to the polycrystalline Si film, but may be made of another material such as Si or S
a conductive film of a metal such as i, titanium nitride (TiN), or silicon nitride (SiN);
Alternatively, a conductive film of carbon C or a metal containing carbon C, or tungsten W may be used.

[0029]

As described above, according to the present invention, CMP
It is possible to provide a method of manufacturing a semiconductor device in which a margin of an etching time by the method can be expanded and a step in a buried element isolation region can be stably reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a part of a step of forming a buried element isolation region according to a first embodiment of a method of manufacturing a semiconductor device of the present invention.

FIG. 2 is a sectional view showing a step of flattening a surface on a substrate by a CMP method following the step of FIG. 1;

FIG. 3 is a cross-sectional view showing a part of a step of forming a buried element isolation region by a conventional buried element isolation method.

FIG. 4 is a cross-sectional view for explaining a phenomenon (dishing) in which the etching rate over a wide element formation planned region is increased in the process of FIG. 3;

[Explanation of symbols]

Reference numeral 301 denotes a semiconductor substrate (Si substrate), 302 denotes a thermal oxide film (SiO ₂ film), 303 denotes a first protective film (polycrystalline Si film), 304 denotes a groove, 305 denotes a region where an element is to be formed, and 306 denotes an insulator ( SiO ₂ film), 307 ... second protective film (polycrystalline Si film).

Continued on the front page (72) Inventor Shiretomo Matsuoka 1 Toshiba-cho, Komukai Toshiba-cho, Saisaki-ku, Kawasaki-shi, Kanagawa Inside the Toshiba R & D Center

Claims (3)

[Claims] A step of forming a silicon oxide film on the semiconductor substrate; a step of forming a first protective film on the silicon oxide film; and a step of forming the first protective film, the silicon oxide film, and the semiconductor substrate. A step of forming a groove for forming an element isolation region by sequentially etching using a lithography method and a dry etching method; a step of depositing an insulator on a semiconductor substrate after the formation of the groove; Forming a second protective film on the insulator; flattening the surface of the semiconductor substrate after the second protective film is formed by a chemical mechanical polishing method to form an element isolation region embedded in the groove; Forming the first protective film thickness t1, the groove depth t2, the insulator thickness t3, and the second protective film thickness t4, where t1 + t2 <t3 + t4. characterized by satisfying the relationship of t2 <t3 A method for manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first protective film is a conductive film of silicon or a metal containing silicon, silicon nitride (SiN), or titanium nitride (SiN). A method for manufacturing a semiconductor device, comprising: a conductive film such as TiN), carbon or a metal containing carbon, or tungsten. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the second protective film is a conductor film of silicon or a metal containing silicon, silicon nitride (SiN), or titanium nitride. A method for manufacturing a semiconductor device, comprising: a conductive film such as a nitride (TiN), carbon or a metal containing carbon, or tungsten.