JPH11120762A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance a memory access speed by dividingly controlling cache memory cells to eliminate unwanted data transfers. SOLUTION: Only a cache memory cell being at a side performing data transfer is set to an activated state by arranging sense amplifiers 2a, 2d and cache memory cells 3a, 3b alternately at both sides of a memory array 1, by arranging the sense amplifiers 2a, 2b every bit line pair 10a, 10b and 11a, 11b, by arranging the cache memory cells 3a, 3b every cache data line, by connecting respective cache data line pairs 30a, 30b and 31a, 31b to the bit line pairs 10a, 10b and 11a, 11b via transfer gates and by allowing transfer control circuits 4a, 4b to respectively and independently control a data transfer in accordance with selection control signals 49a, 49b and control signals 47, 48. Thus, data transfers from prescribed selected memory cells to prescribed cache memory cells are selectively executed to perform only needed data transfer and the lowering of the access speed of a DRAM due to unwanted data transfers can be avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a semiconductor memory device having a cache memory and capable of selectively transferring data between the semiconductor memory device and the cache memory.

[0002]

2. Description of the Related Art A conventional semiconductor memory device is, for example, shown in FIG.
Has the configuration shown in FIG. As shown in the figure, the semiconductor memory device of the present embodiment includes a memory cell array 1, a sense amplifier array 2, a cache memory array 3, and a transfer control circuit 4.

[0005] The memory cell array 1 is configured by arranging a plurality of memory cells connected to an intersection with a plurality of word lines and bit line pairs arranged in a matrix. In FIG. 3, for convenience of explanation, two word lines 20, 21 and two pairs of bit lines 10a, 10b, 11a, 11b, and a pair of these word lines and bit lines are used. The example shows four memory cells 12a, 12b, 14a, 14b connected to the intersection. As shown, each memory cell is a general DRAM memory cell. That is, it is composed of one transistor and one capacitor.

The sense amplifier array 2 includes a plurality of sense amplifiers arranged for each bit line pair. In this example, the sense amplifier 22 connected to the bit line pair 10a, 10b and the bit line pair 11a, 11
Only the sense amplifier 24 connected to the line b is shown.

[0005] The cache memory array 3 is constituted by a plurality of cache memory cells connected to each cache data line pair. In FIG. 3, a cache memory cell 32 and a cache data line pair 31a, 31b connected to a cache data line pair 30a, 30b are shown.
Is shown only the cache memory cell 34 connected to the memory cell. Cache memory cells 32 and 34 are both connected to cache drive signal lines 40a and 40b.

Note that the cache data line pair 30a, 30
b are connected to bit line pairs 10a and 10b via transfer gates 51a and 51b, respectively, and cache data line pairs 31a and 31b are connected to transfer gates 52a and 52b, respectively.
b are connected to the bit line pair 11a and 11b. Each of the transfer gates 51a, 51b, 52a, 52b is formed by an nMOS transistor connected between each bit line and the cache data line.
The gates of these transistors are connected to a transfer control signal line 50.
It is connected to the.

The transfer control circuit 4 includes an nMOS transistor 41, a pMOS transistor 42, and inverters 43 and 4.
4, 45 and 46. As shown, the transfer control circuit 4 applies a signal of a predetermined level to the transfer control signal line 50 and the cache drive signal lines 40a and 40b in response to external control signals 47 and 48. For example, when receiving a high-level control signal 48 from the outside, the transfer control circuit 4 applies a high-level transfer control signal to the transfer control signal line 50. In response, transfer gates 51a, 51b, 52a, 52b are kept on, and each bit line pair 10a, 10b and 11a, 11b
Read data of the cache data line pair 30a, 30
b and 31a and 31b, respectively.

Further, the transfer control circuit 4 responds to a control signal 47 from the outside to control the cache drive signal lines 40a and 40a.
0b is controlled. For example, when a high-level control signal 47 is received from the outside, both the nMOS transistor 41 and the pMOS transistor 42 are held in the ON state in the control circuit 4, so that the cache drive signal line 40a is connected to the ground potential GND and the cache drive signal. The signal lines 40b are each held at the power supply voltage V _DD level. In response, cache memory cells 32 and 34 are maintained in an operating state (activated state), and data of cache signal line pairs 30a, 30b and 31a and 31b are retained by cache memory cells 32 and 34.

When a low-level control signal 47 is received from the outside, both the nMOS transistor 41 and the pMOS transistor 42 are held in the off state in the transfer control circuit 4, so that the cache drive signal line 40
Both a and 40b are held in a floating state.
At this time, cache memory cells 32 and 34 are kept in an inactive state.

FIG. 4 is a waveform chart showing the operation of the semiconductor memory device of this embodiment. It should be noted that FIG. 9 shows the level change of each signal line when data read to the bit line pair 10a, 10b is transferred to the cache data line via the transfer gate at the time of reading and is held by the cache memory cell 32. Is shown. As shown, first, the word line 20 is switched from the low level to the high level "H", and in response to this, the memory cell 12 of the bit line pair 10a, 10b is
The level of the bit line 10a connected to a is set. For this reason, a slight potential difference occurs between the bit lines 10a and 10b. This potential difference is detected by the sense amplifier 22 connected to the bit line pair 10a, 10b.
Since the signals are amplified, the levels of the bit line pairs 10a and 10b are respectively determined.

After the level of the bit line pair 10a, 10b is determined, the control signal 47 switches from the high level to the low level as shown in the figure, and accordingly, the control signal 48 switches from the low level to the high level. The transfer gates 51a and 51b are turned on according to the change of these signals, and the level of the cache data line pair 30a and 30b is set according to the level of the bit line pair 10a and 10b. After the signal levels of the cache data line pair 30a, 30b are determined, the control signal 47 switches from a low level to a high level, and the control signal 48 switches from a high level to a low level. In response to this, the transfer gates 51a, 51
1b is kept off, and the cache data line pair 30
a, 30b are disconnected from the bit line pair 10a, 10b. At this time, the cache drive signal line 40a is set to the ground potential GND and the cache drive signal line 40b is set to the power supply voltage V _DD level by the transfer control circuit 4, so that the cache memory cell 32 is operating and the cache data line The level of the pair 30a, 30b is held.

As described above, the signal of the bit line pair is transferred to the cache data line pair, and the read data is temporarily held by the cache memory cell. By providing the cache memory, the speed of memory access can be increased.

[0013]

The conventional semiconductor memory device described above has a layout in which the sense amplifier array 2 is arranged on one side of the memory cell array 1. Due to the recent miniaturization of the process, the layout of the sense amplifier is physically impossible at the same pitch as the pitch at which the bit line pairs are arranged.

As an example of solving this problem, a method of arranging sense amplifiers on both sides of the memory cell array 1 as shown in FIG. 5 has been devised. As shown in FIG. 5, sense amplifiers and cache memory cells are arranged on both sides of the memory cell array 1, respectively. For example, as shown
A sense amplifier 2a and a cache memory cell 3a are arranged on the left side of the memory cell array 1, and conversely, a sense amplifier 2b and a cache memory cell 3b are arranged on the right side of the memory cell array 1.

Transfer gates 51a, 51b between bit line pairs 10a, 10b and cache data line pairs 30a, 30b
Are controlled by a transfer control signal line 50a, and a bit line pair 11a, 11b and a cache data line pair 31a, 31b
The transfer gates 52a and 52b between the transfer control signal lines 50
b. Note that the transfer control signal lines 50a, 5
0b is controlled by the transfer control circuits 4a and 4b, respectively. The transfer control circuits 4a and 4b control the levels of the transfer control signal lines 50a and 50b according to the common external input signals 47 and 48.

FIG. 6 shows waveforms during a read operation of the semiconductor memory device of this embodiment. As shown in the figure, when this method is adopted, the data read by activating the word line 20 is amplified by the sense amplifiers 2a and 2b. Further, by activating the transfer control signal lines 50a and 50b by the transfer control circuits 4a and 4b, the data amplified by the sense amplifiers 2a and 2b is transferred to the cache memory cells 3a and 3b.

However, in the semiconductor memory device shown in FIG.
There are the following disadvantages. For example, if it is necessary to rewrite data only in the cache memory cell 3, in the conventional method, data transfer of the cache memory is executed in both the cache memory cells 3a and 3b. Therefore, it is necessary to perform the transfer operation again only on the cache memory cell 3b which does not need to transfer data, and to rewrite the original data. The problem here is that access to the DRAM is basically prohibited during data transfer of the cache memory, so that access to the DRAM by re-transfer of data in the cache memory becomes impossible.

The present invention has been made in view of the above circumstances, and has as its object to control the division of a cache memory cell so that only the necessary data is transferred, so that DRAM access by unnecessary data transfer is performed. It is an object of the present invention to provide a semiconductor memory device capable of improving the memory access speed by eliminating restrictions on the semiconductor memory device.

[0019]

In order to achieve the above object, a semiconductor memory device according to the present invention comprises a plurality of memory cells connected to each intersection of a plurality of word lines and a plurality of bit lines arranged in a matrix. A memory cell array arranged in a
At least two data holding means, which are arranged on both sides of the memory cell array and temporarily hold data stored in the memory cells in the memory cell array, and independently control the at least two data holding means, respectively. Control means for holding the data stored in the memory cell in any of the at least two data holding means.

Further, the semiconductor memory device of the present invention comprises a memory cell array in which memory cells connected to respective intersections of a plurality of word lines and a plurality of bit lines arranged in a cross are arranged in a matrix. A plurality of cache data lines arranged for each bit line; a plurality of cache memory cells provided for each of the cache data lines; and a plurality of cache memory cells connected between each of the bit lines and each of the cache data lines. And a transfer control circuit that controls each transfer gate independently and controls the on / off state of each transfer gate.

In the present invention, preferably, the plurality of transfer control gates and cache memory cells are alternately arranged on both sides of the memory cell array, and at the time of data reading, the transfer control circuit determines the level of a selected bit line. After that, the transfer gate is set to the on state, the cache memory cell is kept in the inactive state, and after the signal level of the cache data line is determined, the transfer gate is set to the off state, and the cache is set to the off state. The memory cell is held in an activated state, and the signal level of the cache data line is held.

Further, in the present invention, preferably, the transfer control circuit includes a first control circuit for controlling an on / off state of a transfer gate between an odd-numbered bit line and a cache data line, and an even-numbered bit line. And a second control circuit for controlling the on / off state of the transfer gate between the line and the cache data line, wherein the transfer control circuit controls the first and second control in response to a selection control signal from outside. Arbitrarily set the circuit to the operating state.

According to the present invention, the on / off state of each transfer gate is independently controlled by the transfer control circuit,
For example, only the transfer gates between the odd-numbered bit lines and the cache data lines are set to the ON state, and the other transfer gates are kept in the OFF state, so that the transfer of the bit lines and the cache data lines that require data transfer is performed. Only during that time, data transfer is not performed between the other bit lines and the cache data lines, and only a predetermined cache memory cell can be rewritten.

As a result, the data transfer of the cache memory cells can be controlled independently of each other and can be executed only for the necessary data transfer.
A reduction in the access speed to M can be avoided. Further, the present invention is an effective method for further improving the memory access speed in a system in which a plurality of unit memory circuits operate in parallel.

[0025]

FIG. 1 is a circuit diagram showing one embodiment of a semiconductor memory device according to the present invention. As shown in the figure, the semiconductor memory device of the present embodiment includes a memory cell array 1, sense amplifiers 2a and 2b, and cache memory cells 3a and 3
b and transfer control circuits 4a and 4b.

In an actual semiconductor memory device, a memory cell array is formed by arranging a plurality of memory cells connected to an intersection with a plurality of word lines and bit line pairs arranged in a matrix. I have. In FIG. 1, for convenience of explanation, two word lines 2 are used.
0, 21 and two pairs of bit lines 10a, 10b, 11
a, 11b, and four memory cells 12a, 1b connected to the intersections of these word lines and bit line pairs.
2b, 14a and 14b are shown as examples. Each memory cell forming the memory cell array 1 is, for example, a general DRAM memory cell including one transistor and one capacitor.

The sense amplifier 2a includes a bit line pair 10a,
10b. At the time of reading, a potential difference occurs between the bit lines 10a and 10b according to the storage data of the selected memory cell. The sense amplifier 2a amplifies the minute potential difference to determine the potentials of the bit lines 10a and 10b. Similarly, sense amplifier 2b includes bit line pair 11a,
11b. At the time of reading, a potential difference occurs between the bit lines 11a and 11b according to the storage data of the selected memory cell. The sense amplifier 2b amplifies the minute potential difference to determine the potential of the bit lines 11a and 11b.

As shown, the cache memory cell 3a includes pMOS transistors 301 and 303 and nMOS transistors 302 and 304. Although the cache memory cell of this example has substantially the same configuration as the memory cell of the SRAM, the present invention is not limited to this, and it is possible to temporarily store the signal level of the cache data line pair. May be used. As shown, the transistors forming the cache memory cell constitute a flip-flop. The cache drive signal line 53a has a low level, for example, a ground potential GND, and the cache drive signal line 54a has a high level, for example, a power supply voltage V.
_When the signal of the _DD level is applied, the cache 3a is set to the active state, and the signal level of the cache data line pair 30a, 30b can be determined and held. Cache memory cell 3b connected to cache data line pair 31a, 31b has the same configuration as cache memory cell 3a.

The cache drive signal lines 53a, 54a to which the cache memory cell 3a is connected are controlled by the transfer control circuit 4a, and similarly, the cache drive signal lines 53b, 5 to which the cache memory cell 3b is connected.
4b is controlled by the transfer control circuit 4b.

The cache data line 30a and the bit line 10
The transfer gate 51a is connected between a, and the transfer gate 51b is connected between the cache data line 30b and the bit line 10b. Similarly, a transfer gate 52a is connected between the cache data line 31a and the bit line 11a, and a transfer gate 52 is connected between the cache data line 31b and the bit line 11b.
b is connected.

As shown, the transfer gates 51a, 51
b, 52a, and 52b are formed by nMOS transistors connected between the respective bit lines and the cache data lines. The transfer gates 51a, 51
The gate of the transistor forming 1b is connected to the transfer control signal line 50a, and the gate of the transistor forming the transfer gates 52a and 52b is connected to the transfer control signal line 50b. The transfer control signal lines 50a and 50b are controlled by transfer control circuits 4a and 4b, respectively.

The transfer control circuit 4a comprises an nMOS transistor 41a, a pMOS transistor 42a, a NOR gate 43c, a NAND gate 45c and an inverter 40
c, 44c and 46c. As shown, the transfer control circuit 4a receives control signals 47 and 48 from outside.
And a transfer control signal line 50 in accordance with the selection control signal 49a.
a and a signal of a predetermined level is applied to the cache drive signal lines 53a and 54a.

Similarly, the transfer control circuit 4b includes an nMOS transistor 41b, a pMOS transistor 42b,
It comprises an R gate 43d, a NAND gate 45d and inverters 40d, 44d, 46d. The transfer control circuit 4b applies a signal of a predetermined level to the transfer control signal line 50b and the cache drive signal lines 53b and 54b according to external control signals 47 and 48 and a selection control signal 49b.

Each of the selection control signals 49a and 49b is set to an arbitrary level. By the selection control signals 49a and 49b set in this way, any transfer gates on both sides of the memory cell array 1 are set to the ON state, and the corresponding cache memory cells are set to the inactive state.

In the transfer control circuit 4a, one input terminal of the NOR gate 43c is connected to the output terminal of the inverter 40c, and the other input terminal is connected to the input terminal of the selection control signal 49a. The output terminal of the NOR gate 43c is connected to the gate of the pMOS transistor 42a,
Further, it is connected to the input terminal of the inverter 44c.
The output terminal of the inverter 44c is the nMOS transistor 4
1a is connected to the gate. The pMOS transistor 42a is connected to the cache drive signal line 54a and the power supply voltage V _DD
Of the nMOS transistors 41a
Are connected between the cache drive signal line 53a and the ground potential GND.

One input terminal of the NAND gate 45c is connected to the input terminal of the control signal 48, and the other input terminal is connected to the input terminal of the selection control signal 49a. NA
The output terminal of the ND gate 45c is connected to the input terminal of the inverter 46c, and the output terminal of the inverter 46c is connected to the transfer control signal line 50a.

The transfer control circuit 4 configured as described above
In a, when the selection control signal 49a is held at a low level, the output terminal of the NOR gate 43c is held at a low level, and the output terminal of the 45c is held at a high level, so that the transistors 42a and 43a are turned on. You. In response, cache drive signal line 53a is held at ground potential GND, and 53b is held at power supply voltage _VDD level.
Further, since the transfer control signal line 50a is held at the low level, both the transfer gates 51a and 51b are held in the off state. That is, when the selection control signal 49a is set to the low level, the transfer control circuit 4a holds the transfer gates 51a and 51b in the off state, and holds the cache memory cell 3a in the activated state.

On the other hand, when the selection control signal 49a is held at the high level, the transfer control circuit 4a outputs the control signal
The states of transfer gates 51a, 51b and cache memory cell 3a are controlled in accordance with the levels of 7, 48. For example, when the control signal 47 is at a low level, the NOR gate 4
The output terminal 3c is held at a high level. in this case,
Transistors 41a and 42a are both turned off, cache drive signal lines 53a and 54a are both held in a floating state, and cache memory cell 3a
Are set to the inactive state. Conversely, when the control signal 47 is held at the high level, the output terminal of the NOR gate 43c is held at the low level, and the transistors 41a,
42a are both set to the ON state, the cache drive signal line 53a is connected to the ground potential GND, and the cache drive signal line 5
4a is set to the power supply voltage V _DD level, respectively. That is, in this case, the cache memory cell 3a is set to the operation state.

When the control signal 48 is held at the high level, the output terminal of the NAND gate 45c is held at the low level, and the output terminal of the inverter 46c is held at the high level. That is, the transfer control signal line 50a is held at the high level. In response to this, the transfer gates 51a, 51
b are both kept on, and the bit line pair 10a, 1
The signal of 0b is transferred to the cache data line pair 30a, 30b.

On the other hand, when the control signal 48 is held at the low level, the output terminal of the NAND gate 45c is held at the high level, and the output terminal of the inverter 46c is held at the low level. That is, the transfer control signal line 50a is kept at a low level. In response to this, the transfer gate 51
a and 51b are both kept off, and bit line pair 1
No signal transfer between 0a, 10b and the cache data line pair 30a, 30b is performed.

The transfer control circuit 4b has substantially the same structure as the transfer control circuit 4a, and responds to the selection control signal 49b and the control signals 47 and 48 to transfer the cache memory cell 3b.
b and the level of the transfer control signal line 50b are controlled. When the selection control signal 49b is held at a low level, the cache memory cell 3b is held in an activated state, and the transfer control signal line 50b is held at a low level, so that the transfer gates 52a and 52b are turned off. Is set to

When the selection control signal 49b is held at the high level, the transfer control circuit 4b changes the operating state of the cache memory cell 3b and the on / off state of the transfer gates 52a and 52b in response to the control signals 47 and 48. Control. For example, when the control signal 47 is at a low level, both the cache drive signal lines 53b and 54b are held in a floating state, and the cache memory cell 3b is set to an inactive state. Conversely, when the control signal 47 is at the high level, the cache drive signal line 53b is connected to the ground potential GND,
Since cache drive signal lines 54b are each held at the power supply voltage V _DD level, the cache memory cells are set to the operating state.

When the control signal 48 is at the low level, the transfer control signal line 50b is held at the low level, and the transfer gate 5
2a and 52b are both set to the off state. Conversely, when the control signal 48 is at the high level, the transfer control signal line 50b is held at the high level, and both the transfer gates 52a and 52b are set to the ON state.

FIG. 2 is a waveform diagram showing the operation of the semiconductor memory device of the present embodiment at the time of reading and rewriting the cache. Hereinafter, the operation of the present embodiment will be described with reference to FIGS.

As shown, first, the word line 20 is switched from low level "L" to high level "H". Accordingly, the level of bit line 10b connected to memory cell 12a in bit line pair 10a, 10b is set. Further, the sense amplifier 2a connected to the bit line pair 10a, 10b causes the bit line pair 10a, 1
The level of 0b is determined.

After the level of the bit line pair 10a, 10b is determined, the control signal 47 switches from the high level to the low level as shown in the figure, and accordingly, the control signal 48 switches from the low level to the high level. As shown, the selection control signal 49a is at a high level and the selection control signal 4
Since 9b is held at the low level, the transfer control circuit 4a is set to the active state and the control circuit 4b is set to the inactive state, as described above. That is,
The transfer control circuit 4a sets the transfer control signal line 50a to a high level in response to the level change of the control signals 47 and 48, thereby turning on the transfer gate and setting the bit line pair 1
0a and 10b are transmitted to the cache data line pair 30a and 3
0b. Further, transfer control circuit 4a sets cache drive signal lines 53a and 54a at a predetermined level to set cache memory cell 3a to an activated state, and sets cache data line pairs 30a and 30a.
The signal level of b is held.

On the other hand, since the selection control signal 49b is held at a low level, the transfer control circuit 4b does not perform the above operation, the transfer control signal line 50b is held at a low level, and the transfer gates 52a and 52b are turned off. The state is maintained as it is, and the cache memory cell 3b is maintained in the activated state.

Hereinafter, the signal transfer operation based on the control of the transfer control circuit 4a will be described with reference to FIG. As shown, according to the level change of the control signals 47 and 48,
The transfer gates 51a and 51b are switched on by the transfer control circuit 4a. As a result, the bit line pair 10
a, 10b in accordance with the level of the cache data line pair 30.
The levels of a and 30b are set. After the signal levels of the cache data line pair 30a, 30b are determined, the control signal 47 switches from a low level to a high level, and the control signal 48 switches from a high level to a low level. In response, transfer gates 51a and 51b are kept off, and cache data line pair 30a and 30b are disconnected from bit line pair 10a and 10b.

Further, since the cache drive signal line 53a is set to the ground potential GND and the cache drive signal line 54a is set to the power supply voltage V _DD level by the transfer control circuit 4a, the cache memory cell 3a is in the operating state.
The level of the cache data line pair 30a, 30b is held.

As described above, according to the present embodiment, the sense amplifiers 2a and 2a are provided on both sides of the memory cell array 1.
b and cache cells 3a and 3b are alternately arranged, sense amplifiers are arranged for each bit line pair, cache memory cells are arranged for each cache data line, and each cache data line pair is connected to a bit line via a transfer gate. Connect to pair. The transfer control circuits 4a and 4b output the selection control signal 49
The data transfer between the bit line pair and the cache data line pair is independently controlled in accordance with a and 49b and control signals 47 and 48, and only the cache memory cell on the data transfer side is set to the inactive state. Therefore, it is possible to selectively execute data transfer from a predetermined selected memory cell to a predetermined cache memory cell, perform only necessary data transfer, and avoid a decrease in DRAM access speed due to unnecessary data transfer. Can be.

The operation example described above is based on the selection control signal 4
When 9a is at a high level and 49b is at a low level, the read data detected and amplified by the sense amplifier 2a is transferred to the cache 3a and held there. Conversely, when the selection control signal 49a is at a low level and 49b Is set to the high level, it is needless to say that the read data detected and amplified by the sense amplifier 2b can be transferred to the cache memory cell 3b in the same procedure as the transfer operation described above. In the circuit example shown in FIG. 1, the transfer control circuits 4a and 4b each control the transfer operation between one bit line pair and the cache data line pair, but the present invention is not limited to this. This is more effective in a system in which a plurality of circuits operate in parallel.

[0052]

As described above, according to the semiconductor memory device of the present invention, since only the necessary data is transferred by dividing and controlling the cache memory cells, the DRAM access by unnecessary data transfer can be performed. There is an advantage that the limitation of the above can be eliminated and the memory access speed can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a waveform chart showing an operation of the semiconductor memory device of the present invention.

FIG. 3 is a circuit diagram showing an example of a conventional semiconductor memory device.

FIG. 4 is a waveform chart showing an operation of the semiconductor memory device of FIG. 3;

FIG. 5 is a circuit diagram showing another configuration example of a conventional semiconductor memory device.

FIG. 6 is a waveform chart showing an operation of the semiconductor memory device of FIG. 5;

[Explanation of symbols]

1 ... memory cell array, 2 ... sense amplifier array, 3 ...
Cache memory cell array, 2a, 2b, 22, 24
... sense amplifiers, 3a, 3b, 32, 34 ... cache memory cells, 4, 4a, 4b ... transfer control circuits, 10a,
10b, 11a, 11b... Bit lines, 30a, 30b,
31a, 31b ... cache data lines, 12a, 12
b, 14a, 14b DRAM memory cells, 20, 21
... word lines, 47, 48 ... control signals, 49a, 49b ...
Selection control signal, 50, 50a, 50b ... transfer control signal line, 40a, 40b, 53a, 54a, 53b, 54b
... Cache drive signal lines, 51a, 51b, 52a, 5
2b: transfer gate, _VDD : power supply voltage, GND: ground potential.

Claims (10)

[Claims] 1. A memory cell array in which memory cells connected to respective intersections of a plurality of word lines and a plurality of bit lines arranged in an intersecting manner are arranged in a matrix, and arranged on both sides of the memory cell array. At least two data holding means for temporarily holding the storage data of the memory cells in the memory cell array, and independently controlling the at least two data holding means, and storing the storage data of the memory cells in the memory cell array in the at least two A semiconductor storage device having control means for holding the data in any of the data holding means. 2. The semiconductor memory device according to claim 1, further comprising a plurality of sense amplifiers arranged for each of said bit lines, amplifying the potential of each bit line and outputting data according to the potential. 3. The semiconductor memory device according to claim 2, further comprising a transfer gate between each of said sense amplifiers and said data holding means, the on / off state being controlled by said control means. 4. The semiconductor memory device according to claim 3, wherein said control means selects said transfer gate, and sets only the selected transfer gate to an ON state. 5. A memory cell array in which memory cells connected to intersections of a plurality of word lines and a plurality of bit lines intersected are arranged in a matrix, and arranged for each of the bit lines. A plurality of cache data lines; a plurality of cache memory cells provided for each of the cache data lines; a plurality of transfer gates connected between each of the bit lines and each of the cache data lines; A transfer control circuit that controls gates independently of each other and controls an on / off state of each transfer gate. 6. The semiconductor memory device according to claim 5, wherein said plurality of transfer control gates and cache memory cells are alternately arranged on both sides of said memory cell array. 7. When data is read, the transfer control circuit sets the transfer gate to an on state after the level of a selected bit line is determined, holds the cache memory cell in an inactive state, and 6. The semiconductor memory device according to claim 5, wherein, after the signal level of the line is determined, the transfer gate is set to an off state, the cache memory cell is held in an activated state, and the signal level of the cache data line is held. 8. The semiconductor memory device according to claim 7, wherein said transfer control circuit activates or deactivates said cache memory cell in response to an external control signal. 9. A transfer control circuit comprising: a first control circuit for controlling an on / off state of a transfer gate between an odd-numbered bit line and a cache data line; 6. The semiconductor memory device according to claim 5, further comprising a second control circuit for controlling an on / off state of the transfer gate. 10. The transfer control circuit sets one of the first and second control circuits to an active state and sets the other to an inactive state in response to an external selection control signal. 10. The semiconductor memory device according to claim 9, wherein: