JPH11111842A - Multilayered wiring structure and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayered wiring structure which can prevent contact failure from occurring at a connection interface between a lower wiring layer of Cu as a major component and an Al-embedded plug formed by an Al selective CVD process, and a method for manufacturing the structure. SOLUTION: A Ti film 2, a TiN film 3, a Cu film 4, a TiN film 5, and an adhesive thin-film layer 20 of an Al alloy film 21 and a TiN film 22 are patterned, to form a Cu wiring pattern 23 as a lower wiring layer of Cu as its major component. An inter-layer insulating film 7 is laminated, a contact hole 8 is made in the insulating film 7, and an opening 24 is made in the TiN film 22 of the adhesive thin-film structure 20 at the bottom of the hole 8 for exposing the Al alloy film 21 of the film structure 20. The structure is subjected to a plasma cleaning process and then to an Al selective CVD process to form an Al plug 9, and then an Al alloy wiring pattern is formed on the laminate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring structure and a method of manufacturing the same, and more particularly, to a lower wiring mainly composed of Cu wiring and a selection C of Al in a semiconductor device.
The present invention relates to a multilayer wiring structure having an Al buried plug formed by a VD method and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, with the demand for higher speed and higher integration of semiconductor devices, development of a fine processing technology, a multilayer wiring technology using a low resistivity wiring material, a technology for forming an interlayer insulating film having a low dielectric constant, and the like have been developed. It is being actively performed. In a high-speed, highly integrated semiconductor device, the diameter of a connection hole (contact hole) in an interlayer insulating film that connects between a component of the semiconductor device and a wiring or between a lower wiring and an upper wiring becomes increasingly fine. The ratio between the hole depth and the hole diameter, the so-called aspect ratio, has been increasing.

Conventionally, as a wiring formed in a contact hole having a high aspect ratio, a tungsten plug formed by using a blanket W film formed by CVD, a tungsten plug formed by selective CVD of W, and a high temperature reflow method of Al. There are wiring to contact holes, etc. However, the above-described wiring forming method has a problem that it is difficult to use an interlayer insulating film of a low dielectric constant material having a high forming temperature and low heat resistance. As a method of forming a wiring to a contact hole, that is, a buried plug when using an interlayer insulating film of a low dielectric constant material having low heat resistance, there is a selective CVD method of Al. According to the Al selective CVD method, an Al embedded plug (Al plug) can be formed at about 210 ° C.
It can be applied to an interlayer insulating film with low heat resistance.

Conventionally, an Al film or an Al alloy film has been used as a low resistivity wiring material. However, if Al or an Al alloy wiring is used in a highly integrated semiconductor device, the wiring due to electromigration and stress migration problems will occur. Problems have arisen in the reliability of the Al film, making it difficult to use an Al film or an Al alloy film. In order to solve the above-described problems, technical development of copper wiring using copper (Cu) as a wiring material has been actively performed in recent years. This Cu
Has a resistivity of about 1.4 μΩ · cm, which is about half of the resistivity of Al of about 2.9 μΩ · cm. The electromigration and stress migration resistance of the Cu wiring is considerably higher than that of the Al wiring film. It is promising as a wiring material for high-speed, highly integrated semiconductor devices.

[0005] In order to manufacture the above-described high-speed and highly integrated semiconductor device, a wiring capable of coping with a contact hole formed in an interlayer insulating film having low heat resistance and a high resistance to electromigration and stress migration are provided. As a conventional example of a multilayer wiring structure having a lateral wiring with low resistivity and a method of manufacturing the same, an example of a multilayer wiring structure having a lower wiring mainly composed of Cu and an Al plug formed by a selective CVD method of Al and an example of a method of manufacturing the same are described. This will be described with reference to FIG. First, as shown in FIG. 3A, a semiconductor substrate (not shown) on which a MOS transistor or the like as a constituent element of a semiconductor device is formed has a CVD as an insulating film.
After the SiO ₂ film 1 is formed, a contact hole (not shown) for connecting the component and the wiring and a wiring formed in this contact hole, a so-called buried plug (not shown) are formed, and then a lower layer mainly composed of Cu is formed. Conductor film for forming wiring, for example, using a sputtering method,
Thin Ti film 2 and TiN film 3, Cu serving as the main component of lower wiring
A film 4 and a thin TiN film 5 are deposited. Where the thin T
The i film 2 and the TiN film 3 are composed of a Cu film
The thin TiN film 5 on the top is a film for improving adhesion of the film and a barrier film serving as a diffusion prevention film. The thin TiN film 5 on the upper part prevents the Cu film 4 from being oxidized by diffusion of oxygen atoms from the outside and increasing the resistance. , A so-called barrier film.

Next, using photolithography technology,
The above-described conductor film TiN film 5 / Cu film 4 / TiN film 3
/ Ti film 2 is patterned to form a lower wiring mainly composed of Cu, so-called Cu wiring 6.

Next, as shown in FIG. 3B, an interlayer insulating film 7 having a low dielectric constant is deposited, and thereafter, the interlayer insulating film 7 is patterned by using a photolithography technique so that the Cu wiring 6 and the upper layer are formed. Contact hole 8 for connecting with wiring
To form Thereafter, the removal of the photoresist or the like used as a mask at the time of forming the contact hole, which becomes an obstacle to the formation of the Al plug 9 by the later-described selective CVD of Al, and the subsequent passage of time, the surface of the TiN film 5 exposed at the bottom of the contact hole 8 The formed oxide film and the organic reaction product film at the time of forming the contact hole 8 adhered to the side wall surface of the contact hole 8 and causing the Al plug formed in the contact hole 8 to be granulated are treated with a BCl ₃ gas. By plasma cleaning in a gas atmosphere containing

[0008] Next, as shown in FIG.
(Dimethyl-aluminum Hybrid
e: using (CH ₃ ) ₂ AlH) gas and H ₂ gas,
Using an Al selective CVD method, an Al film is selectively deposited only in the contact hole 8 to form an Al plug 9. Thereafter, a conductor to be an upper layer wiring is deposited, and the conductor is patterned, and the upper layer wiring, for example, contains a small amount of Si or Si and Cu or the like having a large processing dimension and no risk of electromigration or the like. Al film, so-called A
The Al alloy wiring 10 is formed by the 1 alloy film.

Although not shown in the drawings, in the case of a multi-layer wiring structure having three or more wiring layers, the above-described Al alloy wiring 10 is replaced with, for example, a Cu wiring formed of the same conductive film as the above-described Cu wiring 6. The Cu wiring is used as the upper wiring, that is, the lower wiring of the third wiring, and the steps from the formation of the lower wiring to the formation of the Al plug are repeated as described above to form a multilayer wiring. An Al alloy wiring is formed by an Al alloy film having a large processing dimension of the wiring and no risk of occurrence of electromigration or the like.

However, the above-described multilayer wiring structure and the method of manufacturing the same have a problem that contact failure between the Cu wiring 6 and the Al plug frequently occurs. According to the analysis result of the contact failure of the wiring, it has been found that the contact failure occurrence location is the boundary surface where the Cu wiring 6 as the lower layer wiring and the Al plug 9 are connected.

[0011]

According to the above-described conventional multilayer wiring structure and the method of manufacturing the same, the lower wiring having Cu as a main component and the contact hole connecting the lower wiring and the upper wiring are formed with Al. There is a problem that a contact failure occurs at the interface with the Al buried plug by the selective CVD method. The present invention has been made in view of the above circumstances, and an object of the present invention is to prevent a contact failure occurring at a boundary surface between a lower wiring mainly composed of Cu and an Al buried plug formed by a selective CVD method of Al. It is an object of the present invention to provide a multi-layer wiring structure and a method of manufacturing the same.

[0012]

SUMMARY OF THE INVENTION A multilayer wiring structure and a method of manufacturing the same according to the present invention are proposed to solve the above-mentioned problems, and a multilayer wiring structure according to the present invention comprises a lower wiring mainly composed of Cu. And Al formed by selective CVD of Al
In a multilayer wiring structure having an embedded plug, a lower wiring mainly composed of Cu is constituted by a lower barrier film, a Cu film, an upper barrier film, and an adhesive thin film of a conductor.

The method of manufacturing a multilayer wiring structure according to the present invention is a method of manufacturing a multilayer wiring structure having a lower wiring mainly composed of Cu and an Al buried plug formed by selective CVD of Al. Lower barrier film, Cu
Depositing a film, an upper barrier film and an adhesion thin film of a conductor,
Forming a conductive film serving as a lower wiring mainly composed of Cu, forming a lower wiring by patterning the conductive film, depositing an interlayer insulating film, and patterning the interlayer insulating film; Forming a connection hole for connecting the lower layer wiring and the upper layer wiring, a plasma cleaning process for cleaning the surface of the conductive film at the bottom of the connection hole and the side wall of the connection hole;
forming a buried plug.

According to the present invention, since the lower layer wiring mainly composed of Cu is composed of the lower layer barrier film, the Cu film, the upper layer barrier film and the adhesion thin film of the conductor, the lower layer wiring and the selection C of Al can be selected.
Adhesion at the boundary surface where the Al plug is connected to the Al plug by the VD method can be improved, and contact failure between the lower wiring and the Al plug can be prevented. The function of the adhesion thin film on the upper part of the lower wiring is Al
It is inferred that, at the initial stage of the formation of the Al-embedded plug by the selective CVD method, the adhesion at the interface where the lower wiring and the Al-embedded plug are connected is improved in order to contribute to uniform selective growth of Al within the connection interface. You. Therefore, a highly reliable, high-speed, highly integrated semiconductor device can be manufactured.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the present invention will be described with reference to the accompanying drawings. The same components as those in FIG. 3 referred to in the description of the prior art are denoted by the same reference numerals.

Embodiment 1 In this embodiment, a lower wiring mainly composed of Cu,
This is an example in which the present invention is applied to a multilayer wiring structure having an Al embedded plug formed by the selective CVD method and a method of manufacturing the same, which will be described with reference to FIG. First, FIG.
As shown in (a), M as a constituent element of a semiconductor device
An insulating film, for example, a CVD SiO ₂ film 1 is formed on a semiconductor substrate (not shown) on which an OS transistor and the like are formed.
Then, after forming a contact hole (not shown) for connecting the component element and the wiring and a wiring formed in this contact hole, for example, a buried plug (not shown), a conductor film constituting a lower wiring mainly composed of Cu Is deposited.

The conductor film is, for example, a sputtering method, a Ti film 2 having a thickness of about 20 nm as a lower barrier film and a TiN film 3 having a thickness of about 20 nm, and a film serving as a main part of the lower wiring. Cu film 4 about 400 nm thick
And TiN having a thickness of about 30 nm as an upper barrier film.
The adhesion thin film 20 is formed by depositing the film 5 and an adhesion thin film, for example, an Al film containing a small amount of Si or Cu having a thickness of about 50 nm, a so-called Al alloy film 21 and a TiN film 22 having a thickness of about 20 nm. It is a conductor film. Here, the Ti film 2 and the TiN film 3 are a film for improving the adhesion of the Cu film 4 which is a main component of the lower wiring and a lower barrier film which is a diffusion preventing film.
The iN film 5 becomes a Cu film 4 by diffusion of oxygen atoms from the outside.
Is a diffusion prevention film for preventing the resistance from increasing due to oxidation, that is, a so-called upper layer barrier film. The TiN film 22 constituting the adhesion thin film 20 is a film for preventing the Al alloy film 21 from being oxidized. . The thickness d of the adhesive thin film 20 is such that when the interlayer insulating film 7 is etched to form the contact hole 8, the adhesive thin film 20 remains at the bottom of the contact hole 8.
When the thickness is not less than the thickness at which the effect of the adhesion thin film 20 is produced, and is not more than the thickness at which the height of the Cu wiring 23 described later is increased and adversely affects the fine processing, 20 nm ≦ d ≦ 100 n
m is desirable.

Next, using a patterned photoresist (not shown) as a mask, a helicon wave etching apparatus is used to form the above-mentioned conductor film constituting the lower wiring, ie, TiN film 22 / Al alloy film 21 / TiN film 5 / Cu film 4
The / TiN film 3 / Ti film 2 is etched to form a wiring mainly composed of Cu, a so-called Cu wiring 23. The etching conditions when the Cu wiring 23 is formed by the helicon wave etching apparatus are, for example, as follows. [Etching conditions when forming Cu wiring 23] Cl ₂ gas flow rate: 5 sccm Pressure: 0.05 Pa Source power: 1.5 kW RF bias power: 300 W Stage temperature: 250 ° C.

Next, as shown in FIG.
A film thickness of about 600 nm formed by an interlayer insulating film using an organic material such as a SiOF film or a polyimide film formed by mixing a fluorine gas into a reaction gas when an oxide film is formed by a VD method.
An interlayer insulating film 7 having a low dielectric constant is deposited. Thereafter, the interlayer insulating film 7 is patterned by photolithography to form a contact hole 8 for connecting the Cu wiring 23 to an Al alloy wiring 10 described later. Only the TiN film 22 constituting the thin film 20 is etched to form an opening 24 in the TiN film 22. The opening 24 of the TiN film 22 is formed by removing the photoresist used at the time of forming the contact hole 8 after forming the contact hole 8, and then removing the TiN film 22 using the interlayer insulating film 7 with the contact hole 8 formed as a mask. An etching method may be employed. According to this method, Ti is formed at the bottom of the contact hole 8.
Since the photoresist at the time of forming the contact hole 8 is removed in the presence of the N film 22, oxidation of the surface of the Al alloy film 21 in the photoresist removal step can be prevented.

Next, the removal of the photoresist or the like used as a mask at the time of forming the contact hole, which is an obstacle to the formation of the Al plug 9 using the Al selective CVD method described later, The oxide film formed on the exposed surface of the Al alloy film 21 and the contact hole 8 attached to the side wall surface of the contact hole 8 causing the Al plug formed in the contact hole 8 to be granulated.
The organic reaction product film at the time of formation is removed by a plasma cleaning process. The plasma cleaning conditions are, for example, as follows. [Plasma cleaning treatment conditions] BCl ₃ gas flow rate: 300 sccm Pressure: 13.3 Pa RF power: 200 W (13.56 M)
Hz) Temperature: 20 ° C

Next, as shown in FIG. 1C, a selective CVD method of Al, for example, DMAH (Dimethyl-alu) is used.
Minum hydride: (CH ₃ ) ₂ AlH) Using a selective CVD method of Al using H ₂ gas and H ₂ gas,
An Al plug 9 is formed by using a CVD method for selectively depositing an Al film only in the contact hole 8. In addition,
The conditions for forming the Al plug 9 by the above-described Al selective CVD method are, for example, that a DMAH gas is introduced into a reaction chamber of a CVD apparatus using H ₂ gas as a carrier gas, the total pressure in the reaction chamber is 266 Pa, and the amount of the Pressure 1
The pressure of the substrate to be processed is set to 204 ° C. at 3.3 Pa. The Al plug 9 may be an Al film containing a small amount of Si or Cu, so-called Al alloy film. A described above
In the initial stage of the formation of the Al plug 9 by the selective CVD method, the Al is selectively grown on the Al alloy film 21 constituting the adhesion thin film 20 above the Cu wiring 23 at the bottom of the contact hole 8, so that the uniformity is formed within the connection boundary surface. It is inferred that Al selective growth occurs, and the adhesion between the Cu wiring 23 and the Al plug 9 is improved.

Next, a conductive film serving as an upper layer wiring, for example, an Al film containing a small amount of Si or Si and Cu, that is, a so-called Al alloy film, which has a large processing dimension of the wiring and has no risk of electromigration or the like, is formed. The Al alloy film is deposited, and the Al alloy film is patterned to form an Al alloy wiring 10.

Although not shown in the drawings, in the case of a multi-layer wiring structure having three or more wiring layers, the above-described upper wiring, which is the Al alloy wiring 10, is made of, for example, the same conductive film as the above-described Cu wiring 23. This Cu wiring is used as the upper wiring, that is, the lower wiring of the third wiring, and the steps from the formation of the lower wiring to the formation of the Al plug are repeated as described above to form a multilayer wiring. The uppermost layer wiring, for example, an Al alloy wiring made of an Al alloy film having a large processing dimension of the wiring and having no risk of electromigration or the like is formed.

According to the above-described multilayer wiring structure and the method of manufacturing the same, the Cu wiring
3 is TiN film 22 / Al alloy film 21 / TiN film 5 / Cu
After removing the TiN film 22 constituting the adhesion thin film 20 in the contact hole 8 by exposing the Al alloy film 21 by the film 4 / TiN film 3 / Ti film 2, a plasma cleaning process is performed. In order to form the Al plug 9 by the selective CVD method of Al for connecting the Cu wiring 23 and the Al alloy wiring 10 as the upper layer wiring, the adhesion at the boundary surface between the Cu wiring 23 and the Al plug 9 is reduced. And the occurrence of contact failure can be prevented.

Embodiment 2 In this embodiment, a lower wiring mainly composed of Cu,
This is an example in which the present invention is applied to a multilayer wiring structure having an Al buried plug formed by the selective CVD method and a method of manufacturing the same, in which the adhesion thin film in Embodiment 1 is an amorphous silicon thin film. Will be described with reference to FIG. First, as shown in FIG. 2A, as in the first embodiment, on the CVD SiO ₂ film 1, a conductor film constituting a lower layer wiring mainly composed of Cu is deposited. The conductor film of the present embodiment is formed by, for example, a sputtering method and has a thickness of about 20 nm as a lower barrier film.
an i film 2 and a TiN film 3 having a thickness of about 20 nm; and a Cu film 4 having a thickness of about 400 nm, which is a main component of the lower wiring.
And TiN having a thickness of about 30 nm as an upper barrier film.
This is a conductor film formed by depositing a film 5 and an adhesive thin film, for example, an amorphous silicon thin film (a-Si thin film) 30 having a thickness of about 20 nm deposited by a plasma CVD method. In addition,
The a-Si thin film 30 may be an impurity-doped a-Si thin film 30 formed by mixing a gas serving as an impurity such as PH ₃ gas into a reaction gas when the a-Si thin film 30 is formed. . Further, instead of the a-Si thin film 30 by the plasma CVD method, an amorphous silicon film by a sputtering method, which can be deposited at a lower temperature, may be used.

Next, using a patterned photoresist (not shown) as a mask, under the same etching conditions as in the first embodiment using a helicon wave etching apparatus, the above-mentioned conductor film constituting the lower wiring, ie, a -S
i thin film 30 / TiN film 5 / Cu film 4 / TiN film 3 / Ti
The film 2 is etched to form a lower layer wiring mainly composed of Cu, a so-called Cu wiring 31.

Next, as shown in FIG.
A film thickness of about 600 nm formed by an interlayer insulating film using an organic material such as a SiOF film or a polyimide film formed by mixing a fluorine gas into a reaction gas when an oxide film is formed by a VD method.
An interlayer insulating film 7 having a low dielectric constant is deposited. Thereafter, the interlayer insulating film 7 is patterned by using a photolithography technique, and a contact hole 8 for connecting the Cu wiring 31 and an Al alloy wiring 10 described later is formed.

Next, the removal of the photoresist or the like used as a mask at the time of forming the contact hole, which is an obstacle to the formation of the Al plug 9 by using the Al selective CVD method described later, A-S exposed
The oxide film formed on the surface of the i-thin film 30 and the Al plug formed in the contact hole 8 may be granulated.
The organic reaction product film adhering to the side wall surface of the contact hole 8 when the contact hole 8 is formed is removed by plasma cleaning processing under the same plasma cleaning processing conditions as in the first embodiment.

Next, as shown in FIG. 2C, a selective CVD method of Al, for example, DMAH (Dimethyl-alu) is used.
Minum hydride: (CH ₃ ) ₂ AlH) Using a selective CVD method of Al using H ₂ gas and H ₂ gas,
An Al plug 9 is formed by using a CVD method for selectively depositing an Al film only in the contact hole 8. This A
The conditions for forming the 1 plug 9 are, for example, the same as in the first embodiment. The Al plug 9 may be an Al film containing a small amount of Si or Cu, so-called Al alloy film.
In the initial stage of the formation of the Al plug 9 by the above-described Al selective CVD method, the Cu wiring 3 at the bottom of the contact hole 8 is formed.
(1) Since Al is selectively grown on the a-Si thin film 30, which is an adhesion thin film on the upper portion, it is inferred that uniform Al selective growth occurs in the connection boundary surface, and the adhesion between the Cu wiring 31 and the Al plug 9 is improved. .

Next, a conductor film serving as an upper layer wiring, for example, an Al film containing a small amount of Si or Si and Cu, that is, a so-called Al alloy film, which has a large processing dimension of the wiring and does not cause the occurrence of electromigration or the like, is used. The Al alloy film is deposited, and the Al alloy film is patterned to form an Al alloy wiring 10.

Although not shown in the drawings, in the case of a multi-layer wiring structure having three or more wiring layers, the above-mentioned upper wiring, which is the Al alloy wiring 10, is made of, for example, a conductor film similar to the above-described Cu wiring 31. This Cu wiring is used as the upper wiring, that is, the lower wiring of the third wiring, and the steps from the formation of the lower wiring to the formation of the Al plug are repeated as described above to form a multilayer wiring. The uppermost layer wiring, for example, an Al alloy wiring made of an Al alloy film having a large processing dimension of the wiring and having no risk of electromigration or the like is formed.

According to the above-described multilayer wiring structure and the method of manufacturing the same, the Cu wiring
1 is a-Si thin film 30 / TiN film 5 / Cu film 4 / TiN
Composed of film 3 / Ti film 2 and C
The a-Si thin film 30 of the u wiring 31 is exposed, a plasma cleaning process is performed, and then the Al plug 9 for selectively connecting the Cu wiring 31 and the Al alloy wiring 10 as an upper layer wiring is formed by the Al selective CVD method. Cu to form
It is possible to prevent the occurrence of contact failure at the interface between the wiring 31 and the Al plug 9.

Although the present invention has been described with reference to the two embodiments, the present invention is not limited to these embodiments. For example, in the embodiment of the present invention, a film in which the adhesion thin film is composed of an Al alloy film and a TiN film,
Alternatively, a high melting point metal such as W or Mo or a high melting point metal silicide film such as WSi ₂ or MoSi ₂ may be used. In the embodiment of the present invention, the reaction gas used for the selective CVD method of Al is DMAH.
Although the gas and the H ₂ gas have been described, triisobutylaluminum, trimethylaminealane, dimethylaminealane, or the like may be used instead of the DMAH gas. Further, in the embodiment of the present invention, the interlayer insulating film is made of SiOF.
Although described as a low dielectric constant interlayer insulating film such as a film or a polyimide film, a BPSG (B
oro-Phospho Silicate Glass
Obviously, an interlayer insulating film based on the dielectric constant of a normal SiO ₂ film such as s) and a CVD SiO ₂ film may be used. In addition, within the scope of the technical concept of the present invention, the process apparatus and process conditions can be appropriately changed.

[0034]

As is apparent from the above description, the multilayer wiring structure and the method of manufacturing the same according to the present invention are capable of forming a Cu wiring, which is a lower wiring mainly composed of Cu, by using a lower barrier film, a Cu film, an upper barrier film and a conductive film. A contact hole connecting the lower layer wiring and the upper layer wiring, a so-called buried plug, is formed of an Al plug formed by an Al selective CVD method, thereby forming an interface between the Cu wiring and the Al plug. Can be prevented from occurring. Therefore, a highly reliable, high-speed, highly integrated semiconductor device can be manufactured.

[Brief description of the drawings]

FIGS. 1A and 1B are schematic cross-sectional views of a multilayer wiring structure for explaining steps of a first embodiment of the present invention in the order of steps. FIG. 1A is a diagram showing a CVD SiO ₂ film, and the uppermost layers are an Al alloy film and a TiN film. A state in which a Cu wiring, which is a lower layer wiring mainly composed of Cu, is formed as an adhesion thin film composed of: (b) a contact hole is formed in an interlayer insulating film, and then an adhesion thin film at the bottom of the contact hole is formed. (C) shows a state in which an Al plug is formed by a selective CVD method of Al and then an Al alloy wiring as an upper layer wiring is formed.

[2] The present invention will be described the applied example of the embodiment 2 steps in the order of steps, in schematic cross-sectional view of a multilayer wiring structure, (a) shows the on CVD SiO ₂ film, the adhesion uppermost by a-Si film C, which is a lower layer wiring mainly composed of Cu, which is a thin film
(b) is a state in which a contact hole is formed in an interlayer insulating film, (c) is an Al plug formed by selective CVD of Al, and then Al is an upper layer wiring.
This is a state in which an alloy wiring is formed.

FIGS. 3A and 3B are schematic cross-sectional views of a multilayer wiring structure for explaining steps of a conventional method of manufacturing a multilayer wiring structure in the order of steps. FIG. 3A shows a Cu wiring which is a lower wiring mainly composed of Cu on a CVD SiO ₂ film. Is formed, (b) is a state in which a contact hole is formed in the interlayer insulating film, and (c) is a selective CVD of Al.
An Al plug is formed by a method, and then A
This is a state in which 1 alloy wiring is formed.

[Explanation of symbols]

1 ... CVD SiO ₂ film, 2 ... Ti film, 3,5,22 ... T
iN film, 4 ... Cu film, 6, 23, 31 ... Cu wiring, 7 ...
Interlayer insulating film, 8 contact hole, 9 Al plug,
10 ... Al alloy wiring, 20 ... adhesion thin film, 21 ... Al alloy film, 24 ... opening, 30 ... a-Si thin film

Claims (11)

[Claims] In a multilayer wiring structure having a lower wiring mainly composed of Cu and an Al buried plug formed by a selective CVD method of Al, an adhesive thin film of a lower barrier film, a Cu film, an upper barrier film and a conductor is provided. And a lower layer wiring mainly composed of Cu. 2. The multilayer wiring structure according to claim 1, wherein the lower barrier film is one of a TiN film and a film composed of a Ti film and a TiN film. 3. The multilayer wiring structure according to claim 1, wherein said upper layer barrier film is a TiN film. 4. The thin film comprising an Al film and a TiN film on the Al film, a thin film comprising an Al alloy film and a TiN film on the Al alloy film, and an amorphous silicon thin film. 2. The multilayer wiring structure according to claim 1, wherein the multilayer wiring structure is any one of the films. 5. The film thickness d of the adhesion thin film is 20 nm ≦ d
The multilayer wiring structure according to claim 1, wherein ≤ 100 nm. 6. A method for manufacturing a multilayer wiring structure having a lower wiring mainly composed of Cu and an Al buried plug formed by selective CVD of Al, wherein a lower barrier film, a Cu film and an upper barrier film are formed on an insulating film. Depositing an adhesive thin film of a conductor and a conductor to form a conductor film serving as a lower wiring mainly composed of Cu; patterning the conductor film to form a lower wiring; depositing an interlayer insulating film Patterning the interlayer insulating film to form a connection hole connecting the lower wiring and the upper wiring, and cleaning the conductive film surface and the connection hole side wall at the bottom of the connection hole. A method of manufacturing a multilayer wiring structure, comprising: a plasma cleaning step; and a step of forming an Al buried plug in the connection hole by an Al selective CVD method. . 7. The method according to claim 6, wherein the lower barrier film is one of a TiN film and a film composed of a Ti film and a TiN film. . 8. The method according to claim 6, wherein the upper barrier film is a TiN film. 9. The thin film composed of an Al film and a TiN film on the Al film, a thin film composed of an Al alloy film and a TiN film on the Al alloy film, and an amorphous silicon thin film. 7. The method according to claim 6, wherein the film is any one of the films. 10. The thin film comprising an Al film and a TiN film on the Al film, or a thin film comprising an Al alloy film and a TiN film on the Al alloy film. 10. The method according to claim 9, wherein, after forming the connection hole in the interlayer insulating film, removing the TiN film at the bottom of the connection hole. 11. The film thickness d of the adhesion thin film is 20 nm ≦
7. The method according to claim 6, wherein d ≦ 100 nm.