JPH1098111A - Mos semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability by forming various insulation films between overlapped parts of source and drain diffused regions formed in gate electrodes and semiconductor substrate. SOLUTION: A thermally oxidized film 105 is formed on gate electrodes 104 of MOS transistors and source and drain diffusion regions 102. An insulating film 106 is buried in overlapped parts of the gate electrodes 104 and source and drain diffusion regions 102. By CVD method a nitride insulation film 106 is deposited. To completly fill up voids, the low pressure CVD, providing a high coverage is effective. For the insulating film 106, a nitride film having a wide selective ratio relative to a lower thermally oxide film is advantageous in stability and reduction of the process for a later dry etching, compared with an oxide film. This greatly improves the TDDB characteristic caused between the electrodes 104 and diffusion regions 102 and hance markedly improves the CDM resistances.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a high breakdown voltage MOS type semiconductor device and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 3 is a sectional view of a conventional MOS type semiconductor device in the order of manufacturing steps. In FIG. 3A, after a gate electrode 104 is formed on a gate insulating film 103 on a semiconductor substrate 101, the gate insulating film 1 on the portions to be the source and drain diffusions 102 and 102 and below the end of the gate electrode 104
03 shows a state in which wet etching is performed. In order to guarantee the reliability of the semiconductor device, it is necessary to set the thickness of the gate insulating film 103 usually formed of a silicon thermal oxide film to a thickness of about 3 MV / cm.
Electrode 104 and semiconductor substrate 1 in a semiconductor device
When a voltage of 30 V is applied during 01, an oxide film thickness of 1000 ° is required. In that case, it is difficult to sufficiently introduce impurities into the semiconductor substrate due to the limitation of implantation energy when impurities are introduced using a high current ion implantation apparatus at the time of forming the source and drain later. Therefore, after the gate electrode is formed, it is necessary to etch the gate insulating film on the portion where the source diffusion and drain diffusion will be performed later by wet etching. However, since the wet etching is isotropic, the gate insulating film below the end of the gate electrode 104 is etched. The film 103 is also etched.

[0003] Next, as shown in FIG. 3 (b), an oxide film 105 is formed on the semiconductor substrate 101 and the surface of the gate electrode 104 by a thermal oxidation method, and impurities are introduced by using a high current ion implantation apparatus to perform source diffusion. 102, drain diffusion 102
To form If the oxide film thickness at this time is set to about 200 °, the impurity is sufficiently introduced. Thereafter, as shown in FIG. 3C, an intermediate insulating film 107 is formed by a CVD method.

[0004]

In the MOS type semiconductor device manufactured by the above-mentioned conventional manufacturing method, the gate electrode 104, the source diffusion 102, and the drain diffusion 10
A gap is formed in a portion overlapping with No. 2, causing a significant decrease in reliability.

[0005]

In order to solve the above-mentioned problems, the present invention uses the following means. (1) An insulating film between a gate electrode and an overlapping portion of a source diffusion and a drain diffusion formed in a semiconductor substrate is formed of a plurality of types of insulating films.
OS type semiconductor device. (2) A MOS type semiconductor device wherein an insulating film between a gate electrode and a semiconductor substrate is a silicon oxide film and has a thickness of 500 ° or more. (3) A MOS semiconductor device, wherein at least one of the insulating films between the gate electrode and the overlapping portion between the source diffusion and the drain diffusion is a silicon oxide film, and at least one is a silicon nitride film. (4) At least one type of insulating film between the gate electrode and the overlapped portion between the source diffusion and the drain diffusion is a silicon thermal oxide film, and at least one type is a silicon oxide film formed by a CVD method. apparatus. (5) forming a gate insulating film on the semiconductor substrate;
A step of forming a gate electrode on the gate insulating film, a step of wet etching the gate insulating film, a step of forming an oxide film on the semiconductor substrate and the surface of the gate electrode by a thermal oxidation method, and a step of forming an oxide film by a CVD method. Attaching step;
A method for manufacturing a MOS semiconductor device, comprising: a step of etching an insulating film by a dry etching method; and a step of introducing an impurity into a semiconductor substrate. (6) A method for manufacturing a MOS type semiconductor device, characterized in that the insulating film to be deposited by the CVD method is an oxide film or a nitride film having a thickness in the range of 300 to 1000 °.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic sectional view showing one embodiment of a semiconductor device according to the manufacturing method of the present invention. A source diffusion and a drain diffusion 102 of a conductivity type opposite to that of the substrate 101 are formed in the semiconductor substrate 101, and a MOS transistor including a gate electrode 104 and a gate insulating film 103 is formed.

In FIG. 1, a gate electrode 104 of a MOS transistor and source and drain diffusions 102 are shown.
A thermal oxide film 105 is formed thereon, and an insulating film 106 is buried in an overlapping portion between the gate electrode 104 and the source and drain diffusions 102. With such a structure, a TDDB (Time Dependent Die electric Br) generated between the gate electrode 104 and the source diffusion or the drain diffusion 102 as compared with a conventional structure having a gap.
eakdown) The characteristics are dramatically improved. In addition, ESD (Ele
CDM, a method for evaluating ctro Static Discharge)
(Device charging method) A remarkable improvement was also observed in the resistance. In the present structure, the breakdown at 750 V was 30
No destruction was observed even at 00V.

FIG. 2 is a sectional view showing the manufacturing method of the present invention in the order of steps. 2A, after a gate electrode 104 is formed on a gate insulating film 103 on a semiconductor substrate 101, a source diffusion and a drain diffusion 10 are formed later by wet etching.
2 shows a state in which the gate insulating film 103 above the portion to be 2 and under the end of the gate electrode 104 is removed by etching. For example, when the power supply voltage is a 30 V MOS type semiconductor device, the thickness of the gate insulating film 103 usually formed of a silicon thermal oxide film is set to about 3 MV / cm in order to guarantee the reliability of the semiconductor device. In this case, wet etching is performed using hydrofluoric acid so as to prevent the gate insulating film 103 from remaining on the semiconductor substrate 101. Since the wet etching is isotropic, an undercut of about 0.1 μm occurs under the gate electrode 104. Next, as shown in FIG. 2B, a thermal oxide film 105 having a thickness of about 200 ° is formed on the semiconductor substrate 101 and the gate electrode surface by a thermal oxidation method, and further, a film thickness of 300 °
A 0 ° oxide or nitride insulating film 106 is deposited. Here, the distance between the gate electrode 104 and the semiconductor substrate 101 is 1000 °, and even if a thermal oxide film 105 of about 200 ° is grown, the gap below the end of the gate electrode 104 is not eliminated. At this time, it is conceivable to increase the thickness of the oxide film 105 so as to eliminate the voids. Cannot be eliminated. Next, when depositing the insulating film 106 of a nitride film by the CVD method, it is necessary to completely fill the voids.
It is more effective to use the VD method. Further, the insulating film 106
However, when dry etching is performed later than an oxide film, a nitride film having a selectivity with respect to an underlying thermal oxide film is more advantageous in terms of stabilization and reduction of steps. When an oxide film is used, an etch stop is performed when the semiconductor substrate is exposed, so that an additional thermal oxidation step is required.

Thereafter, as shown in FIG. 2C, when etching is performed by a dry etching method, since the etching has directionality, the end of the gate electrode 104 and the semiconductor substrate 101 are etched.
It is possible to selectively leave only the insulating film 106 of the nitride film sandwiched between the layers. Thereafter, source diffusion and drain diffusion 102 are formed by ion implantation, and an intermediate insulating film 107 is formed by CVD. FIG. 4 shows a second embodiment of the semiconductor device according to the present invention. On the gate electrode 104 of the MOS transistor, an insulating layer in which a thermal oxide film 105 is formed above and below a silicon nitride film 110 is formed, and polysilicon 111 is formed thereon to form a capacitor. The thickness of the thermal oxide film 105 under the silicon nitride film 110 is about 300 ° to 700 °, and the thickness of the silicon nitride film 110 is about 200 ° to 1 °.
000 °, and the thickness of the thermal oxide film 105 on the silicon nitride film 110 is about 10 ° to 100 °. With such a structure, a highly reliable semiconductor device which does not break down even when a high voltage is applied between the gate electrode 104 and the polysilicon 111 can be manufactured.

FIG. 5 shows the gate electrode 104 and the polysilicon 1
It shows the current value between the electrodes when a voltage is applied to the electrodes of 11 tubes. The horizontal axis of the graph represents voltage, and the vertical axis represents current. It can be seen that the leak current of the conventional product rapidly increases from around 10 V and breaks at 22 V, whereas the product of the present invention has almost no leak current and a high breakdown voltage up to around 30 V. . Also, polysilicon 1
11 has a smaller area than the gate electrode 104. Where the polysilicon 111 straddles the gate electrode 104, the electric field is concentrated, so that the breakdown voltage is reduced. Further, since the relative dielectric constant of Si3N4 is 7.5, which is larger than the relative dielectric constant of the silicon oxide film of 3.9, the capacity can be increased by using Si3N4. That is, the area can be reduced.

FIG. 6 shows a second embodiment of the manufacturing method according to the present invention. In a process A shown in FIG. 6A, after a silicon nitride film (Si3N4) is patterned in a region where a MOS transistor is to be formed on the semiconductor substrate 101, thermal oxidation is performed to form a field oxide film 109. Next, the gate oxide film 103 is formed by removing the silicon nitride film. The thickness of the gate oxide film 103 was set to about 900 °.

In a step B shown in FIG.
Polysilicon is deposited from 00 to 4000 degrees, and heat treatment (predeposition) is performed to implant high-concentration phosphorus into the polysilicon. After that, the gate electrode 1 is etched.
04 to the gate oxide film 103 and the field oxide film 109
Form on top. The sheet resistance of the gate electrode 104 is 30
Ω / □. Next, an oxide film on the source / drain regions 102, 102 formed in a later step is removed by wet etching, and then a thermal oxidation process is performed to grow a silicon oxide film 105 (BottomOx.) On the entire surface of the substrate. Next, a silicon nitride film 110 is deposited on the silicon oxide film 105 by a CVD method. At this time, the gap under the edge of the gate electrode 104 formed by wet etching is completely filled. Thereafter, thermal oxidation is performed at 900 ° C. in an oxygen atmosphere to form oxide film 105 (TopOx.).
Grow. The product of the present invention formed an oxide film of about 12 °. BottomOx. Thickness is about 300 to 70
0 °, the thickness of the Si 3 N 4 is set to be about 200 ° to 1000 °. However, BottomOx. It is preferable that the film thickness of Si3N4 be determined by the required breakdown electric field. FIG. 7 shows Ox. Indicates Ratio. The vertical axis of the graph indicates the breakdown electric field, and the horizontal axis indicates Ox. Ratio
(= BottomOx.film thickness / (BottomOx.film thickness + Si3N4 film thickness)). The product of the present invention is Bo
tttomOx. About 600Å, and 500Ｎ for Si3N4
About. Next, after depositing polysilicon 111,
Impurities (phosphorus, arsenic or BF2) are ion-implanted into the polysilicon to make the polysilicon a required resistance. The thickness of the polysilicon is as thin as about 300 ° to 2000 °. The product of the present invention used 1000 °. By reducing the film thickness, the deviation of the resistance value can be reduced (FIG. 8).

In a step C shown in FIG. 6C, a mask is patterned on a portion on the gate electrode 104 on the field insulating film 109 and on a resistance forming portion on the field oxide film 109. Then, the polysilicon 111 and the oxide film 105 are formed.
(TopOx.) And the silicon nitride film 110 are simultaneously etched. At this time, the polysilicon 111 on the gate electrode 104 is made smaller than the area of the gate electrode 104. This is because the electric field concentrates where the polysilicon 111 straddles the gate electrode 104, so that the breakdown voltage is reduced. Next, the part of the resistor 112 formed earlier is replaced with photoresist 1
Then, impurities are introduced into the semiconductor substrate by using a high-current ion implantation apparatus, and at the same time, impurities are introduced into the polysilicon 111 to form a conductive band. The sheet resistance of the polysilicon of the present invention was about 130Ω / □. In a step D shown in FIG. 6D, the photoresist is removed, a high-temperature heat treatment is performed, and the implanted impurities are activated and diffused to form a MOS transistor-114. As described above, the insulating film is formed between the gate electrode and the overlapped portion of the source diffusion and the drain diffusion formed in the semiconductor substrate, and at the same time, the capacitor 11 is formed by one film formation, thermal oxidation and ion implantation.
5 and the resistor 112 can be formed. The capacitance element 115 is a highly reliable device that can withstand a high voltage.

A third embodiment of the semiconductor device according to the present invention will be described in detail. FIG. 9 shows P-channel and Nc
FIG. 2 is an inverter circuit composed of a channel MOS transistor and an oscillation circuit composed of a capacitance element and a resistance element of the present invention. FIG. 10A is a plan view showing the structure of the capacitance and the resistance, and FIG. 10B is a schematic symbol. The capacitance element and the resistance element have a configuration as shown in FIG. Thermal oxidation treatment is performed on the first conductive band 1, e.g., a polysilicon having a thickness of 2500 to 5000 mm, which has been reduced in resistance by pre-deposition, to grow a silicon oxide film on the polysilicon. The first conductive band may use a gate electrode of a MOS transistor. In the present invention, the polysilicon is 300
0 ° and the thickness of the silicon oxide film were set to about 500 °. Next, a silicon nitride film having a thickness of about 200 to 900 is deposited on the silicon oxide film by the CVD method. In the present invention, 2
It was about 00Å. Thereafter, thermal oxidation is performed at 900 ° C. in an oxygen atmosphere to grow an oxide film on the silicon nitride film. The product of the present invention formed an oxide film of about 20 °. Next, a second conductive band 3, for example, polysilicon is deposited. Thereafter, an impurity (phosphorus, arsenic or BF2) is ion-implanted into the semiconductor substrate to form a diffusion layer (source / drain) of the MOS transistor. Reduce the resistance of the belt. In the present invention, for example, 3 to 5E15 / cm 2 for phosphorus and 5 to 7E15 / cm 2 for arsenic.
In the case of BF2, ions were implanted at a concentration of 3 to 5E15 / cm2. Phosphorus and arsenic may be mixed and implanted.
The resistance element is formed by the second conductive band, and the resistance value is adjusted by the length of the second conductive band. The resistance value increases as the length increases. The thickness of this polysilicon is the same as the polysilicon of the first conductive band 1, or approximately 300 to 2,000. The product of the present invention used 2000 mm. Finally, the photoresist is patterned and the polysilicon is etched to make the polysilicon of the second conductive band the required length. In this way, a capacitor element including the first conductive band, the insulating layer and the second conductive band, and a resistance element including the second conductive band can be formed in the same area with a small area without increasing the number of steps. be able to. FIG. 10b) is a schematic symbol of the capacitance and the resistance, and the capacitance is connected to the resistance as shown in FIG.
It forms part of an oscillation circuit. Ox. Rati
o is 0.7, and BreakDownFie from FIG.
Since ld is 8 MV / cm, the structure does not break even when a voltage of 15 V or more is applied.

FIG. 11 shows a third embodiment of the manufacturing method according to the present invention. In step A, a thermal oxide film 105 is formed on the semiconductor substrate 101, and an impurity having the same polarity as the substrate is ion-implanted. 1 to 8E14 / cm2 of the phosphorus or arsenic of the present invention
Injected. This ion implantation may not be performed depending on the circuit. In step B, the thermal oxide film 105 is removed to form a gate oxide film 103. Gate oxide film thickness is 90
It was about 0 °.

In step C, the film thickness is from 3000 to 400
A polysilicon of 0 ° is deposited, and a heat treatment (pre-deposition) is performed to add a high concentration of phosphorus to the polysilicon. Thereafter, etching is performed to form a gate electrode 104 on the gate oxide film 103. The sheet resistance of the gate electrode is 30
Ω / □. Next, a thermal oxidation treatment is applied to the gate electrode 1.
A silicon oxide film (BottomOx.) Is grown on the substrate 04.

In step D, a silicon nitride film 110 is deposited on the bottom oxide film by a CVD method. Thereafter, thermal oxidation is performed at 900 ° C. in an oxygen atmosphere to form an oxide film (T
opOx. Grow). The product of the present invention formed an oxide film of about 100 °. BottomOx. The film thickness is about 30
0 ° to 700 °, Si3N4 film thickness from about 200 ° to 8
Set to 00. However, BottomOx. And Si3N4
Is preferably determined by the required breakdown electric field.
FIG. 7 shows Ox. Indicates Ratio. The vertical axis of the graph indicates the breakdown electric field, and the horizontal axis indicates Ox. R
atio (= BottomOx.film thickness / (Bottom
Ox. Film thickness + Si3N4 film thickness)). The product of the present invention is BottomOx. About 600 ° and Si3N4 about 500 °. Next, polysilicon 111 is deposited. Polysilicon film thickness is about 300-2000mm
And thin. The product of the present invention used 1500 °.

In step E, after the patterning, the polysilicon and TopOx. And the silicon nitride film are simultaneously etched. At this time, the polysilicon 111 on the gate electrode is made smaller than the area of the gate electrode. This is because the breakdown voltage is reduced because the electric field concentrates where the polysilicon straddles the gate electrode. Next, impurities (phosphorus, arsenic, or BF2) are applied to the entire surface of the substrate using a high-current ion implantation apparatus. In the present invention, phosphorus or arsenic is implanted. The polysilicon 111 is converted into a conductive band by the impurity implantation. In step D, high-temperature heat treatment is performed to activate and diffuse the implanted impurities.

FIG. 12 is a sectional view of a fourth embodiment of the semiconductor device according to the manufacturing method of the present invention. An intermediate insulating film 107 is formed by a CVD method or the like, and is subsequently flattened by a heat treatment. Next, after a metal material is formed on the entire surface by vacuum deposition or sputtering, photolithography and etching are performed to pattern the metal 117 on the polysilicon 111. This makes it possible to form three types of capacitance elements including the metal 117 and the polysilicon 111, a capacitance element including the polysilicon 111 and the gate electrode 104, and a capacitance element including the gate electrode 104 and the semiconductor substrate 101 in the same area. Therefore, a high capacity can be formed in a small area, and the IC can be reduced in size. FIG. 13 a) is a simplified cross-sectional view of FIG. 12, and b) is a schematic view of a). By connecting the vertically overlapping capacitance elements as shown in the figure, the capacitance can be increased due to parallel connection. When there is no metal, two types of capacitance elements are used. However, the other two types of capacitance can sufficiently increase the capacitance and reduce the size of the IC. This capacity naturally constitutes a device with high withstand voltage and high reliability.

[0020]

As described above, according to the present invention, an insulator such as an oxide film or a nitride film is buried by a CVD method so that no void is formed in a portion where a gate electrode overlaps a source diffusion and a drain diffusion. By using a plurality of types of insulating films, a highly reliable MOS semiconductor device can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a first embodiment of a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view in a process order showing a manufacturing method of a first embodiment of a semiconductor device of the present invention.

FIG. 3 is a cross-sectional view in the order of steps showing a conventional method for manufacturing a semiconductor device.

FIG. 4 is a schematic sectional view of a second embodiment of the semiconductor device of the present invention.

FIG. 5 is a graph showing a relationship between a voltage of a capacitor and a leakage current.

FIG. 6 is a sectional view illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.

FIG. 7 shows an example of an Ox. 4 is a graph showing a relationship between a ratio and a breakdown voltage.

FIG. 8 is a graph showing a relationship between a polysilicon film thickness insulating film and a deviation in resistance value.

FIG. 9 is an oscillation circuit diagram.

FIG. 10 is a schematic view showing a third embodiment of the semiconductor device of the present invention.

FIG. 11 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a third embodiment of the present invention in the order of steps.

FIG. 12 is a schematic sectional view of a fourth embodiment of the semiconductor device of the present invention.

FIG. 13 is a schematic diagram of a fourth embodiment of the semiconductor device of the present invention.

[Explanation of symbols]

 Reference Signs List 101 semiconductor substrate 102 source diffusion or drain diffusion layer 103 gate insulating film 104 gate electrode 105 thermal oxide film 106 insulating film 107 intermediate insulating film 108 void 109 field oxide film 110 silicon nitride film 111 polysilicon 112 resistive element 113 photoresist 114 MOS transistor − 115 Capacitance element 116 N-type diffusion layer 117 metal

Claims (13)

[Claims] 1. An MOS type semiconductor device, wherein an insulating film between a gate electrode and an overlap portion of a source diffusion and a drain diffusion formed in a semiconductor substrate comprises a plurality of types of insulating films. 2. The MOS semiconductor device according to claim 1, wherein an insulating film between said gate electrode and said semiconductor substrate is a silicon oxide film and has a thickness of 500 ° or more. 3. The semiconductor device according to claim 1, wherein at least one of the insulating films between the gate electrode and an overlap portion between the source diffusion and the drain diffusion is a silicon oxide film, and at least one of the insulating films is a silicon nitride film. Item 1
The MOS type semiconductor device described in the above. 4. The method according to claim 1, wherein at least one of the insulating films between the gate electrode and the overlapping portion of the source diffusion and the drain diffusion is a silicon thermal oxide film, and at least one of the insulating films is a silicon oxide film formed by a CVD method. The MOS type semiconductor device according to claim 1, wherein 5. A step of forming a gate insulating film on a semiconductor substrate, a step of forming a gate electrode on the gate insulating film, a step of wet-etching the gate insulating film, and a step of thermally oxidizing the semiconductor. Forming an oxide film on a substrate and on the gate electrode surface, applying an insulating film by a CVD method, etching the insulating film by a dry etching method, and introducing impurities into the semiconductor substrate. 2. The method according to claim 1, further comprising:
The manufacturing method of the MOS type semiconductor device described in the above. 6. The MO according to claim 5, wherein said insulating film to be deposited by said CVD method is an oxide film or a nitride film having a thickness in a range of 300 ° to 1000 °.
A method for manufacturing an S-type semiconductor device. 7. The semiconductor device according to claim 1, wherein the gate electrode and the conductive band sandwich an insulating layer composed of three layers of the silicon oxide film, the silicon nitride film and the silicon oxide film. 8. A step of forming a field oxide film on a semiconductor substrate, a step of forming a gate electrode on the field oxide film, a step of forming an oxide film on the entire surface of the substrate by a thermal oxidation method, and a CVD method Depositing the silicon nitride film on the silicon nitride film, forming an oxide film on the silicon nitride film by a thermal oxidation method, depositing polysilicon on the oxide film by a CVD method, 2. The method according to claim 1, further comprising: a step of introducing the polysilicon, the step of simultaneously etching the polysilicon, the oxide film and the silicon nitride film by a dry etching method, and a step of introducing impurities to the entire surface of the substrate. 8. The method for manufacturing a semiconductor device according to item 7. 9. The semiconductor device according to claim 7, wherein said polysilicon has a smaller area than said gate electrode. 10. The semiconductor device according to claim 7, wherein said polysilicon has a thickness in a range of 300 ° to 2000 °. 11. An oscillation circuit including a capacitor, a resistor, and an inverter, wherein a capacitor formed by the gate electrode, the insulating film layer, and the polysilicon, and a resistor formed by the polysilicon. And a semiconductor device formed of 12. A semiconductor device comprising a MOS type semiconductor and a capacitor comprising a plurality of types of insulating layers. 13. A step of forming a gate insulating film on a semiconductor substrate, a step of forming a gate electrode on the gate insulating film, a step of forming an oxide film on the entire surface of the semiconductor substrate by a thermal oxidation method, and a step of CVD. Depositing a silicon nitride film on the oxide film by a method, forming an oxide film on the silicon nitride film by a thermal oxidation method,
A step of depositing polysilicon by a VD method, a step of simultaneously etching the polysilicon, the oxide film and the silicon nitride film, and a step of introducing impurities into the semiconductor substrate and the polysilicon. The method for manufacturing a semiconductor device according to claim 12, wherein