JPH1093093A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable solving problems of gate material which remains behind and the deterioration of an element characteristic by forming a pair of source/ drain regions being opposed through a gate electrode respectively, on the surface of each side surface of a semiconductor layer. SOLUTION: It becomes possible to prevent effectively a semiconductor layer 12 from being etched, if a protective insulating film 13 is provided on the whole top surface of the semiconductor layer 12, for example, even if long- time etching with an extent of not leaving a gate material behind to be a possible cause for an interwiring short-circuit in the lower part of the semiconductor layer 12 is performed, in an etching process at the forming of a gate electrode 4. Accordingly, the removal of the gate material in the lower part of the semiconductor layer is made possible, without etching the semiconductor layer 12 in the source/drain region. Further, on this occasion exposure of the upper part corner sections of the semiconductor layer is reduced, so it becomes possible to prevent the deterioration of the gate withstand voltage and the element characteristics, such as a sub-threshold characteristic.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a MOS transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, large-scale integrated circuits (LSIs) formed by integrating a large number of transistors, resistors, and the like to achieve an electric circuit are integrated in an important part of a computer or a communication device. It is heavily used. For this reason, the performance of the entire device is greatly related to the performance of the LSI alone.

[0003] The performance of an LSI alone can be improved by increasing the degree of integration, that is, by miniaturizing elements. With the increasing integration of such conductor devices and miniaturization of elements, in recent years,
It is also necessary to reduce the area of the element isolation region.

A LOCOS method (selective oxidation method) has been used as one of the element isolation methods conventionally used. However, this method has a problem that a dimensional conversion difference called a bird's beak occurs and the separation is performed in a narrow isolation width. Because the oxide film used for thinning (field thinning effect)
Not suitable for miniaturization of element isolation regions.

A typical element isolation method is a trench isolation method. In this method, usually, a groove is formed in a semiconductor layer, and an insulator is buried in the groove to realize element isolation.

In addition, SOI (Silicon On I)
If an nsulator substrate is used, the buried oxide film 82
, It is possible to perform element isolation without embedding an insulator (mesa element isolation). If these trench isolation methods are used, a conversion difference is small, and element isolation suitable for miniaturization can be realized.

FIG. 22 shows a conventional SOI substrate.
FIG. 3 shows a cross-sectional view of a MOSFET separated by a trench, which is parallel to a channel width direction. A buried oxide film 8 is formed on the support substrate 81.
2, a convex island silicon layer 83 is formed. A MOS gate structure is formed on the convex island silicon layer 83.

Here, after forming an etching mask made of an oxide film on the SOI layer,
RIE (reactive ion etching) on OI layer
Formed by anisotropic etching.

The gate insulating film 86 is formed after removing the etching mask and the etching by-product. This removal is usually performed by HF (hydrofluoric acid) wet etching. At this time, the buried oxide film 82 is also etched, so that a depression 87 is formed below the silicon layer 83, and a corner portion 85 is exposed below the silicon layer 83. Further, a corner portion 85 is also provided above the silicon layer 83.
Is exposed.

As a result, an electric field is concentrated on the gate insulating film 84 at the corner portion 85, and problems such as deterioration of the gate breakdown voltage and deterioration of the sub-threshold characteristic (parasitic transistor) occur.

Various proposals have been made to oxidize and round the corner portion 85 or to cover and cover the corner portion 85 with an insulator, but there are problems such as a complicated process. In the step of forming the gate electrode 84, the gate material remains in the depression 87. Such a residual gate material causes a short circuit between wirings when the element isolation width is reduced.

On the other hand, there is also a proposal to actively use parasitic transistors at corners and side surfaces of a convex island silicon layer (for example, K. Hieda, et al "Effects of New Trench-i").
solated Transistor Using Side wall Gates ", IEEE Tr
ans. Electron Devices, vol. 36, p. 1615, (1959)).

As shown in FIG. 23, the corner portions 99 and the side portions 98 of the island-shaped silicon layer 93 are also formed by MO.
By forming an S-gate structure and completely depleting the silicon layer 93, a transistor with a small body effect is realized as a whole.

Here, the silicon layer 93 is not formed by etching the SOI layer, but is formed by digging a trench in the silicon substrate 91. In this trench, an insulating film 9 for element isolation is used for trench isolation.
2 is embedded.

However, this type of MOSFET has the following problems. That is, when the trench is deepened to increase the size of the transistor on the side surface portion 98, the gate material 95 remains on the lower side wall of the silicon layer 93. The remaining gate material 95 causes a short circuit between wirings.

In order to prevent the gate material 95 from remaining under the silicon layer 93 by extending the etching time of the conductive film serving as the gate electrode 94, the
The gate insulating film 96 on the silicon layer 93 in the drain region may be removed, and the silicon layer 93 in the source / drain region may be etched and disappear.

Further, in order to ensure the gate breakdown voltage of the corner portion 99, it is absolutely necessary to devise a method such as oxidizing and rounding the corner portion 99, which causes problems such as a complicated process. In addition, there is a problem that an increase in dimensional conversion difference cannot be avoided by rounding.

[0018]

As described above, an M gate having a MOS gate structure formed on a side surface of a silicon layer having a convex island shape.
The OSFET has a problem that a gate material that causes a short circuit between wirings remains under a silicon layer in a process of forming a gate electrode. To solve this, there is a method of performing etching for a long time so that the gate material does not remain under the silicon layer. However, this method has a problem that the silicon layer in the source / drain region may be etched and disappear. was there.

Further, since the gate insulating film is formed at the exposed corners, the gate breakdown voltage and the sub-threshold characteristics are deteriorated, and there is a problem that the element performance is deteriorated. In order to solve this, there is a method of oxidizing and rounding the gate insulating film in the corner portion, but this has a problem that the process becomes complicated.

The present invention has been made in consideration of the above circumstances, and has as its object to solve the problem of the remaining gate material and the problem of deterioration of the device characteristics on the side surface of the semiconductor layer, which can solve the above problem. MOSF with MOS gate structure formed
An object of the present invention is to provide a semiconductor device provided with ET and a method of manufacturing the same.

[0021]

[Means for Solving the Problems]

[Summary] To achieve the above object, a semiconductor device according to the present invention (Claim 1) includes a semiconductor layer selectively formed on an insulating layer, and a covering insulating film formed on an upper surface of the semiconductor layer. A gate electrode formed so as to extend from one side surface of the semiconductor layer to the other side surface of the semiconductor layer facing the covering insulating film and the side surface; and between the gate electrode and each of the side surfaces. And a pair of source / drain regions formed on the surface of each of the side surfaces and facing each other with the gate electrode interposed therebetween.

In another semiconductor device according to the present invention (claim 2), in the semiconductor device (claim 1), the covering insulating film is below the gate electrode, and the source / drain region is It does not exist on the upper surface of the semiconductor layer in a region sandwiched between the formed side surfaces.

According to another aspect of the present invention, there is provided a semiconductor device according to the present invention, wherein the coating insulating film has a lower etching rate than the gate electrode. It is characterized by being thicker than a film, or slower in etching rate than the gate electrode and thicker than the gate insulating film.

Further, in another semiconductor device according to the present invention (claim 4), in the semiconductor device (claim 1), the side surface of the portion provided with the gate insulating film is (100).
Surface.

In another semiconductor device according to the present invention (claim 5), in the semiconductor device (claim 1), the thickness of the semiconductor layer is larger than the distance between the two opposing side surfaces. It is characterized.

According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a coating insulating film on the entire surface of a semiconductor layer whose base is an insulating layer; A step of patterning the film into a convex shape having two opposing side surfaces, a step of forming a gate insulating film on each of the side surfaces, and forming a conductive film on the entire surface, and then etching the covering insulating film by etching the semiconductor layer. Used for protective film,
Forming a gate electrode adjacent to the gate insulating film by etching the conductive film; and forming a pair of source / drain regions on each of the side surfaces facing each other via the gate electrode. It is characterized by the following.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the present invention, wherein the semiconductor layer formed on an insulating film is used as the semiconductor layer. Forming a trench in the semiconductor layer to reach the insulating film, or using a semiconductor substrate as the semiconductor layer, forming a trench in the surface of the semiconductor layer, and embedding the insulating film in the trench. Is used to perform element isolation.

In the present invention, the coating insulating film preferably has a smaller dielectric constant than the gate insulating film. [Operation] According to the present invention, for example, if a protective insulating film is provided on the entire upper surface of a semiconductor layer, it causes a short circuit between wirings under the semiconductor layer in an etching step when forming a gate electrode. Even if the etching is performed for a long time so that the gate material does not remain, the etching of the semiconductor layer can be effectively prevented. Therefore, according to the present invention, the gate material under the semiconductor layer can be removed without causing the etching of the semiconductor layer in the source / drain regions.

Also, in this case, since the exposure of the upper corner portion of the semiconductor layer is reduced, it is possible to prevent the deterioration of the gate breakdown voltage and the deterioration of the device characteristics such as the sub-threshold characteristics.

According to the present invention (claim 4), since the side surface is the (100) surface, the interface state density at the interface between the gate insulating film and the side surface can be sufficiently reduced. Also,
In the present invention, two gate electrodes are provided on two opposing side surfaces of the semiconductor layer with a gate insulating film interposed therebetween.
A sandwich structure in which a semiconductor layer is sandwiched between S gates, that is, a so-called double gate MOSFET is formed.

Therefore, as in the present invention (claim 5), if the thickness of the semiconductor layer is made larger than the distance between the two opposing side surfaces, that is, if the width of the semiconductor layer is made smaller, the semiconductor layer becomes thinner. Can be completely depleted, so that the performance of the transistor can be improved. Further, by reducing the distance between the two side surfaces, the area occupied by the transistor can be reduced.

It is often observed that the occupied area of the element region is reduced and the contact resistance between the source / drain region and the electrode connected thereto is increased by the miniaturization. Increasing the height of the layer can prevent an increase in contact resistance.

[0033]

Embodiments of the present invention (hereinafter, referred to as embodiments) will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a plan view showing a MOSFET according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view of the MOSFET of FIG.
FIG. 4 is a sectional view of the SFET taken along the line BB 'of FIG.
FIG. 3 is a cross-sectional perspective view of the CDEF region of FIG. FIG.
In the figures, 2 indicates an SOI substrate, 3 indicates an element isolation region, and 5 indicates an element region.

FIGS. 5 to 11 show the MOSFE of this embodiment.
It is sectional drawing which shows the manufacturing method of T. These figures (a) and (b) are a sectional view taken along the line AA 'and a sectional view taken along the line BB' during the manufacture of the MOSFET of FIG. 1, respectively.

First, as shown in FIG. 5, an SOI substrate including a support substrate 9, a buried oxide film 8, and a silicon layer 10 is prepared. This SOI substrate is formed by the SIMOX method. Note that the SOI substrate may be formed by a bonding method. Further, an SOI substrate having no buried oxide film such as SOS may be used.

Next, as shown in FIG. 6, a buffer oxide film 12 having a thickness of 10 nm is formed on the surface of the silicon layer 10 by thermal oxidation. At this time, if necessary, MOSFET
Is performed to adjust the threshold voltage of.

Although only one MOSFET is shown in the figure, an n-channel MOSFET such as a CMOS is used.
If the T and p-type channel MOSFETs are formed simultaneously, the ion implantation is performed by using the n-type channel MOSFET.
T and p-type channel MOSFETs are performed separately.

Thereafter, as shown in FIG. 1, a silicon nitride film 13 having a thickness of, for example, 150 nm is formed on the buffer oxide film 12 as a protective insulating film (etching mask). The protective insulating film preferably has a lower dielectric constant than a gate insulating film formed in a later step.

Next, as shown in FIG. 7, after forming a photoresist pattern 15 on the silicon nitride film 13 by patterning by EB drawing or photolithography,
Using the photoresist pattern 15 as a mask, the silicon nitride film 1 is exposed until the surface of the buried oxide film 8 is exposed.
3. The buffer oxide film 12 and the silicon layer 10 are continuously etched by RIE, and the silicon nitride film 13, the buffer oxide film 12, and the silicon layer 10 are processed into an island shape.

Basically, the element isolation step is completed with only these steps, and the number of steps is very small and easy, which is advantageous for mass production of semiconductor devices. Moreover, since the trench is separated without any conversion difference, it is suitable for miniaturization.

Next, as shown in FIG. 8, after removing the photoresist pattern 15, the silicon layer 1 is thermally oxidized.
A gate insulating film 11 having a thickness of 6 nm is formed on the side surface of the zero.
Next, as shown in FIG.
a 100 nm thick polysilicon film and a 100 nm thick tungsten silicide film (or tungsten film)
The layers are formed by a CVD method and a sputtering method.

The polysilicon film is doped with impurities by ion implantation after film formation. In the case where a metal film such as a TiN film is used instead of the polysilicon film, the ion implantation for adjusting the threshold voltage (described on the same page) is unnecessary.

In the process of FIG. 8, the silicon nitride film 1
3. Since the buffer oxide film 12 is left without being removed, a CDE (chemical dry etching) or HF-based solution for removing the silicon nitride film 13 and the buffer oxide film 12 immediately before the gate insulating film 11 is formed. No etching is performed.

Therefore, the depression 8 as shown in FIG.
7 is difficult to be formed, and the upper and lower corner portions of the edge portion of the silicon layer 10 (element region) are not exposed. Thereby, the withstand voltage of the gate insulating film 11 is improved, and a hump of the sub-threshold characteristic is suppressed.

Further, by adjusting the crystal plane orientation of silicon,
At least a part of the side surface of the island-shaped silicon layer 10 has (10
When the 0) plane is exposed, the gate insulating film 11 having a small interface state can be formed on the side surface of the silicon layer 10.

Next, as shown in FIG. 9, the polysilicon film and the tungsten silicide film (or tungsten film) are laminated by RIE using a photoresist pattern (not shown) as a mask by patterning by EB drawing or photolithography. Etch the film,
The gate electrode 4 is formed. Thereafter, the photoresist pattern is removed, and the surface of the gate electrode 4 is lightly oxidized to form a thin (about 5 nm) oxide film (not shown).

Here, a buried oxide film 8 or a silicon nitride film 13 as a protective insulating film (etching mask) exists below the above-mentioned laminated film to be the gate electrode 4. Therefore, even if the laminated film is etched for a long time so that the gate material does not remain on the lower side surface of the silicon layer 10, the silicon layer 10 in the source / drain region is not etched.

In order to further completely prevent the gate material from remaining, it is effective to give the trench angle a slight taper (7 degrees or less with respect to the vertical plane, a direction in which the width of the trench becomes narrow at a deep position). .

Next, as shown in FIG. 10, in order to form a source / drain diffusion layer, annealing is performed after ion implantation of the impurity ions 14 at an angle. Here, As is used for an n-type channel MOSFET, and BF _{2 is set} to 1 × 10 ¹⁵ / cm for a p-type channel MOSFET.
Ion implantation is performed at a dose of about ² .

Next, as shown in FIG. 11, an interlayer insulating film 7 is formed on the entire surface. Thereafter, the normal MOSFET manufacturing process is followed. That is, as shown in FIGS.
Contact holes 1 _G , 1
_{The SD} is opened, and lead wirings 16, 17, and 18 connected to the gate electrode 4 and the two source / drain diffusion layers are formed.

Even if the area occupied by the element region is reduced by miniaturization, by increasing the thickness of the silicon layer 10 (by increasing the depth of the trench groove), The parasitic resistance at the contact portion between the drain layer and the lead-out wiring 17 and the parasitic resistance at the contact portion between the other source / drain layer and the lead-out wiring 18 can be reduced, and an increase in the contact resistance can be prevented.

Note that, in FIG.
Has been omitted. Since the lead wirings 17 and 18 can make contact with the side surface of the silicon layer 10, the contact area increases.

In the present embodiment, the gate electrode 4 is formed on two opposing side surfaces of the semiconductor layer 10 via the gate insulating film 11.
Is provided, a sandwich structure in which the semiconductor layer 3 is sandwiched between two MOS gates, that is, a so-called double-gate MOSFET is formed.

Therefore, if the thickness d of the semiconductor layer 10 is made larger than the distance between the two opposing side surfaces, that is, if the width w of the semiconductor layer 10 is made smaller (for example, 40 nm).
Degree), the semiconductor layer 10 can be completely depleted, so that the performance of the transistor can be improved. Further, by reducing the distance between the two side surfaces, the area occupied by the transistor can be reduced. (Second Embodiment) The feature of the MOSFET of this embodiment is that the MOSFET of the first embodiment has
This means that the silicon nitride film 13 as a protective insulating film on the silicon layer 10 between the side surfaces where the drain diffusion layer is formed is removed.

In the MOSFET having such a structure, for example, after processing the gate in the step of FIG. 9, the silicon nitride film 13 on the silicon layer 10 between the side surfaces where the source / drain diffusion layers are formed is subjected to RIE (reactive Then, as shown in FIG. 10, ion implantation for forming source / drain diffusion layers is performed. Since there is no silicon nitride film, ions can be easily implanted into the semiconductor layer 10. Next, as shown in FIG. 11, an interlayer insulating film 7 is formed on the entire surface.
Thereafter, a normal MOSFET similar to that of the first embodiment is used.
According to the manufacturing process. (Third Embodiment) FIGS. 12 to 20 are sectional views showing a method for manufacturing a MOSFET according to a third embodiment.
The plan view is the same as that shown in FIG. 1, and each figure (a) and FIG. (B) correspond to the AA 'sectional view and the BB' sectional view of the plan view in FIG. 1, respectively.

This embodiment is an example using a normal silicon substrate instead of an SOI substrate. That is, the present embodiment is not an embodiment according to the present invention, but has the same effects as the present invention.

First, as shown in FIG. 12, a silicon substrate 21 is prepared, and then a buffer oxide film 22 having a thickness of 10 nm is formed on the surface of the silicon substrate 21 by thermal oxidation. At this time, if necessary, ion implantation for adjusting the threshold voltage of the MOSFET is performed.

Although only one MOSFET is shown in the figure, an n-type channel MOSFET such as a CMOS is used.
If the T and p-type channel MOSFETs are formed simultaneously, the ion implantation is performed by using the n-type channel MOSFET.
T and p-type channel MOSFETs are performed separately.

Thereafter, as shown in FIG. 6, a silicon nitride film 23 having a thickness of, for example, 150 nm is formed on the buffer oxide film 22 as a protective insulating film (etching mask). Next, as shown in FIG. 13, after forming a photoresist pattern 24 on the silicon nitride film 23 by patterning by EB drawing or photolithography, the silicon nitride film 2 is formed using the photoresist pattern 24 as a mask.
3. The buffer oxide film 22 and the silicon substrate 21 are continuously etched by the RIE method to form a trench having a depth of, for example, 250 nm, and the silicon nitride film 23, the buffer oxide film 22, and the silicon substrate 21 are processed into an island shape. .

Next, as shown in FIG. 14, after removing the photoresist pattern 24, an oxide film 25 having a thickness of 350 nm is formed on the entire surface. Then, as shown in FIG. 15, the silicon nitride film 23 is used as a stopper. The surface of the oxide film 25
It is polished and flattened by an MP (chemical mechanical polish) method.

Next, as shown in FIG. 16, the entire surface is etched by the RIE method under the condition that the silicon nitride film 23 is not etched and the oxide film 25 is selectively etched. Is left at the bottom of the trench groove by 125 nm.

Basically, the element isolation step ends with the above steps. Since the insulating film is buried in the trench, the conversion difference is small, which is suitable for miniaturization. Next, as shown in FIG. 17, a 6-nm-thick gate insulating film 26 is formed on the side surface of the island-shaped silicon substrate 21 by thermal oxidation, and then a 150-nm-thick polysilicon film serving as the gate electrode 27 is formed.
A 0-nm-thick tungsten silicide film (or tungsten film) is formed by lamination using the LPCVD method and the sputtering method, respectively.

After the film formation, the polysilicon film is doped with impurities by ion implantation. When a metal film such as a TiN film is used instead of the polysilicon film, the ion implantation for adjusting the threshold voltage described on the previous page is unnecessary.

In the step of FIG. 17, the silicon nitride film 2
3. Since the buffer oxide film 22 is left without being removed, a CDE (chemical dry etching) or HF-based solution for removing the silicon nitride film 23 and the buffer oxide film 22 immediately before forming the gate insulating film 26 is used. No etching is performed.

Therefore, the depression 8 as shown in FIG.
7 is difficult to be formed, and the upper corner portion of the edge portion of the island-shaped silicon substrate 21 (element region) is not exposed. As a result, the breakdown voltage of the gate insulating film 26 is improved, and a hump of the sub-threshold characteristic is suppressed.

Further, by adjusting the crystal plane orientation of silicon,
At least a part of the side surface of the island-shaped silicon substrate 21 has (1
When the (00) plane is exposed, the gate insulating film 26 with a small interface state can be formed on the side surface of the silicon substrate 21.

Next, as shown in FIG. 18, the polysilicon film and the tungsten silicide film (or tungsten film) are laminated by RIE using a photoresist pattern (not shown) as a mask by patterning by EB drawing or photolithography. The gate electrode 27 is formed by etching the film. Thereafter, the photoresist pattern is removed, and the surface of the gate electrode 27 is lightly oxidized to form a thin (about 5 nm) oxide film (not shown).

Here, an oxide film 25 or a silicon nitride film 23 as a protective insulating film (etching mask) exists under the above-mentioned laminated film to be the gate electrode 27. Therefore,
Even if the laminated film is etched for a long time so that the gate material does not remain on the lower side surface of the island-shaped silicon substrate 21,
The island-shaped silicon substrate 21 in the source / drain region is not etched.

In order to further completely prevent the gate material from remaining, it is effective to give the trench angle a slight taper (7 degrees or less with respect to the vertical plane, a direction in which the width of the trench becomes smaller at a deeper angle). .

Next, as shown in FIG.
In order to form a drain diffusion layer, annealing is performed after oblique ion implantation of impurity ions 28. here,
As for an n-channel MOSFET, BF ₂ is 1 × 10 ^{15 for} a p-channel MOSFET.
Ions are implanted at a dose of about / cm ² .

Next, as shown in FIG. 20, after an interlayer insulating film 29 is formed on the entire surface, contact holes 30 are opened in each of the gate, source and drain regions in accordance with a normal MOSFET manufacturing process. 27, extraction wirings 31 respectively connected to the two source / drain diffusion layers,
32 and 33 are formed.

Even if the occupied area of the element region is reduced by miniaturization, by increasing the thickness of the island-shaped silicon substrate 21 (trench groove) as in the case of forming the SOI substrate described above. In this case, the parasitic resistance at the contact portions between the source / drain layers and the lead wirings 32 and 33 can be reduced, and the contact resistance can be prevented from increasing. This is because a contact can be made even on the side surface of the island-shaped silicon.

In this embodiment, since the gate electrode 27 is provided on the two opposing side surfaces of the island-shaped silicon substrate 21 via the gate insulating film 26, the island-shaped silicon substrate 21 is formed by two MOS gates. , A so-called double-gate MOSFET is formed.

Therefore, if the thickness d of the island-shaped silicon substrate 21 is made larger than the distance between the two opposing side surfaces, that is, the width w of the island-shaped silicon
If the thickness is reduced to about 0 nm, the island-shaped silicon substrate 21 can be completely depleted, so that the performance of the transistor can be improved. Further, by reducing the distance between the two side surfaces, the area occupied by the transistor can be reduced.

The present invention is not limited to the embodiment described above. For example, in the case where the width of an island-shaped silicon layer or a silicon substrate (element region) is narrowed due to the progress of miniaturization, and it becomes difficult to align the source / drain contact holes, as shown in FIG. if greater than the width D2 of the source-drain element region a contact hole 1 _SD diameter D1 of, it becomes possible to prevent an increase in contact resistance due to misalignment of the contact hole 1 _SD.

In the above embodiment, the silicon nitride film is used as the protective insulating film, but another insulating film may be used. The point is that as the protective insulating film, a material having a lower etching rate than the gate electrode, a material having a thickness larger than the gate insulating film, or a material having a lower etching rate than the gate electrode and having a thickness larger than the gate insulating film is used. It is sufficient to prevent the silicon layer on the source / drain region from being etched and lost when the conductive film to be etched is etched for a long time. In addition, various modifications can be made without departing from the scope of the present invention.

[0077]

As described above in detail, according to the present invention, a MOSF in which a MOS gate structure is formed on a side surface of a semiconductor layer.
In a semiconductor device provided with ET, the problem of remaining gate material and the problem of deterioration of element characteristics can be solved.

[Brief description of the drawings]

FIG. 1 is a MOSFET according to a first embodiment of the present invention.
A plan view showing

FIG. 2 is a cross-sectional view of the MOSFET of FIG.

FIG. 3 is a cross-sectional view of the MOSFET of FIG.

4 is a sectional perspective view of a CDEF region of the MOSFET of FIG. 1;

FIG. 5 is a MOSFET according to the first embodiment of the present invention.
Cross section showing

FIG. 6 is a MOSFET according to the first embodiment of the present invention.
Cross section showing

FIG. 7 is a MOSFET according to the first embodiment of the present invention.
Cross section showing

FIG. 8 is a MOSFET according to the first embodiment of the present invention.
Cross section showing

FIG. 9 is a MOSFET according to the first embodiment of the present invention.
Cross section showing

FIG. 10 is a diagram showing a MOSFE according to the first embodiment of the present invention;
Sectional view showing T

FIG. 11 is a diagram showing a MOSFE according to the first embodiment of the present invention;
Sectional view showing T

FIG. 12 shows a MOSFE according to a third embodiment of the present invention;
Sectional drawing which shows the manufacturing method of T

FIG. 13 shows a MOSFE according to a third embodiment of the present invention;
Sectional drawing which shows the manufacturing method of T

FIG. 14 is a diagram showing a MOSFE according to a third embodiment of the present invention;
Sectional drawing which shows the manufacturing method of T

FIG. 15 shows a MOSFE according to a third embodiment of the present invention;
Sectional drawing which shows the manufacturing method of T

FIG. 16 shows a MOSFE according to a third embodiment of the present invention.
Sectional drawing which shows the manufacturing method of T

FIG. 17 shows a MOSFE according to a third embodiment of the present invention.
Sectional drawing which shows the manufacturing method of T

FIG. 18 shows a MOSFE according to a third embodiment of the present invention.
Sectional drawing which shows the manufacturing method of T

FIG. 19 is a diagram showing a MOSFE according to a third embodiment of the present invention;
Sectional drawing which shows the manufacturing method of T

FIG. 20 is a diagram showing a MOSFE according to a third embodiment of the present invention;
Sectional drawing which shows the manufacturing method of T

FIG. 21 is a plan view for explaining a method for preventing misalignment of a contact hole.

FIG. 22 is a sectional view showing a conventional MOSFET.

FIG. 23 is a sectional perspective view showing a conventional MOSFET.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 _G , 1 _SD ... Contact hole 2 ... SOI substrate 3 ... Element isolation region 4 ... Gate electrode 5 ... Element region 7 ... Interlayer insulating film 8 ... Buried oxide film 9 ... Support substrate 10 ... Silicon layer 11 ... Gate insulating film 12 ... Buffer oxide film 13 Silicon nitride film (protective insulating film) 14 Impurity ions 15 Photoresist pattern 16 Lead wiring 17 Lead wiring 18 Lead wiring 21 Silicon substrate 22 Buffer oxide film 23 Silicon nitride film (protection) 24 ... photoresist pattern 25 ... oxide film 26 ... gate insulating film 27 ... gate electrode 28 ... impurity ions 29 ... interlayer insulating film _30G , _30SD ... contact hole 31 ... lead-out wiring 32 ... lead-out wiring 33 ... lead-out wiring

Claims (7)

[Claims] A semiconductor layer formed on an insulating layer; a coating insulating film formed on an upper surface of the semiconductor layer; and a coating insulating film formed on one side of the semiconductor layer. A gate electrode formed over the other side surface of the semiconductor layer facing the gate electrode; a gate insulating film provided between the gate electrode and each of the side surfaces; and a gate electrode formed on the surface of each of the side surfaces, respectively. And a pair of source / drain regions facing each other with the gate electrode interposed therebetween. 2. The semiconductor device according to claim 1, wherein said coating insulating film is located below said gate electrode and does not exist on an upper surface of said semiconductor layer in a region sandwiched between side surfaces on which said source / drain regions are formed. 2. The semiconductor device according to 1. 3. The coating insulating film has a lower etching rate than the gate electrode, is thicker than the gate insulating film, or has a lower etching rate than the gate electrode and is thicker than the gate insulating film. The semiconductor device according to claim 1, wherein 4. The semiconductor device according to claim 1, wherein said side surface of a portion where said gate insulating film is provided is a (100) plane. 5. The semiconductor device according to claim 1, wherein a thickness of the semiconductor layer is larger than a distance between the two opposing side surfaces.
3. The semiconductor device according to claim 1. 6. A step of forming a coating insulating film over the entire surface of a semiconductor layer whose underlying layer is an insulating layer; Patterning; forming a gate insulating film on each of the side surfaces; forming a conductive film on the entire surface; and etching the conductive film using the coating insulating film as an etching protection film for the semiconductor layer. Forming a pair of source / drain regions on the respective side surfaces via the gate electrode by forming a gate electrode adjacent to the gate insulating film. Device manufacturing method. 7. The semiconductor device according to claim 7, wherein the insulating film on the semiconductor layer between the side surfaces on which the source / drain regions are formed is removed, and the insulating film is selectively left under the gate electrode. The method for manufacturing a semiconductor device according to claim 6.