JPH1093047A - Semiconductor memory device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a semiconductor memory device, capable of providing a high density structure by using switching elements having a punch-through preventive structure to form fine memory cells. SOLUTION: A p-type Si substrate 1 forms plate electrodes of MOS capacitors composed of the Si substrate 1, a capacitor insulating film 5 and storage electrodes 6. On the upper side walls of trenches 4 an element isolation insulation film 22 for separating the storage electrodes 6 from the substrate 1. These electrodes 6 buried in the trenches 4 each have a structure having a p-n junction at the top and gate electrode thereon. An n-type diffusion layer 9 functions as a flow input/output end of a diode 1 having a gate and is connected to bit lines 13 through bit line connection holes 11 of an interlayer insulating film 38. This reduces the distance between the storage electrode and electrode connected to the bit line, to thereby form fine memory cells and hence realize a semiconductor memory device capable of providing a high density structure.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device such as a DRAM and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a DRAM has one MISFE.
Memory cells combining T and one capacitor have been used. Along with the high integration of DRAM, such memory cells have the following problems due to miniaturization. Hereinafter, this problem will be described using the substrate plate type trench memory cell shown in FIG. 43 as an example. FIG.
3 (a) is a plan view of a substrate plate type trench memory cell, and FIG. 43 (b) is a sectional view taken along line AA ′ of FIG. 43 (a). Here, 1 is a semiconductor substrate, 8 is a gate electrode, 7 is a gate insulating film, 9 and 9 'are source or drain electrodes, 4 is a trench, 5 is a capacitor insulating film, 6 is a capacitor storage electrode, and 12 is an element. An isolation insulating film, 11 is a bit line contact, and 13 is a bit line. The cell transistor includes a source or drain diffusion layer 9 or 9 ′ formed on the semiconductor substrate 1 and a gate electrode 8 formed on the semiconductor substrate 1 via a gate insulating film 7. Further, the cell capacitor is constituted by the storage electrode 6 and the substrate 1 via the capacitor insulating film 5. One of the source or drain electrodes 9 of the transistor is connected to the storage electrode 6, and the other 9 ′ is connected to the bit line 13. The data transmitted through the bit line 13 is transmitted to the cell transistor T1.
Is written to the storage electrode 6 of the selected cell. Further, by turning off the transistor T1, the written data is held in the storage electrode.

However, as the distance d between the source electrode 9 and the drain electrode 9 'becomes smaller with the miniaturization of the element,
Even when the gate is turned off by applying a voltage to the gate electrode 8, a phenomenon occurs in which the current between the source electrode 9 and the drain electrode 9 'cannot be cut off due to punch-through. For this reason, the retention time of the data written to the storage electrode is shortened, and a problem that erroneous data is read occurs.

[0004] Such a phenomenon is further increased by the fact that the alignment accuracy between the patterning elements is not sufficient, and the trench 4 approaches the gate electrode 8 side or the process fluctuates. That is, the additional impurity diffuses from the storage electrode 6 in the trench 4 to the substrate 1, the diffusion length of the source or drain diffusion layer 9 increases, and the distance d between the source and drain diffusion layers decreases. As a result, the gate length is effectively shortened, and punch-through occurs.

Therefore, in order to operate the transistor stably and normally, it is necessary to secure a certain distance or more between the storage electrode 6 in ohmic contact with the source diffusion layer 9 and the drain electrode 9 '. For this reason, it has been difficult to miniaturize the memory cell.

This problem also occurs not only in the memory cell using the trench type capacitor shown here but also in the memory cell using the planar capacitor or the stack type capacitor.

[0007]

As described above, the conventional MI
In a DRAM memory cell using an S-transistor and a capacitor, the source or drain electrode 9 in resistive contact with the storage electrode 6 of the capacitor is prevented from approaching the other source or drain electrode 9 'and causing punch-through. To this end, it is necessary to ensure a distance between the storage electrode 6 and the diffusion layer 9 connected to the bit line 13, which has hindered miniaturization of the memory cell.

The present invention has been made to solve the above problems, and a first object of the present invention is to provide an electrode connected to a storage electrode and a bit line by using a switching element having a structure for preventing punch-through. To reduce the distance between
It is an object of the present invention to provide a semiconductor memory device which has a fine memory cell and can be made higher in density.

A second object of the present invention is to provide a semiconductor memory device having a circuit configuration which can be randomly accessed by a plurality of the above memory cells.

Further, a third object of the present invention is to provide a simple manufacturing method for manufacturing the above-mentioned semiconductor memory device with a small number of steps.

[0011]

SUMMARY OF THE INVENTION The feature of the present invention is that
A diode with a gate is used instead of the switch element using the IS transistor, and the capacitor storage electrode 6 is used.
By reducing the number of pn junctions or the number of Schottky junctions between the gate electrode and the drain electrode 9 'to one, a fine memory cell is formed.

That is, in the semiconductor memory device of the present invention, the first electrode region and the second electrode region separated by the rectifying junction formed on the surface of the semiconductor substrate, and the edge of the junction are located. A switch element having a gate electrode formed on a substrate surface via a gate insulating film,
The storage device includes a capacitor having a storage electrode, a capacitor insulating film, and a plate electrode, wherein a first electrode region of the switch element is connected to a storage electrode of the capacitor.

In the above-mentioned semiconductor memory device, the junction may be a pn junction or a Schottky junction.

In the above-mentioned semiconductor memory device, the storage electrode of the capacitor is embedded in a groove formed in the semiconductor substrate, the capacitor insulating film is formed on a wall surface of the groove, and the plate electrode is It is also possible that the semiconductor device is constituted by a semiconductor substrate, and an edge portion exposed on the substrate surface of the junction and at least a part of the gate electrode are formed above the groove.

Further, in the above-mentioned semiconductor memory device,
The semiconductor substrate may include an insulating layer on the surface and a semiconductor layer formed on the insulating layer, and the junction of the switch element may be formed on the semiconductor layer.

Further, according to the semiconductor memory device of the present invention, the first memory device includes a first line forming a bit line on an insulating layer formed on a semiconductor substrate.
And a rectifying junction formed in a part of a side wall surface region of a second semiconductor layer formed in a columnar shape on the first semiconductor layer so that an edge thereof is exposed on the side wall surface. Having a first electrode region and a second electrode region separated by a gate electrode and a gate electrode formed via a gate insulating film on a side wall surface of the second semiconductor layer located at an edge of the junction. An element, a storage electrode, a capacitor having a capacitor insulating film and a plate electrode, wherein a first electrode region of the switch element and a storage electrode of the capacitor are connected on an upper surface of the second semiconductor layer; A second electrode region of the switch element is connected to the first semiconductor layer.

Further, in the semiconductor memory device of the present invention, the first electrode region and the second electrode region separated by the rectifying junction formed on the surface of the semiconductor substrate, and the edges of the junction are located. A switch element having a gate electrode formed on a substrate surface with a gate insulating film interposed therebetween; and a capacitor having a storage electrode, a capacitor insulating film, and a plate electrode, and a first electrode region of the switch element. A semiconductor storage element to which a storage electrode of the capacitor is connected, and a conductive wiring to which a plurality of the semiconductor storage elements are connected via a second electrode region of the switch element; The current flowing between the first and second electrode regions is controlled by a voltage applied to the gate electrode.

Further, the semiconductor memory device of the present invention includes a first switch element having three electrodes, and a capacitor having a storage electrode and a plate electrode, wherein the first electrode of the first switch element is provided. A semiconductor storage element connected to the storage electrode; a first conductive wiring in which the plurality of semiconductor storage elements are connected via a second electrode of the switch element; and a first conductive wiring. The connected second switch element and the plurality of first conductive wires are connected to the second switch element.
A second conductive wiring connected through the switch element of the first and second elements, and a sense amplifier for detecting a potential of the first conductive wiring, wherein a first electrode of the first switch element and a second The voltage-current characteristic of the electrode has a rectifying property, and when the voltage between the first and second electrodes is reverse-biased,
The current flowing between the first electrode and the second electrode is changed by changing the voltage between the first electrode and the third electrode of the first switch element, and the first and second electrodes are changed. By applying a potential at which a voltage between the electrodes becomes a forward bias to the second conductive wiring, charges are simultaneously stored in the storage electrodes of the capacitors of the plurality of semiconductor memory elements selected by the second switch element. It is characterized by injection.

Further, the semiconductor memory device of the present invention includes a first switch element having three electrodes, and a capacitor having a storage electrode and a plate electrode, wherein the first electrode of the first switch element is provided. A semiconductor storage element connected to the storage electrode, a conductive wiring in which the plurality of semiconductor storage elements are connected via a second electrode of the switch element, and a sense amplifier for detecting a potential of the conductive wiring Wherein the voltage-current characteristics of the first electrode and the second electrode of the first switch element have a rectifying property, and the voltage between the first and second electrodes is reverse-biased. By changing the voltage between the second electrode and the third electrode of the first switch element, the current flowing between the first electrode and the second electrode is changed, and the potential of the storage electrode is changed. V ₂ + less than Va but greater than or equal _to V ₀ Where the first state, when the potential of the storage electrode is the case the second state is less than V ₂ + Va or V ₁ + Va-V _2, the third a T up to the second state
Time for applying the V ₁ to the electrode, V ₂ and I _d1 current flowing between the first and second electrodes upon application of a V ₁ to the third electrode, the third electrode I _d2 When current is applied between the first and second electrodes, Cs is the capacitance of the capacitor, Cb is the capacitance of the conductive wiring, Va is an arbitrary potential, and is connected in parallel to the conductive wiring. V ₀ , V ₁ , V ₂ are T × I _d1 ≧ Cs × (V ₁ + Va−V ₀ ) T × I _d2 << Cs × (V ₂ + Va−V ₀ ) V ₀ ≦ V ₂ + Va Cs / (Cs + Cb) × (V ₂ + Va) ≦ V ₁ −V ₂ n ≦ I _d1 / I _d2

Further, in the method of manufacturing a semiconductor memory device according to the present invention, a step of forming a capacitor having a storage electrode, a capacitor insulating film and a plate electrode in a semiconductor substrate, and a first step of connecting to the storage electrode are performed. Forming a semiconductor layer having the above conductivity type, forming a gate insulating film on the surface of the semiconductor layer, and forming a gate electrode on the gate insulating film so as to cover at least a part of the semiconductor layer. Forming a diffusion layer or a conductive layer having a second conductivity type so that a junction with the semiconductor layer having the first conductivity type is formed at a position facing the gate electrode with the gate insulating film interposed therebetween. Forming, forming an insulating film covering the gate electrode, and forming a conductive wiring connected to the second diffusion layer or the conductive layer. That.

Further, the method of manufacturing a semiconductor memory device according to the present invention includes a step of forming a diffusion layer or a conductive layer having a second conductivity type on a surface of a semiconductor layer having a first conductivity type;
A gate electrode is formed via a gate insulating film on a surface of the semiconductor layer where an edge of a junction between the semiconductor layer having the first conductivity type and the diffusion layer having the second conductivity type or the conductive layer is located. Forming, forming an insulating film covering the gate electrode, and forming a storage layer connected to the semiconductor layer having the first conductivity type or the diffusion layer having the second conductivity type or the conductive layer. And forming a plate electrode on the surface of the storage electrode via a capacitor insulating film.

As described above, in the semiconductor memory device according to the present invention, the storage electrode is connected to one electrode connected to the two regions separated by the rectifying junction, and the conductive electrode (bit) is connected to the other electrode. Lines), the connection between the storage electrode and the bit line connection hole can be made one.

Further, since this junction has a rectifying property, by applying a reverse bias to this junction, it is possible to cut off the current between the two terminals and prevent punch-through. .

Therefore, the distance between the storage electrode and the bit line connection hole can be reduced, so that a fine memory cell can be realized, and high density can be achieved.

Further, by arranging the gate electrode above the junction, the current flowing through the junction can be controlled by the voltage applied to the gate electrode, so that the amount of charge stored in the storage electrode can be controlled.

As described above, by controlling the voltage between the bit line, the gate electrode, and the storage electrode, it is possible to configure a memory cell that can be randomly accessed by using a plurality of memory cells. Become.

Further, according to the method of manufacturing a semiconductor memory device of the present invention, the gate is formed on the junction between the first diffusion layer connected to the storage electrode and the second diffusion layer connected to the conductive wiring. Since an electrode can be formed, a memory cell that can be miniaturized can be easily manufactured.

[0028]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1A is a plan view of the structure according to the first embodiment of the present invention, and FIGS.
A-A 'section of FIG. 1A and BB', respectively.
It is sectional drawing. In FIG. 1A, only the structure below the gate electrode is shown for the lower memory cell in order to make the structure easier to understand. Although a plurality of memory cells are formed in FIG. 1, it is not always necessary to form them in the arrangement of FIG. 1, and they can be implemented independently.

As in the conventional memory cell described above, a memory cell region is formed on, for example, a p-type semiconductor substrate 1,
A trench 4 is formed inside the substrate 1. The element region is separated by an element isolation insulating film 12 such as an oxide film formed on the surface of the substrate 1. Further, a polycrystalline silicon layer or the like containing a p-type impurity such as boron is buried in the trench 4 via a capacitor insulating film 5 to form a storage electrode 6. That is,
The p-type silicon substrate 1 serves as a plate electrode of a MOS capacitor, and the silicon capacitor 1, the capacitor insulating film 5 and the storage electrode 6 constitute a MOS capacitor. Further, the storage electrode 6 and the substrate 1 are formed on the upper side wall surface of the trench 4.
And an element isolation insulating film 22 for isolating the element.

In the above-mentioned conventional memory cell, it is necessary to increase the distance between the gate electrode 8 and the storage electrode inside the trench 4. However, in this embodiment, the substrate 1 and the trench A gate electrode 8 is formed on the storage electrode 6 buried in 4 with a gate insulating film 7 interposed therebetween. The gate electrode 8 is patterned in one direction of the cell array to form a word line. Under the gate electrode 8, an n-type diffusion layer 9 is formed so as to reach the storage electrode 6, and a pn junction with the storage electrode 6 having a p-type conductivity is formed inside the trench 4. In order to prevent conduction between the storage electrode 6 and the substrate 1, the junction depth must be deeper than the element isolation region 22. As described above, the present invention has a structure in which the storage electrode 6 embedded in the trench 4 has a pn junction on the upper part, and a gate electrode is formed above the pn junction. Also,
The n-type diffusion layer 9 functions as a current input / output terminal of the diode with a gate, and is connected to the bit line 13 via the bit line connection hole 11 formed in the interlayer insulating film 38.

Next, a manufacturing process of the memory cell according to this embodiment will be described with reference to FIG. FIG. 2 (b) of FIG.
13 is a cross-sectional view in a manufacturing step corresponding to the cross section of FIG.

First, a manufacturing process for obtaining a structure as shown in FIG. 2A will be described. For example, if the boron concentration is 1
0 ¹⁸ to the high-concentration p-type Si substrate 1 of 10 ²⁰ cm ^-3, for example, a substrate having a p-type epitaxial layer 31 of boron concentration 10 ¹⁵ cm ^-3. The thickness of the epitaxial growth layer 31 is, for example, 0.7 μm.

Next, for example, boron is ion-implanted into the cell array region and then well diffusion is carried out to reduce the boron concentration of the p-type epitaxial growth layer 31 in the cell array region to 10 ^16.
Optimize 10 ¹⁸ cm ^-3 from. Further, an element isolation film 12 is formed on the upper surface of the Si substrate 1 by, for example, a selective oxidation method.

Thereafter, a trench having a depth of, for example, 1 μm is formed by a lithography method and a reactive ion etching technique. Further, the element isolation insulating film 22 is formed on the wall surface of the trench by, for example, oxidation. The oxide film thickness is, for example, between 5 nm and 200 nm.

Further, after forming the insulating film 22,
In order to secure the thickness of the insulating film 22 and prevent deterioration due to thermal stress due to the thick oxide film, for example, a silicon oxide film is deposited, and the silicon oxide film is anisotropically etched to form the element isolation oxide film 22. It is also possible to add a step of forming an insulating film on the side wall of the semiconductor device. In this way,
By increasing the thickness of the insulating film formed on the side wall of the trench, a short circuit between the storage electrode formed later inside the trench and the substrate can be reliably prevented. Further, the thick insulating film 22 is formed on the side surfaces of the trench only by oxidation.
Is formed, there is a possibility that a defect may occur due to thermal stress or the like. However, according to the above method, after performing thermal oxidation to such an extent that no defect occurs, the thickness of the sidewall insulating film is further increased by deposition. Increases, it is possible to prevent the occurrence of defects and to ensure the element isolation withstand voltage.

Thereafter, the oxide film on the bottom surface of the element isolation oxide film 22 is removed by, for example, a reactive ion etching technique until the Si substrate 1 is exposed. At this time, by selecting the conditions of the reactive ion etching, the element isolation oxide film 22 is formed.
Can be made lower than the etching rate of the bottom surface.

Further, a trench 4 is formed in the Si substrate 1 by, for example, a reactive ion etching technique. The depth of the trench 4 is, for example, between 2 and 10 μm.

Thereafter, in order to increase the capacitance of the capacitor, an impurity such as boron can be ion-implanted into the trench 4 to increase the impurity concentration on the wall surface of the trench 4 serving as the substrate plate electrode.

Next, after forming the capacitor insulating film 5 on the inner wall of the trench 4, a polycrystalline silicon film serving as the storage electrode 6 is deposited. As the capacitor insulating film 5, for example, a stacked film of silicon oxide film / silicon nitride film / silicon oxide film (effective thickness 10 nm) can be used. In addition, for example, boron is ion-implanted into the polycrystalline silicon film to reduce the resistance. Subsequently, the surface polycrystalline silicon film is etched back by, for example, a chemical dry etching technique, and is left as the storage electrode 6 in the trench 4. After that, the capacitor insulating film 5 exposed on the p-type epitaxial layer 31 and the element isolation insulating film 12 is removed by, for example, a chemical dry etching technique to obtain a shape shown in FIG.

Thereafter, as shown in FIG. 2B, silicon is selectively grown to a thickness of, for example, 3 nm to 300 nm to form a silicon layer 2. In this step, after depositing a polycrystalline silicon film over the entire surface, the polycrystalline silicon film is monocrystallized by, for example, a solid phase epitaxial growth method.
Further, a method of removing an unnecessary portion of the silicon film on the element isolation insulating film 12 by, for example, a lithography method and an etching technique may be used.

Thereafter, as shown in FIG. 2C, the silicon layer 2 is oxidized to form a gate oxide film 7 having a thickness of, for example, 3 nm to 100 nm.
A gate electrode material such as a polycrystalline silicon film having a thickness of nm is deposited and, for example, POCl _{3 is} diffused to reduce the resistance.
Further, after depositing an insulating film 36 such as a silicon nitride film, the gate electrode 8 is formed by processing the film by, for example, lithography and reactive ion etching. further,
A resist film having an opening only at the bit line contact 11 is formed, and an n-type impurity such as arsenic or phosphorus is doped with 10 ^13.
10 ¹⁷ cm ^-2 ions are implanted. Thereafter, the resist is removed, thermal diffusion is performed as appropriate, and a p-type storage electrode 6 is formed in the lateral direction.
The n-type impurity is diffused so that the junction with the gate electrode 8 is formed below the gate electrode 8 and the junction with the p-type substrate 1 is formed deeper than the insulating film 22 in the vertical direction. A mold diffusion layer 9 is formed.

[0043] The n-type diffusion layer 9, after forming the silicon layer 2, the region becomes a bit line contact 11 to form an opening resist film, for example, arsenic or n-type impurities such as phosphorus 10 ¹³ 10 the following can also be formed by ¹⁷ cm ^-2 ion implantation, and the insulating film 37 is deposited a silicon nitride film, for example, for example, by using an anisotropic etching technique to remove the silicon nitride film on the substrate 1, steep By leaving the silicon nitride film on the side wall of the gate electrode 8, a side wall insulating film 37 of the gate electrode 8 is formed. The sidewall insulating film 37 and the insulating film 36 cover the gate electrode 8, so that it is easy to maintain electrical insulation between the gate electrode 8 and the bit line 13.

Thereafter, in order to reduce the connection resistance between the bit line 13 and the n-type diffusion layer 9, an n-type impurity such as arsenic is doped with n-type impurity.
It is also possible to further implant ions into the mold diffusion layer 9.

Next, after an interlayer insulating film 38 is entirely deposited,
For example, the bit line contact 11 is formed by a lithography method and a reactive ion etching technique. afterwards,
For example, a bit line electrode material such as a polycrystalline silicon film is deposited, and the bit line 13 is processed by, for example, lithography and reactive ion etching techniques. Complete.

In the above embodiment, the low-concentration epitaxial growth layer 31 is formed on the high-concentration substrate 1 as the substrate. However, the p-type substrate having a boron concentration of 10 ¹⁵ cm ⁻³ is used without forming the epitaxial growth layer 31. Then, at an accelerating voltage of several MeV, the concentration of boron is increased from 10 ¹⁸ to 1
If the ion implantation can be performed so as to be 0 ²⁰ cm ^-3 , it can be used instead.

Further, the trench forming step after the formation of the element isolation region 12 can be performed as follows. For example, the trench 4 is formed in the Si substrate 1 by a reactive ion etching technique. The depth of the trench 4 is, for example,
It is between 2 and 10 μm. Then, for example, by oxidation, the inner wall surface of the trench 4 has a thickness of, for example, 1-100 n.
After forming the oxide film 24 having a thickness of m, a silicon nitride film 35 is deposited to a thickness of, for example, 1 to 100 nm. Further, after applying the resist film, the resist film is removed from the surface of the substrate 1 to a depth of, for example, 1 μm. Furthermore, after removing the exposed silicon nitride film 35 by, for example, a reactive ion etching technique, oxidation is performed to form an oxide film 22 on the trench. The oxide film thickness is, for example, 5 nm to 2
00 nm. Further, after the silicon nitride film 35 remaining in the trench is removed by, for example, a dry etching technique, the oxide film 24 below the trench 4 is removed by using, for example, an ammonium fluoride solution.

As a modification of the above embodiment, instead of the element isolation by the selective oxidation method, a trench element isolation method in which a groove is formed in a substrate and an insulating film is buried can be used.

FIG. 3A is a plan view showing a structure according to a modification of the first embodiment of the present invention, and FIGS. 3B and 3C respectively show FIGS. ) Is a cross-sectional view taken along line AA ′ and a line BB ′. In FIG. 3A,
For simplicity of the structure, only the structure below the gate is shown for the lower memory cell. FIG.
In the above, a plurality of memory cells are formed.
It is not always necessary to form them in the arrangement shown in FIG. 3, and they can be implemented independently.

In this modification, the element isolation is performed by the insulating film 41 embedded in the groove formed in the substrate 1 instead of the element isolation insulating film 12 by the selective oxidation method in the first embodiment. Is the feature.

Next, the manufacturing method of the present modification will be described with reference to FIG.

In this modification, the trench 4 is formed in the substrate 1 without forming the element isolation insulating film 12 using the selective oxidation method of the first embodiment. Further, similarly to the first embodiment, an element isolation insulating film 22 is formed on the side wall of the trench 4, a capacitor insulating film 5 is formed, and a first polycrystalline silicon film serving as the storage electrode 6 is formed inside the trench. (FIG. 4A).

Thereafter, a resist film having an opening in an element formation region is formed, and a part of the element isolation insulating film 22 is removed by etching. The removal depth is, for example, 3 nm to 500 n.
m. Next, a second polycrystalline silicon film serving as the storage electrode 6 'is deposited, and boron is ion-implanted, for example, to lower the resistance of the second polycrystalline silicon film.

Subsequently, the second polycrystalline silicon film is etched back by, for example, a chemical dry etching technique, and is left inside the trench 4 as the storage electrode 6 '.
((B) of FIG. 4).

Further, as shown in FIG. 4C, a groove is formed by etching the substrate 1 and the storage electrodes 6, 6 'in the element isolation region by using a lithography method and an etching technique. The etching depth is, for example, between 100 nm and 800 nm. Thereafter, as a punch-through stopper, for example, boron can be ion-implanted at about 10 ¹² to 10 ¹⁴ cm ⁻² . Further, after depositing an insulating film 41 such as a silicon oxide film, the surface of the substrate 1 is exposed by, for example, an etch back or polishing method, and the element isolation insulating film 41 is left inside the groove.

Thereafter, the steps after the step of forming the gate insulating film 7 are performed in the same manner as in the first embodiment.

As described above, the first embodiment of the present invention is characterized in that a diode with a gate is used as a control element instead of the MIS transistor which has conventionally constituted a DRAM memory cell. . here,
The diode with a gate includes a gate electrode 8, a gate oxide film 7, and an n-type diffusion layer 9 connected to a bit line 13.
And a storage electrode 6 or 6 ′ having a p-type conductivity.

In such a structure, since there is no problem of punch-through unlike the conventional MIS transistor, the distance between the storage electrode 6 and the bit line connection hole 11 can be made smaller than in the conventional case. is there.

In particular, in the structure of the first embodiment, since the gate electrode 8 can be formed above the trench 4, the distance between the bit line connection hole 11 and the trench 4 is set to be smaller than that of the conventional DRAM. It can be made very small, and can have higher density.

In the conventional MIS transistor, the threshold voltage of the transistor rises as the potential of the storage electrode 6 rises due to the writing of data, that is, the potential of the gate electrode 8 is reduced by the so-called substrate bias effect. Although it was necessary to increase the voltage by the rise of the threshold voltage, the structure of the present invention has no substrate bias effect, so that the gate electrode 8
There is no need to boost the voltage of

Further, since there is no problem of punch-through as described above, the junction depth of the diffusion layer 9 connected to the bit line 13 can be increased, and the contact resistance and the diffusion resistance can be reduced.

Since the diode junction (junction between the n-type diffusion layer 9 and the storage electrode 6) of the diode with a gate is on the storage electrode 6 and the depletion layer region due to the junction is not in contact with the substrate 1, the alpha ray It is possible to prevent electrons or holes generated by the particle beam from flowing out to the substrate 1. For this reason, resistance against soft errors caused by these charges can be improved.

Next, the electrical operation of the memory cell in which the diode with the gate and the capacitor are connected will be described by taking the structure according to the first embodiment of the present invention as an example.
This operation can be applied not only to the structure according to the above-described first embodiment but also to the structure according to another embodiment.

First, the operation of the diode with a gate will be described with reference to FIG. Here, as an example, a case is shown in which a gate electrode 8 is formed on a pn junction between a p-type diffusion layer 51 and an n-type diffusion layer 9 with a gate oxide film 7 interposed therebetween. Is formed in the same manner.

In this device, a reverse bias voltage is applied to the pn junction as shown in FIG.
Further, by applying a gate voltage in a direction to deplete the n-type diffusion layer 9, the current flowing through the n-type diffusion layer 9 can be controlled as shown in FIG.

This current is changed to pn by application of a gate electric field.
A reduction in the reverse breakdown voltage at the junction (hereinafter referred to as junction breakdown), and a depletion of the surface of the n-type diffusion layer 9 due to the application of the gate electric field to cause surface tunneling (hereinafter referred to as "depletion breakdown") -depletion-bre
akdown), the generated current increases when the depletion layer due to the application of the gate electric field reaches a crystal defect existing in the n-type diffusion layer 9 which is not covered by the gate electrode 8 (hereinafter, the gate edge generated current ( gate edge generation). In particular, the junction breakdown and the depletion breakdown (deep-depleti) shown in FIG.
on breakdown) Regarding the current,
Proceedings of the Semiconductor Seminar ".

Further, as shown in FIG. 5A, by introducing a defect into the diffusion layer at the gate edge, when a voltage causing the n-type diffusion layer 9 to be depleted is applied to the gate electrode, Since the current generated from the defect increases, it is possible to control the current flowing through the n-type diffusion layer 9 by applying the gate voltage. For example, after patterning the gate electrode, an element such as, for example, silicon (Si), arsenic (As), phosphorus (P), germanium (Ge), and the like, having a concentration of 10 ¹³
From 10 ²⁰ cm ^-3, ion-implanted with 200keV from an acceleration voltage 5, a region which is not covered with the gate electrode to amorphous. Further, by performing recrystallization by heat treatment, stacking faults can be formed at the edge of the gate electrode as shown in FIG.

Of course, these factors may be executed by only one, may be executed by combining a plurality of them,
Other factors described herein may be used.

Next, the operation of the memory cell will be described. Here, V ₁ is defined as a voltage for providing an on current of the diode with a gate, and V ₂ and V ₀ are defined as voltages for providing an off current.

A capacitor is connected to the p-type layer 51 shown in FIG. 5A, a bit line (hereinafter abbreviated as BL) is connected to the n-type layer 9, and a word line (hereinafter abbreviated as WL) is connected to the gate. Are connected, one memory cell as shown in FIG. 5C can be realized. The other terminal of the capacitor is connected to the plate electrode.

Hereinafter, the circuit configuration of the DRAM according to the present invention will be described, but the notation of the memory cell is simplified as shown in FIG. The feature of the circuit configuration according to the present invention is shown in FIG.
(B), the simultaneous erase line 52 with the potential of the n-type layer of the cell at V ₀ and _{two of} V ₁ + Va and V ₂ + Va
And a sense amplifier system 53 of a normal DRAM operating between two potentials. This makes it possible to arrange memory cells in a matrix at the intersection of the lattices of BL13 and WL8, A storage device can be realized.

Further, in FIG. 6B, the simultaneous erase line 52
And a transistor T52 is provided between BL13 and BL13,
"0" by writing control line 54 controls the gate voltage of the transistor T52, the selected potential V ₀ BL13
Only communicate to. This MISFET (T52)
Can be replaced with a bipolar transistor 55 as shown in FIG.

Next, the operation of this memory cell will be described with reference to FIGS. It is assumed that the potential of the p-type layer of the cell is driven by a voltage between V ₀ and V ₁ . here,
The potential of the storage electrode 51 of the cell storing “0” data is
Set within a range from V ₀ to V ₂ + Va, the potential of the storage electrode 51 of the cell storing "1" data, in the range from V ₂ + Va to V ₁ + Va. Further, V _WL0 is defined as a potential greater than V ₁ + Va−V ₂ as the potential of WL.

The memory cell operation is roughly classified into the following three operations.

1) Writing "0" (Simultaneous Erasing) Since the potential of the p-type layer of the cell is set so as to be driven by a voltage between V ₀ and V ₁ , FIG. As shown in (2), by applying V ₀ to BL, the junction of the gated diode becomes forward biased, and the potential of the storage electrodes 51 of all cells becomes V _{0 in} a steady state regardless of the gate voltage. .

2) Writing "1" First, the state in which V ₁ + Va is applied to BL is “1”, V ₂
The state where + Va is applied is “0”, the state where Va is applied to WL is “1”, and the state where a voltage of V ₁ + Va−V ₂ or more is applied is “0”.

1) For the cell in which "0" has been written by the simultaneous erasure, as shown in FIG.
a, by applying a voltage of V ₁ + Va to BL, it can be written "1" to a selected cell, i.e., a voltage of V ₁ + Va. In this case, although erroneous writing becomes "0" to "1" of the other cells is an issue, for example, in FIG. 8 (c), (d) , (e), the the WL respectively Va + V ₁ -V ₂ or more of the potential (V _WL0), the BL V
By applying ₂ + Va, (BL) is always applied to cells other than the cell at the intersection where Va is applied to WL and V ₁ + Va is applied to BL.
(Voltage of WL) − (voltage of WL) ≦ V ₂ . Therefore, as long as the pulse width of the condition 1 is satisfied, the potential of the storage electrode 51 of the cell can be kept at a potential between V ₀ and V ₂ + Va, and the information of the cell is kept at “0”.

3) Reading As shown in FIGS. 9A and 9B, for example, V ₁ + Va is applied to BL as a precharge voltage, and WL is applied.
To turn on the gated diode of the selected cell to read the potential of the storage electrode.

At this time, the potential of the storage electrode of the memory cell corresponding to “0” is from V ₀ to V ₂ + Va.
Since the potential of the storage electrode of the cell corresponding to “1” changes from V ₂ + Va to V ₁ + Va, reading is performed by V ₂ + V
The detection can be performed by using a sense amplifier in which the cell potential of a is set to a dummy level. Of course, the sense amplifier may be a current detection type sense amplifier instead of a voltage detection type sense amplifier.

Here, FIG. 9 shows V ₁ + Va as the bit line precharge voltage, but it is not necessarily V ₁ + V
a is not necessary, and if a voltage for turning on the gated diode of the selected cell is given, the potential V at the time of writing is given.
_It may be lower than ₁ + Va.

As shown in FIG. 9C, the WL of the non-selected cell is set to Va + V ₁ − in the same manner as in the writing.
By applying V ₂ or more potential, by turning off the gated diode, data can be held.

FIGS. 10 to 12 show a cell configuration diagram and a timing chart for explaining operations at the time of writing "0", writing "1", and "reading". Respectively,
(A) in the figure shows the connection configuration between the memory cell and the word lines and bit lines, and (b) in the figure shows a timing chart.

Here, as shown in FIGS. 10 to 12A, four memory cells are connected in parallel, and this connection line is connected to a common bit line via one selection gate T4 or T5. It is connected. The hatched cells are cells to be written or read.

In FIGS. 10 to 12B, V _s1 and V _s2 denote the gate voltages of the selection gates T4 and T5, and V _on and V _off denote the conduction or interruption of these T4 and T5. Gate voltage. Further, VWL _sel and VWL _unsel are the selected cell,
The gate voltage of the non-selected cell, the potential of VBL common bit line, VBL _sel and VBL _unsel shows the bit line potential and the bit line potential than the bit lines, each selected cell is connected.

First, the operation of the memory cell when "0" is written will be described. FIG. 10 shows a case where four memory cells connected to a common bit line are selected via a selection gate T4, "0" is written in these memory cells, and no writing is performed in other cells. . After setting the gate voltage V _s1 of the selection gate T4 to which the selected cell is connected to V _on to turn _on T4 and setting the gate voltage V _{s2 of} T5 to which the unselected cell is connected to V _off , the potential of the common bit line is changed. the VBL and V _0. As described above, in the “0” write, the selection gate T
"0" is written to all the cells connected to "4".

FIG. 11 is a time chart for explaining the operation of writing "1" to a selected memory cell. V gate voltage VWL _sel of the selected cell from V _WLO
in a, it sets the potential VBL _sel of the bit line to V ₁ + Va,
The gate voltage VWL _unsel of the unselected cell is kept at V _WLO ,
The potential VBL of the bit line not connected to the selected cell
_unsel is set to V ₂ + Va. At this time, the gate voltage of the selection gate T4 is set to _Von , and the potential of the bit line is applied to the selected cell. Thus, W of the selected cell and the non-selected cell
By setting the potentials of L and BL, FIG.
As described above, "1" can be written in only the selected cell, and "0" can be held in other cells.

FIG. 12 is a timing chart at the time of reading. The potential of the bit line is set to, for example, V ₁
The precharge potential is set to + Va, and the select gate T4 between the selected cell and the sense amplifier is turned on. Furthermore, the Va gate voltage VWL _sel of the selected cell from V _WLO, the gate voltage VWL _unsel unselected cell by holding the V _WLO, the sense amplifier charges accumulated in the selected cell to transmit a bit line And reaches “1” or “0” by comparing with a certain dummy potential, for example.
The signal is further amplified and read.

By applying a potential at such a timing, data of an arbitrary memory cell can be read without destroying data of another memory cell.

Further, as described above, by constructing a plurality (n) of memory cells, destroying "1" or "0" data for an arbitrary selected cell and destroying data of other cells. Instead, to write and read, V ₁ , V ₂ ,
V ₀ needs to be set as a voltage satisfying the following conditions.

T × I _d1 ≧ Cs × (V ₁ + Va−V ₀ ) (1) T × I _d2 << Cs × (V ₂ + Va−V ₀ ) (2) V ₀ ≦ V ₂ + Va (3) Cs / (Cs + Cb) × (V ₂ + Va) ≦ V ₁ −V ₂ (4) n ≦ I _d1 / I _d2 (5) where T is a pulse time for applying V ₁ to the gate electrode at the time of writing “1”. (“1” write time), I _d1 is a current flowing between the pn junctions when V ₁ is applied to the gate electrode with the voltage of the drain 9 set to 0 V, and I _d2 is V
Current flowing between the pn junctions when ₂ is applied, Cs is the capacity per cell, Cb is the bit line capacity, Va is any potential, and n is the memory cell connected to one bit line operating simultaneously. Is the number of

Equation (1) shows the relationship between the “1” write time and the current flowing through the pn junction in order to sufficiently write “1” data to the storage electrode. Equation (2) shows a condition for preventing data of the non-selected cell from being destroyed by a leak current from the non-selected cell while writing “1” to the selected cell. Equation (3) shows the relationship between the dummy potential for determining “0” and “1” of the sense amplifier and the simultaneous erase potential. Equation (4)
Indicates a condition so as not to destroy data of a non-selected cell when "1" is read from the selected cell. Furthermore, equation (5) shows the limit on the number of memory cells that can be connected to one bit line.

The operation of the DRAM of the present invention is ensured by the above-described conditions such as the voltage and current, and the above-described potential relationship and potential application timing.

The writing and reading operations of the memory cell n shown in FIGS. 8 to 12 are not limited to the above-described memory cell structure, but are performed by using an element having at least three terminals having the following characteristics. can do. That is, the voltage-current characteristics of the second electrode (n-type diffusion layer 9) and the third electrode (p-type storage electrode 51) have rectifying properties, and the voltage between the second electrode and the third electrode is reduced. In the first voltage range (forward bias), a current flows between the second electrode and the third electrode irrespective of the potential of the first electrode (gate electrode 8), and in the second voltage range, By changing the voltage between the first electrode and the second electrode, the third electrode and the third
The current flowing between the electrodes can be changed.

For example, it is possible to use the structure of FIG. 13A in which the conductivity type of the pn junction of the memory cell is reversed. At this time, the potential relationship between the electrodes of the element is reversed between the gate and the drain as shown in FIG.
If the definitions of the voltage and the current are changed as shown in FIGS. 13A and 13B, it is clear that the discussion thus far holds.

For example, as shown in FIG. 14, the second electrode 17 is made of a metal of Ta, Ti, Hf, Co, Pt, Pd or a metal made of silicide thereof, and the third electrode 1 is made of a semiconductor. Alternatively, a Schottky diode with a gate can be used. FIG. 14 is a diagram for explaining the operation principle of a gate control diode using a Schottky junction. FIG. 14A is a cross-sectional view showing the structure of a gated Schottky diode. As shown in FIG. This device is a device in which the diffusion layer 9 of the diode with a gate shown in FIG.

In this device, by applying a positive voltage to the gate electrode 8, conduction electrons are accumulated in a region of the semiconductor substrate 1 in contact with the gate insulating film 7, and this region is compared with a deep region of the semiconductor substrate 1. Thus, a higher concentration n-type layer can be obtained. Therefore, the width of the depletion layer formed on the semiconductor substrate 1 side by the Schottky junction in the region in contact with the gate insulating film 7 can be reduced. (B) and (c) of FIG. 14 show the energy band structure along the AA ′ section in (a) of FIG. As shown in this figure, when a positive voltage is applied to the gate electrode 8 (FIG. 14 (b)), compared with the case where no voltage is applied (FIG. 14 (b)), the Schottky junction is used. The width of the formed depletion layer in the section AA ′ direction becomes thin. If the thickness of the depletion layer is sufficiently small, a tunnel current flows from the metal layer 17 to the semiconductor substrate 1, and the current flowing through the Schottky junction increases. In this manner, the current from the metal layer 17 to the semiconductor substrate 1 via the Schottky junction can be controlled by the voltage applied to the gate electrode 8.

Also, '95 IEDM. Technical Digest p
p.645-648 J.P. H. It is also possible to use a device using a tunnel phenomenon between the surface electron channel and the hole channel on the buried oxide film interface side in the SOI device shown by Choi et al.

Next, as a second embodiment, a memory cell in which a diode with a gate is formed on an insulating layer will be described with reference to FIG. FIG. 15A is a structural plan view according to the second embodiment of the present invention, and FIG.
15A and 15C are cross-sectional views taken along lines AA ′ and BB ′ of FIG. In FIG. 15A, only the structure below the gate is shown for the lower memory cell in order to make the structure easy to understand. Although a plurality of memory cells are formed in FIG. 1, it is not always necessary to form them in the arrangement of FIG. 15, and they can be implemented independently. 1 and 2 are denoted by the same reference numerals, and detailed description is omitted.

The memory cell according to the present embodiment has the first
As in the first embodiment, a gated diode and a storage capacitor are provided. However, the first thing is that the gated diode is formed in the semiconductor layer on the insulating layer 62 and the element isolation insulating film 22 becomes unnecessary. This is different from the embodiment.

In this structure, first, instead of the silicon substrate 1 of the first embodiment, for example, a semiconductor layer made of silicon or the like, an insulating layer 62, and a semiconductor substrate 61 made of silicon or the like are used.
(SOI substrate) composed of at least three layers
Is used. Here, the thickness of the semiconductor layer is, for example, 30 nm.
To 500 nm, and the thickness of the insulating layer 62 is between 50 nm to 1000 nm. Such an SOI substrate is formed, for example, by bonding two semiconductor substrates made of silicon or the like with the insulating film 62 interposed therebetween, and forming one of the substrates to a desired thickness by etching or mechanical polishing, or forming oxygen ions in the silicon substrate. It can be formed by an implantation method (so-called SIMOX).

As the method of forming the element isolation 12 used here, a selective oxidation method, trench isolation, mesa isolation, isolation using a field shield gate, or the like can be used.

The manufacturing process is the same as that of the first embodiment except that the process of forming the element isolation insulating film 22 is omitted, and therefore the description is omitted.

The second embodiment has the following features in addition to the features of the first embodiment.

First, in the above-described first embodiment, the storage electrode 6 and the substrate 1 are separated by the n-type diffusion layer 9 and the element isolation insulating film 22. In order to prevent a short circuit, it is necessary to form a junction between the n-type diffusion layer 9 and the storage electrode 6 inside the trench 4. However, in the present embodiment, the insulating layer 62 is provided below the n-type diffusion layer 9.
And the substrate 61 is not directly in contact with the n-type diffusion layer 9.
Thus, since the storage electrode 6 and the substrate 61 are separated by the insulating layer 62, the junction between the diffusion layer 9 and the storage electrode 6 does not always need to be formed inside the trench 4.

For example, as shown in FIG. 16, the junction between the diffusion layer 9 and the p-type diffusion layer connected to the storage electrode 6 is not on the trench 4 but on the bit line connection hole rather than on the trench 4 pattern. 11 side.

Therefore, when the n-type diffusion layer 9 is formed on the gate electrode 8 in a self-alignment manner, the margin for patterning between the gate electrode 8 and the trench 4 can be relaxed. When the diffusion layer is formed earlier than the gate electrode, the margin of alignment between the n-type diffusion layer 9 and the trench 4 can be reduced.

Further, in this embodiment, since the SOI substrate is used, the capacity of the diffusion layer 9 connected to the bit line 13 can be reduced, so that the capacity of the bit line 13 can be reduced. In this way, by improving the signal sensitivity, it is possible to improve the resistance against so-called soft errors.

A conventional DRAM memory cell comprising a MOS transistor and a capacitor is
When formed on the upper side, the substrate below the channel region of the MOS transistor becomes floating and the potential is not fixed. Therefore, when the potential of the bit line rises, the potential of the substrate also rises due to coupling of the junction, and the punch-through occurs. However, in this embodiment, since all the terminals of the gated diode are connected to the BL, WL, and the charge holding capacitor, punch-through due to the substrate floating effect as in the related art can be achieved. No adverse effect is caused.

Next, the structure of a memory cell for increasing the storage capacity will be described as a third embodiment. FIG. 17A is a structural plan view according to the third embodiment of the present invention, and FIGS. 17B and 17C are FIGS.
10A is a cross-sectional view taken along line AA ′ and line BB ′ of FIG. FIG.
In FIG. 7A, only the structure below the gate is shown for the lower memory cell in order to make the structure easier to understand. Further, in this embodiment, a plurality of memory cells are formed. However, these need not necessarily be formed in the arrangement shown in FIG. 17 and can be implemented independently. 1 and 2 are denoted by the same reference numerals, and detailed description is omitted.

In this embodiment, as in the second embodiment, a memory cell is formed by a diode with a gate and a capacitor, and the diode with a gate is formed on an SOI substrate. The method for forming the electrodes is different from that of the second embodiment. In the present embodiment, a cylindrical so-called crown-type storage electrode 6 is used in order to improve the capacity of the storage electrode 6.

The manufacturing process of the memory cell of this embodiment will be described with reference to FIG. FIG. 18 is a manufacturing process sectional view corresponding to the section of FIG.

First, as shown in FIG. 18A, for example, a p-type Si substrate 71 having a boron concentration of 10 ¹⁵ cm ⁻³ is prepared, and for example, boron is ion-implanted into the cell array region to perform a diffusion step. , A p-well is formed, and the concentration of the cell array region is optimized. Further, an element isolation film 12 is formed on the upper surface of the Si substrate by using, for example, a selective oxidation method.

Next, an insulating film 7 such as a silicon oxide film
2 is deposited to a thickness of, for example, 30 nm to 500 nm.
Subsequently, the insulating film 72 is formed using an anisotropic etching technique such as a lithography method and a reactive ion etching technique.
Is etched to open a connection hole 11 'for the storage electrode. Next, for example, a polycrystalline silicon film 73 or the like is deposited, and the polycrystalline silicon film 73 on the insulating film 72 is polished or the like.
Is removed and embedded in the connection hole 11 ′.

Thereafter, an insulating film is further deposited, and an opening is formed so as to expose the polycrystalline silicon film 73 by etching the insulating film by, for example, lithography and reactive ion etching. Next, for example, the polycrystalline silicon film 7
6 is deposited, and the polysilicon film 76 is etched by an anisotropic etching technique such as reactive ion etching to leave the polysilicon film 76 on the side wall of the opening. In this way, as shown in FIG.
The crown type storage electrode 6 is formed by the polycrystalline silicon film 73 and the polycrystalline silicon film 76. The height of the crown is, for example, between 0.2 μm and 2.0 μm. Here, after laminating the polycrystalline silicon layer 76, for example, boron is ion-implanted by about 10 ¹³ cm ⁻² to 10 ¹⁸ cm ⁻² to mix the interface between the polycrystalline silicon layers 73 and 76 to reduce the connection resistance. It is also possible to reduce it.

Thereafter, the insulating film is removed, a capacitor insulating film 5 is formed on the upper surface and side surfaces of the storage electrode 6, and then a polycrystalline silicon film 10 serving as the plate electrode 10 is deposited. The capacitor insulating film 5 is, for example, a laminated film of silicon oxide film / silicon nitride film / silicon oxide film (effective film thickness 10 n).
m). For example, boron or the like is diffused into the polycrystalline silicon film 10 to reduce the resistance.

Next, the wafer is inverted and the silicon substrate 71
By the polishing or etching technique.
Etching is performed from the side of the silicon substrate 71 until is exposed, and a silicon thin film layer 16 to be an element region is formed as shown in FIG. At this time, the element isolation insulating film 1
By setting the etching conditions such that the etching rate for the silicon substrate 2 is lower than the etching rate for the Si substrate 71, the etching can be stopped with good controllability when the surface of the element isolation insulating film 12 is exposed. The thin film layer 16 can be formed.

Thereafter, the gate oxide film 7, the gate electrode 8, the n-type diffusion layer, the bit line 13 and the like are formed in the same manner as in the first embodiment to complete the DRAM.

Although the crown-shaped storage electrode 6 is shown here, a storage box 6 having a so-called simple box shape as shown in FIG. 19 or a fin shape as shown in FIG. 20 can also be used. In addition, any shape of storage electrode can be used as long as the storage electrode can form a stacked capacitor storage electrode.

As described above, the present embodiment has the following features in addition to the features of the above-described first and second embodiments. That is, the shape of the storage electrode 6 is
By adopting a shape such as a crown type or a fin type, the width of which increases from the substrate surface to the bottom, a capacitor electrode with a larger surface area than the simple trench shape can be formed, and the accumulated charge can be increased Becomes

Next, as a fourth embodiment, a memory cell having a planar capacitor on an SOI substrate will be described. FIG. 21A is a structural plan view according to the fourth embodiment of the present invention, and FIGS.
FIG. 22 is a cross-sectional view taken along line AA ′ and line BB ′ of FIG. In FIG. 21A, only the structure below the gate is shown for the left memory cell to make the structure easy to understand. Here, a plurality of memory cells are formed. However, these need not necessarily be formed in the arrangement shown in FIG. 21 and can be implemented independently. 1 and 2 are denoted by the same reference numerals, and detailed description is omitted.

In this embodiment, similarly to the second embodiment, a memory cell is constituted by a diode with a gate and a capacitor, and the diode with a gate is formed on an SOI substrate. The method for forming the electrodes is different from that of the second embodiment. In the present embodiment, instead of the trench capacitor of the second embodiment, a semiconductor substrate layer 83 of, for example, silicon of an SOI substrate is used.
Is formed on the MIS capacitor.

In this embodiment, the element isolation insulating film 12 is formed on the semiconductor substrate layer 83 of the SOI substrate formed in the same manner as in the second embodiment, for example, by selective oxidation. Next, for example, the semiconductor substrate layer 83 is used as the storage electrode 6.
A p-type diffusion layer is formed on the
Is formed, for example, a polycrystalline silicon film 15 is deposited. The capacitor insulating film 5 is, for example, a stacked film of silicon oxide film / silicon nitride film / silicon oxide film (effective film thickness 10n).
m). Further, for example, boron or the like is added to the polycrystalline silicon film 15 to reduce its resistance, and further, the plate electrode 15 is formed by patterning. Thereafter, the gate electrode 8 and the like are formed in the same manner as in the first embodiment.

It is also possible to form gate electrode 8 before or simultaneously with this MIS capacitor.

The fourth embodiment has the following features in addition to the features of the first and second embodiments. That is, in the present embodiment, since the trench 4 is not formed, the manufacturing process is easy, and the process is less affected by process variations such as the depth of the trench 4. As described above, since a capacitor having a constant capacitance can always be formed, a stable operation of the DRAM can be guaranteed.

In the second embodiment, since the storage capacitor is formed inside trench 4 formed through insulating layer 82 of the SOI substrate, the depth of trench 4 and the depth of insulating layer 82 are reduced. The capacitance changes depending on the thickness. However, in this embodiment, since the capacitor is formed on the insulating layer 82, a capacitor having a stable capacitance can be formed regardless of the depth of the trench 4 or the thickness of the insulating layer 82.

Next, as a fifth embodiment, a memory cell having a stacked capacitor on an SOI will be described with reference to FIG.

FIG. 22A is a structural plan view according to the fourth embodiment of the present invention, and FIGS. 22B and 22C.
Are respectively AA ′ and BB ′ in FIG.
It is sectional drawing. In FIG. 22A, only the structure below the gate is shown for the left memory cell to make the structure easy to understand. In this embodiment, a plurality of memory cells are formed, but these need not necessarily be formed in the arrangement shown in FIG. 22 and can be implemented independently. 1 and 2 are denoted by the same reference numerals, and detailed description is omitted.

In this embodiment, as in the fourth embodiment, a memory cell is formed by a diode with a gate and a capacitor, and the diode with a gate is formed on an SOI substrate. 15 is different from the fourth embodiment. In this structure,
In order to improve the capacity of the storage electrode, a stacked MIS capacitor is formed instead of the planar MIS capacitor of the fourth embodiment. That is, the capacitor includes the storage electrode 6, the capacitor insulating film 5, and the plate electrode 15.

In the present embodiment, for example, an element isolation insulating film 12 is formed on a semiconductor substrate layer 93 of, for example, silicon or the like of an SOI substrate formed in the same manner as in the fourth embodiment by, for example, a selective oxide film method. I do. Then, the semiconductor substrate layer 9
3 is oxidized to form a gate oxide film 7 having a thickness of, for example, 3 nm to 100 nm, for example, 50 nm to 400 nm.
Then, a polycrystalline silicon film having a thickness of ₃ nm is deposited, for example, by diffusion of POCl ₃ to reduce the resistance. Further, after depositing, for example, a silicon nitride film 94, etching is performed using an anisotropic etching technique such as lithography and reactive ion etching to form the gate electrode 8. Further, a resist film having an opening in at least a diffusion layer region connected to the bit line contact 11 is formed, and arsenic, phosphorus, or the like is ion-implanted at 10 ^{13 to} 10 ¹⁷ cm ⁻² to form the n-type diffusion layer 9. Form.

After forming the semiconductor substrate layer 93 or the element isolation insulating film 12, the n-type diffusion layer 9 forms a resist film in which a diffusion layer region connected to the bit line contact 11 is opened. 10 ^{13 to} 10
^It can also be formed by ion implantation at ¹⁷ cm ⁻² . In this case, a gate electrode needs to be formed on a junction between n-type diffusion layer 9 and p-type region 93 connected to storage electrode 6 in a step of forming gate electrode 8 later.

Next, an insulating film such as a silicon nitride film is deposited, the insulating film is removed by anisotropic etching, and the insulating film is left on the side wall of the gate electrode 8 which has been cut. Is formed. As described above, since the insulating films 95 and 94 have a structure covering the gate electrode 8, it is easy to maintain electrical insulation from the bit line 13.

Thereafter, for example, after forming an interlayer insulating film 96, a connection hole between the storage electrode 6 and the semiconductor substrate layer 93 is formed, and for example, a polycrystalline silicon film is formed, for example, from 100 to 400.
The storage electrode 6 is formed by depositing a film having a thickness of nm and processing it using an anisotropic etching technique such as lithography and reactive ion etching. At this time, the resistance can also be reduced by, for example, implanting boron or the like at 10 ^{13 to} 10 ¹⁷ cm ⁻² . Thereafter, the capacitor insulating film 5 is formed on the upper and side surfaces of the storage electrode 6, and further, for example, a polycrystalline silicon film is deposited. Capacitor insulating film 5
Is a laminated film of silicon oxide film / silicon nitride film / silicon oxide film (effective thickness: 10 nm), for example. After lowering the resistance of the polycrystalline silicon film 15 by, for example, arsenic or phosphorus, the plate electrode 15 is formed by processing using, for example, a lithography method and an etching technique.

Next, after depositing the interlayer insulating film 97, the interlayer insulating film 97 is opened by using an anisotropic etching technique such as lithography and reactive ion etching.
A bit line connection hole 11 is formed. Thereafter, a bit line material such as a polycrystalline silicon film is deposited, and the polycrystalline silicon film is processed to form a bit line 13 using, for example, a lithography method and an anisotropic etching technique such as reactive ion etching. . Thereafter, if necessary, the upper wiring layer is processed by a usual method to complete the DRAM.

In the present embodiment, in addition to the effects of the fourth embodiment, since the storage electrode 6 is also formed on the element isolation region 12 and the gate electrode 8, the surface area of the storage electrode 6 is increased. , The accumulated charge increases, and D
A stable operation of the RAM can be guaranteed.

FIG. 22 shows a case where the storage electrode 6 is a simple box type. However, for example, the storage electrode 6 having a shape such as a crown type or a fin type shown in the third embodiment is used. It is also possible.

Next, a sixth embodiment of the present invention will be described.
This will be described with reference to FIGS. (A) of FIG.
FIG. 23 is a plan view showing a structure of a semiconductor device according to a sixth embodiment of the present invention, and FIG. 23B is a cross-sectional view taken along the line AA ′ of FIG.

In FIG. 23, a plurality of memory cells are formed. However, these need not necessarily be formed in the arrangement shown in the figure, and can be implemented independently. 1 and 2 are denoted by the same reference numerals, and detailed description is omitted.

The memory cell according to the present embodiment has the first
Similarly to the first embodiment, the second embodiment is configured by a diode with a gate and a storage capacitor, but is different from the first embodiment in that the diode with a gate is buried inside the trench and formed vertically. .

That is, as shown in FIG.
A storage electrode 6 is formed inside a trench 4 formed in the mold semiconductor substrate 1 via a capacitor insulating film 5. The storage electrode 6 is connected to a p-type semiconductor layer 116 ′ via an embedded electrode 116 formed on the storage electrode 6.
The p-type semiconductor layer 116 'forms a junction with the n-type diffusion layer 9. A gate electrode 8 is formed in contact with the pn junction via a gate insulating film 7. N-type diffusion layer 9 is connected to bit line 13 through bit line connection hole 11. As described above, in the present embodiment, the junction between the p-type semiconductor layer 116 ′ connected to the storage electrodes 6 and 116 and the n-type diffusion layer 9 is formed in the trench 4 in the vertical direction. Further, the gate electrode 8 is in contact with the side surface of the
It is formed so as to be embedded in.

Next, a method of manufacturing a memory cell according to this embodiment will be described. 24 to 32 are process cross-sectional views for explaining the method for manufacturing the memory cell according to the present embodiment, in which (a) is a plan view and (b) is A in FIG.
It is -A 'sectional drawing.

First, for example, when the boron concentration is 10 ¹⁵ to 10
^On a p-type semiconductor substrate 1 of ²⁰ cm ^-3 , for example, a depth of 0.1 to 2
A trench isolation made of the insulating film 111 having a depth of μm is formed (FIG. 24). As the insulating film 111, for example, it is desirable to use a silicon oxide film or a silicon nitride film, or a composite film thereof.

Next, after insulating films 113, 114, and 115 serving as mask materials for trench formation are deposited, trenches 4 are formed by lithography and reactive ion etching.
Is formed (FIG. 25). The depth of the trench 4 is, for example, 1 μm.
m to 20 μm. Insulating films 113, 114, 1
For example, 15 is preferably a silicon oxide film or a silicon nitride film, or a composite film thereof.

Thereafter, in order to increase the capacitance of the capacitor formed on the wall surface of the trench 4, an impurity such as boron can be added to the side wall surface and the bottom surface of the trench 4 by, for example, ion implantation. Next, after a capacitor insulating film 5 is formed on the wall surface of the trench 4, for example, a polycrystalline silicon film serving as a storage electrode 6 is deposited. The capacitor insulating film 5 is, for example, a laminated film of silicon oxide film / silicon nitride film / silicon oxide film (effective thickness: 1 to 20 nm). For example, the resistance of the polycrystalline silicon film can be reduced by ion implantation of As. Also, for example, P, As, B, etc. can be added simultaneously with the deposition of the polycrystalline silicon film. Subsequently, the polycrystalline silicon film 6 and the capacitor film 5 are etched back by, for example, a chemical dry etching technique to expose the mask material 115, and then the mask material 115 is removed. further,
The polycrystalline silicon film 6 is etched back, and as shown in FIG. 26, the polycrystalline silicon film is left inside the trench 4 to form the storage electrode 6.

Further, an insulating film 12 such as a silicon oxide film is deposited inside the trench 4 and on the mask material 114, and the insulating film 1 is formed by, for example, an anisotropic etching technique.
2 is etched to form the bottom surface of the trench 4 and the insulating film 1
The insulating film 12 on 14 is removed, and the insulating film 12 is left only on the side wall of the trench 4. The thickness of the insulating film 12 is, for example, between 5 nm and 200 nm. Further, after the resist film 45 is applied, the resist film 45 inside the trench 4 is removed from the surface of the substrate 1 by, for example, 0.1
It is removed to a depth of １1 μm (FIG. 27).

Thereafter, the insulating film 12 and the capacitor insulating film 5 on the upper side surface of the trench 4 are removed by using, for example, an ammonium fluoride solution, and the semiconductor substrate 1 is exposed. After that, the resist film 45 inside the trench 4 is removed,
The storage electrode 6 is exposed (FIG. 28).

Thereafter, the trench 4 is formed by using the selective growth method.
From the storage electrode 6 exposed inside the semiconductor layer 11
6 and a semiconductor layer 116 ′ is grown from the semiconductor substrate 1 exposed on the upper side surface of the trench 4. At this time, the growth is performed so that the storage electrode 116 grown from the storage electrode 6 and the storage electrode 116 'grown from the semiconductor substrate 1 are connected (FIG. 29).

At this time, for example, after removing the resist film 45, a polycrystalline silicon film is deposited, and the upper surface of the polycrystalline silicon film is removed from the upper surface of the insulating film 12 formed on the side surface of the trench 4 by an etch-back method. It is also possible to form the storage electrode 116 by etching such that the polycrystalline silicon film is left only inside the trench 4 by performing etching so as to be lower. In this case, after forming the storage electrode 116, the semiconductor layer is selectively grown.

Next, an insulating film 117 is deposited, and the insulating film 117 is etched by an etch-back method.
The insulating film 117 is left so that the insulating film 117 and a part of the storage electrode 116 'are covered. At this time, the insulating film 12 and the insulating film 1
In the case where the materials of 17 are the same, a part of the insulating film 12 is etched as shown in FIG. Furthermore, mask material 1
13 and 114 are removed.

Thereafter, an n-type diffusion layer 9 is formed by ion implantation of, for example, arsenic or phosphorus at 10 ¹³ to 10 ¹⁷ cm ⁻² , and the n-type diffusion layer 9 and the p-type storage electrode 116 ′ are formed.
To form a pn junction. At this time, as shown in FIG. 31, the pn junction needs to be formed at a position lower than the upper surface of the insulating film 12 in order to prevent conduction between the substrate 1 and the storage electrode 6. That is, the n-type diffusion layer 9 needs to be diffused deeper than the upper surface of the insulating film 12. In addition, since this pn junction forms a diode with a gate together with a gate electrode formed on the side surface of the storage electrode 116 ′ via a gate insulating film in a later step, the pn junction is formed inside the storage electrode 116 ′. There is a need to. That is, the n-type diffusion layer 9 includes the storage electrode 116 ′ and the storage electrode 116.
Must not be diffused deeper than the interface with.

Then, the insulating film 117 is removed.

Thereafter, as shown in FIG. 32, the exposed semiconductor substrate 1 and the semiconductor layers 116 and 116 'are oxidized to form a gate oxide film 7 having a thickness of, for example, 3 nm to 100 nm. A polycrystalline silicon film having a thickness of 50 nm to 400 nm is deposited and, for example, POCl _{3 is} diffused to reduce the resistance. Further, after depositing an insulating film 36 such as a silicon nitride film, the insulating film 36 and the polycrystalline silicon film are processed by using a lithography method and a reactive ion etching technique to form the gate electrode 8. Further, the bit line contact hole region to form an opening resist film, for example, arsenic or phosphorus 10 ¹³ 10 ¹⁷ c
By implanting m ^-2 ions, the impurity concentration of the n-type diffusion layer 9 can be increased.

Next, an insulating film 37 of, for example, silicon nitride is deposited, and the insulating film 37 is etched by anisotropic etching to expose the gate insulating film 7 and leave the insulating film 37 on the side wall of the gate electrode 8. The side wall insulating film 3 of the gate electrode 8
7 is formed. Since the side wall insulating film 37 and the insulating film 36 have a structure covering the gate electrode 8, a short circuit between the bit line 13 formed later and the gate electrode 8 can be easily prevented. Thereafter, in order to reduce the connection resistance between the bit line 13 and the n-type diffusion layer 9, an impurity such as arsenic can be further added to the diffusion layer 9 by, for example, an ion implantation method.

Next, after depositing the interlayer insulating film 38, the bit line connection hole 11 is formed by, for example, lithography and reactive ion etching. Thereafter, a bit line material such as a polycrystalline silicon film is deposited, and the bit line 13 is processed by, for example, a lithography method and a reactive ion etching technique, thereby completing a memory cell as shown in FIG.

If necessary, an upper wiring layer is formed by a normal integrated circuit manufacturing method to complete a semiconductor memory device.

The sixth embodiment has the following features in addition to the features of the first embodiment.

That is, the depth of the diode junction of the diode with a gate is controlled by the depth of the etch back of the insulating film 117 serving as a mask material for ion implantation for forming the junction, the depth of the ion implantation, and the thermal diffusion step. And also
The burying depth of the gate electrode 8 formed inside the trench 4 is controlled by adjusting the burying depth of the storage electrode 116. For this reason, the gated diode according to the present embodiment has a structure that does not depend on the planar dimensional accuracy of the lithography technique. Therefore, even if the plane area of the memory cell is reduced, it is possible to secure a sufficient bonding area, so that the memory cell is miniaturized,
The semiconductor memory device can be highly integrated.

Further, with a structure having a sufficient junction area, it is possible to reduce the variation of the junction current among a plurality of memory cells, and to prevent the malfunction of the semiconductor memory device due to the variation.

In the first embodiment, when forming the n-type diffusion layer 9 before forming the gate electrode,
A lithography process for an n-type diffusion layer is required,
The number of steps increases. In addition, alignment accuracy between the pattern of the gate electrode and the pattern of the n-type diffusion layer is required, which may hinder miniaturization of the memory cell.
However, according to the present embodiment, since the junction is formed not in the plane direction but in the depth direction, the lithography step for forming the n-type diffusion layer becomes unnecessary, and the above problem does not occur.

Further, the steps after the formation of the gate electrode 8 are the same as the steps for forming the planar transistor except for the ion implantation step for forming the source or drain diffusion layer. A planar transistor used for a peripheral circuit or the like can be formed at the same time, and the process can be simplified.

Next, as a seventh embodiment of the present invention,
A memory cell in which the bit line connection hole, the gate electrode, and the storage electrode connection hole formed adjacent to each other in the horizontal direction in the above-described fifth embodiment are configured in the vertical direction, and the plane area can be reduced. The structure will be described with reference to FIGS. FIG. 33 is a plan view of the memory cell structure according to the present embodiment, and FIGS. 34A and 34B are cross-sectional views taken along the lines AA ′ and BB ′ of FIG. 32, respectively. In this embodiment mode, a plurality of memory cells are formed. However, it is not always necessary to form them in the arrangement shown in the drawing, and they can be implemented independently. 1 and 2 are denoted by the same reference numerals, and detailed description is omitted.

The memory cell according to the present embodiment is composed of a diode with a gate and a capacitor, similarly to the fifth embodiment. The capacitor includes a storage electrode 6, a capacitor insulating film 5, and a plate electrode 10. One electrode of the gate electrode is connected to the storage electrode 6 of the capacitor, and the other electrode is connected to the bit line.
In the present embodiment, as shown in FIG. 34, unlike the fifth embodiment, the bit line 13 is formed on the insulating film 92, and the p-type semiconductor layer 12 is formed on the bit line 13 in a columnar shape.
1 is formed. An n ⁺ diffusion layer 9 connected to the bit line 13 is formed on one side surface of the p-type semiconductor layer 121, and a pillar is formed so as to be in contact with the junction between the n ⁺ diffusion layer 9 and the p-type semiconductor layer 121. The gate electrode 8 is formed on the side surface of the substrate with a gate insulating film 7 interposed therebetween. This junction and the gate electrode 8
Thus, a diode with a gate is formed. further,
The storage electrode 6 is formed on the columnar semiconductor layer 121 so as to be connected on the upper surface, and the storage electrode 6, the capacitor insulating film 5, and the plate electrode 10 form a capacitor.

As described above, the present embodiment is the same as the fifth embodiment.
As compared with the embodiment, the gate insulating film 7 of the gated diode is not formed on the main plane of the semiconductor but is formed on the side surface of the columnar p-type semiconductor layer 121. Are different in that a junction with a gate is formed by laminating them, and that a storage electrode connection hole is formed above the diode with a gate. Further, as in the fifth embodiment, in this embodiment, a memory cell having a stacked MIS capacitor structure is used in order to improve the capacity of the cell capacitor.

Hereinafter, a method for manufacturing a semiconductor device according to the seventh embodiment of the present invention will be described with reference to FIGS. In the figure, (a) is a plan view, (b) is A- of FIG.
A sectional view corresponding to the A ′ section is shown.

First, as in the fifth embodiment, an SOI substrate including the semiconductor substrate 1, the insulating layer 92, and the semiconductor layer 120 is used. The thickness of the semiconductor layer 120 is, for example, between 0.1 and 3 μm, and is, for example, n such as phosphorus or arsenic.
Type impurity from 10 ¹⁸ to 10 ²⁰ cm ^-3 on the ^{n +} -type region 13 containing, for example, a p-type impurity such as boron from 10 ¹⁵ 1
A p-type region 121 containing 0 ¹⁹ cm ⁻³ is formed.
The n ⁺ -type region 13 may be formed by, for example, ion-implanting an n-type impurity such as P or As accelerated to 100 KeV to 10 MeV into a p-type semiconductor layer to which a p-type impurity is added, It may be formed by epitaxially growing a p-type semiconductor in n ⁺ -type region 13. The thickness of the n ⁺ type region 13 is, for example, 0.0
The thickness is 5 to 0.5 μm.

Next, the semiconductor layer 120 is patterned along the word line direction and etched to form a groove as shown in FIG. Etching is performed on the n ⁺ type region 1
3 until the insulating layer 92 is reached.

Next, an insulating film 122 made of, for example, PSG or AsSG is deposited, etched back, and left inside the groove so that the height of the surface is in the middle of the p-type region 121. Further, as shown in FIG. 36, the resist film 123 is patterned in the word line direction so as to cover a part of the insulating film 122 remaining inside the groove.

Subsequently, the insulating film 122 is etched to form the p-type semiconductor region 121 as shown in FIG.
The insulating film 122 is left only on one side surface of. Next, for example, a heat treatment is performed in a nitrogen atmosphere at a temperature of 900 to 1100 ° C. for 5 to 120 seconds, so that the insulating film 122 is formed.
Is diffused into the P-type semiconductor region 121 to form the n ⁺ -type region 9 on one side of the semiconductor region 121.

Next, the insulating film 122 is removed by etching with, for example, an ammonium fluoride solution. Further, as shown in FIG. 38, the bit line 13 is formed by patterning the bit line and etching the n-type semiconductor region 13 until the insulating film 92 is exposed. As shown in FIG. 37, the bit line pattern is preferably formed in a direction perpendicular to the word line in order to reduce the area of the memory cell. Further, an embedded element isolation 124 is formed by embedding the insulating film 124 inside the groove. FIG. 39A is a sectional view taken along line AA ′ of FIG.
FIG. 9B is a sectional view taken along the line BB ′ of FIG. As shown in this figure, the insulating film 12 is formed such that the surface height of the insulating film 124 is lower than the highest position of the n ⁺ type diffusion layer region 9.
Adjust the embedding depth to 4. Further, it is desirable that the insulating film 124 be formed higher than the bit line 13 in order to reduce the capacitive coupling between the gate electrode 8 formed on the insulating film 124 and the bit line 13 later.

Thereafter, a gate insulating film 7 made of, for example, a silicon oxide film is formed by deposition or oxidation to a thickness of, for example, 3 nm to 100 nm, and a polycrystalline silicon film 8 having a thickness of, for example, 50 nm to 400 nm is formed as a gate electrode material. Is deposited, and POCl _{3 is} diffused, for example, to reduce the resistance. Further, an insulating film 36 such as a silicon nitride film is deposited on the polycrystalline silicon film 8. (A) and (b) of FIG.
9 is a cross-sectional view corresponding to FIGS. 9A and 9B. FIG.

Next, for example, using a lithography method,
As shown in FIG. 41, patterning of the word line is performed,
For example, the insulating film 36 is formed by a reactive ion etching technique.
Then, the gate electrode 8 is formed by processing the polycrystalline silicon film. Further, an insulating film 3 such as a silicon nitride film
7, the insulating film 37 is removed by etching, for example, by an anisotropic etching technique to expose the gate insulating film 7 and leave the insulating film 37 on the side wall of the gate electrode 8.
A gate sidewall insulating film is formed. 42A is a cross-sectional view taken along the line AA ′ of FIG. 41, and FIG.
It is B 'sectional drawing. . In this manner, the insulating films 36 and 37 surround the gate electrode 8, and it becomes easy to maintain electrical insulation between the storage electrode 6 and the gate electrode 8, which are formed later.

Further, an insulating film 125 is deposited, and a storage electrode connection hole is formed on the upper surface of the columnar semiconductor layer 121 by using, for example, a lithography method and an etching technique. Thereafter, the p ⁺ diffusion layer region 126 is formed by ion implantation of, for example, B or BF ₂ at about 10 ^{12 to} 10 ¹⁷ cm ⁻² , and the resistance between the storage electrode and the p-type semiconductor layer 121 may be reduced. It is possible.

Next, for example, a polycrystalline silicon film is deposited to a thickness of, for example, 100 to 400 nm, and the polycrystalline silicon film is processed by using a lithography method and an etching technique to form the storage electrode 6. Here, for example, B or BF ₂
By implanting ions of about 10 ¹² to 10 ¹⁷ cm ^-2 , the resistance of the storage electrode 6 can be reduced. Further, on the storage electrode 6, a capacitor insulating film 5 composed of, for example, a stacked film of silicon oxide film / silicon nitride film / silicon oxide film (effective thickness 10 nm) is formed, and then, for example, a polycrystalline silicon film 15 is deposited. Thereafter, the resistance of the polycrystalline silicon film 15 is reduced by, for example, diffusing arsenic, phosphorus, boron, or the like, and the polycrystalline silicon film 15 is processed by, for example, a lithography method and an etching technique to complete a memory cell ( (FIG. 34).

As described above, the seventh embodiment of the present invention has the following features in addition to the features of the above-described fifth embodiment.

First, since the bit line contact is formed below the pn junction with a gate and the storage electrode connection hole is formed above the pn junction with a gate, the area is smaller than that of the structure according to the fifth embodiment. Can be greatly reduced.

The position of the pn junction is determined by the BPSG film 122 remaining inside the groove for forming the n-type diffusion layer 9.
And is not affected by lithography patterning. Therefore, the patterning of the bit line connection hole or the storage electrode connection hole does not need to consider the alignment accuracy with the pn junction, and the burden on the lithography technique is reduced.

Further, the bit line 13 and the storage electrode 6
The diodes are opposed to each other with the gated diode interposed therebetween, and the distance between them can be increased by increasing the height of the columnar semiconductor layer 121. Therefore, a short circuit between the bit line 13 and the storage electrode 6 can be easily performed. Can be prevented.

The present invention is not limited to the above embodiments.

In a modification of the first embodiment,
A groove for forming an element isolation region is formed in the semiconductor substrate 1 by etching. After selectively oxidizing the element isolation region by a selective oxidation method and removing an oxidation mask material, the oxidation is performed using, for example, NH4F or the like. By removing the film,
Grooves can also be formed.

In the first to seventh embodiments, various insulating films used can be formed by the following various methods. For example, an oxide film is formed by thermal oxidation, oxygen is implanted into silicon or the like at a low acceleration energy of, for example, about 30 keV, an insulating film such as an oxide film, a silicon nitride film is deposited, or a combination thereof is used. It is also possible to form

For example, a method other than a method of converting silicon to a silicon oxide film or a silicon nitride film, such as a method of depositing silicon and implanting oxygen ions, or a method of depositing silicon and oxidizing Can be used.

As the insulating film, a tantalum oxide film, a ferroelectric film such as strontium titanate, barium titanate, or lead zirconium titanate, a monolayer film of a paraelectric film, or a composite film thereof can be used. .

Further, in the first to seventh embodiments, the case where the selective oxidation method is used to form the element isolation insulating film 12 is mainly shown, but a finer element isolation region is formed. Other element isolation methods such as a selective oxidation method improved for the above purpose, a trench isolation method described in the modification of the first embodiment, and a field shield isolation method using a conductive film to which a potential is applied instead of an insulating film , Or a combination thereof.

In the first to seventh embodiments, the case where a semiconductor element is formed on the p-type Si substrate 1 or the SOI substrate has been described. Instead, for example, an n-type Si substrate, a GaAs substrate, an InP It is possible to use a semiconductor substrate such as a substrate and a substrate having a stacked structure of these and an insulating layer.

Further, in the first to seventh embodiments, the p-type polycrystalline silicon film into which boron is ion-implanted is used as the plate electrode 15 and the storage electrode 6, but, for example, BSG (boron containing boron) is used. It can also be added by solid phase diffusion from a (oxidized film). Further, boron can be added simultaneously with the deposition of the polycrystalline silicon film. Further, instead of the deposited polycrystalline silicon film, a silicon film formed by an epitaxial growth method, a selective growth method, or the like can be used, and boron ions can be implanted into the silicon film or boron can be added during growth. . Further, the impurity to be added is not limited to boron, and may be any impurity having p-type conductivity.

Also, an n-type polycrystalline silicon film can be formed by adding an n-type conductive impurity such as arsenic, phosphorus, and antimony to the polycrystalline silicon film used as the plate electrode 15 and the storage electrode 6. . At this time, as shown in FIG. 9, the diffusion layer connected to the bit line 13 is made p-type,
It is necessary to use an n-type substrate and to reverse the polarity of the voltage applied to each terminal.

Further, the plate electrode 15, the storage electrode 6, the n-type diffusion layer 9, and the gate electrode 8 are made of single-crystal silicon other than polycrystalline silicon, porous silicon, amorphous silicon, SiGe mixed crystal, SiC mixed crystal, GaAs, W ,
Metals of Ta, Ti, Hf, Co, Pt, Pd or silicides thereof can also be used. Further, it is also possible to adopt a laminated structure of these.

As described above, in the first to seventh embodiments, the second electrode connected to the bit line has n
Although the p-type semiconductor is used for the third electrode connected to the storage electrode 6, the p-type semiconductor may be used for the second electrode and the n-type semiconductor may be used for the third electrode.

Further, the voltage-current characteristics of the second electrode (n-type diffusion layer 9) and the third electrode (p-type storage electrode 51) have a rectifying property, and the voltage between the second electrode and the third electrode is high. Is in the first voltage range (forward bias), a current flows between the second electrode and the third electrode without depending on the potential of the first electrode (gate electrode 8), and the second voltage In the range, a semiconductor having three terminals capable of changing a current flowing between the second electrode and the third electrode by changing a voltage between the first electrode and the second electrode. As long as the device is a device, the present invention can be implemented using a semiconductor device other than a diode with a gate.

For example, as shown in FIG. 14, the second electrode 16 is made of a metal such as Ta, Ti, Hf, Co, Pt, and Pd.
Alternatively, a Schottky diode with a gate in which the third electrode 1 is formed of a semiconductor and a metal made of the silicide can be used.

Also, '95 IEDM. Technical Digest p
p.645-648 J.P. H. In the SOI device shown by Choi et al., An element using a tunnel phenomenon between a surface electron channel and a hole channel on the buried oxide film interface side or an element based on another phenomenon can be used.

In addition, various modifications can be made without departing from the spirit of the present invention.

[0192]

As described above, in the semiconductor memory device according to the present invention, the distance between the storage electrode and the electrode connected to the bit line is reduced by using the switch element having the structure for preventing punch-through. Thus, it is possible to provide a semiconductor memory device in which a fine memory cell is formed and which can achieve higher density.

Also, a random accessible circuit can be constructed by combining a plurality of the above memory cells and adding only one simultaneous erase line to the conventional DRAM circuit configuration.

Further, the semiconductor memory device described above can be easily manufactured by the manufacturing method according to the present invention.

[Brief description of the drawings]

FIGS. 1A and 1B are a plan view and a cross-sectional view illustrating a structure of a semiconductor memory device according to a first embodiment;

FIG. 2 is a process sectional view illustrating the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIGS. 3A and 3B are a plan view and a cross-sectional view, respectively, showing a structure of the semiconductor memory device according to the first embodiment;

FIG. 4 is a process sectional view illustrating the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 5 is a diagram illustrating the operation principle of the semiconductor memory device according to the present invention.

FIG. 6 is a circuit configuration diagram of a semiconductor memory device according to the present invention.

FIG. 7 is a circuit configuration diagram of a semiconductor memory device according to the present invention.

FIG. 8 is a circuit diagram illustrating the operation principle of a semiconductor memory device according to the present invention.

FIG. 9 is a circuit diagram illustrating the operation principle of a semiconductor memory device according to the present invention.

FIG. 10 is a diagram showing a timing chart of the semiconductor memory device according to the present invention.

FIG. 11 is a diagram showing a timing chart of the semiconductor memory device according to the present invention.

FIG. 12 is a diagram showing a timing chart of the semiconductor memory device according to the present invention.

FIG. 13 is a sectional view showing another example of the semiconductor memory device according to the present invention.

FIG. 14 is a sectional view showing another example of the semiconductor memory device according to the present invention.

FIGS. 15A and 15B are a plan view and a cross-sectional view illustrating a structure of a semiconductor memory device according to a second embodiment;

FIG. 16 is a sectional view showing another structure of the semiconductor memory device according to the second embodiment;

FIGS. 17A and 17B are a plan view and a cross-sectional view illustrating a structure of a semiconductor memory device according to a third embodiment;

FIG. 18 is a process sectional view illustrating the method for manufacturing the semiconductor memory device according to the third embodiment of the present invention.

FIG. 19 is a plan view and a cross-sectional view illustrating another structure of the semiconductor memory device according to the third embodiment of the present invention.

FIG. 20 is a plan view and a cross-sectional view illustrating another structure of the semiconductor memory device according to the third embodiment of the present invention.

FIGS. 21A and 21B are a plan view and a cross-sectional view illustrating a structure of a semiconductor memory device according to a fourth embodiment;

FIGS. 22A and 22B are a plan view and a cross-sectional view illustrating a structure of a semiconductor memory device according to a fifth embodiment;

FIGS. 23A and 23B are a plan view and a cross-sectional view illustrating a structure of a semiconductor memory device according to a sixth embodiment;

FIGS. 24A and 24B are a plan view and a sectional view showing the method for manufacturing the semiconductor memory device according to the sixth embodiment; FIGS.

FIGS. 25A and 25B are a plan view and a cross-sectional view illustrating the method for manufacturing the semiconductor storage device according to the sixth embodiment; FIGS.

FIGS. 26A and 26B are a plan view and a cross-sectional view illustrating the method for manufacturing the semiconductor memory device according to the sixth embodiment; FIGS.

FIGS. 27A and 27B are a plan view and a sectional view illustrating the method for manufacturing the semiconductor memory device according to the sixth embodiment; FIGS.

FIGS. 28A and 28B are a plan view and a sectional view illustrating the method for manufacturing the semiconductor memory device according to the sixth embodiment; FIGS.

FIGS. 29A and 29B are a plan view and a cross-sectional view illustrating the method for manufacturing the semiconductor memory device according to the sixth embodiment; FIGS.

FIGS. 30A and 30B are a plan view and a sectional view showing the method for manufacturing the semiconductor memory device according to the sixth embodiment; FIGS.

FIG. 31 is a plan view and a cross-sectional view illustrating the method for manufacturing the semiconductor memory device according to the sixth embodiment;

FIGS. 32A and 32B are a plan view and a cross-sectional view illustrating the method for manufacturing the semiconductor memory device according to the sixth embodiment;

FIG. 33 is a plan view showing a structure of a semiconductor memory device according to a seventh embodiment;

FIG. 34 is a sectional view showing the structure of the semiconductor memory device according to the seventh embodiment;

FIG. 35 is a plan view and a cross-sectional view illustrating the method for manufacturing the semiconductor memory device according to the seventh embodiment of the present invention.

FIG. 36 is a plan view and a cross-sectional view illustrating the method for manufacturing the semiconductor storage device according to the seventh embodiment;

FIG. 37 is a plan view and a cross-sectional view illustrating the method for manufacturing the semiconductor storage device according to the seventh embodiment of the present invention;

FIG. 38 is a plan view illustrating the method for manufacturing the semiconductor memory device according to the seventh embodiment of the present invention.

FIG. 39 is a sectional view showing the method of manufacturing the semiconductor memory device according to the seventh embodiment;

FIG. 40 is a sectional view showing the method of manufacturing the semiconductor memory device according to the seventh embodiment of the present invention.

FIG. 41 is a plan view showing the method for manufacturing the semiconductor memory device according to the seventh embodiment of the present invention.

FIG. 42 is a sectional view showing the method of manufacturing the semiconductor memory device according to the seventh embodiment;

FIG. 43 is a plan view and a cross-sectional view illustrating a structure of a conventional semiconductor memory device.

[Explanation of symbols]

1, 61, 71, 81, 91: semiconductor substrate, 4: trench, 5: capacitor insulating film, 6, 6 ', 73, 76 ... storage electrode, 7: gate insulating film, 8: gate electrode, 9, 9' , 126: diffusion layer, 10: plate electrode, 11: bit line connection hole, 12, 22, 41: element isolation insulating film, 13: bit line, 16, 93: semiconductor layer, 17: metal, 31: epitaxial growth layer, 36, 37, 94, 95, 111, 113, 114, 1
15, 117, 122, 124, 125 ... insulating film, 38, 96, 97 ... interlayer insulating film, 45, 123 ... resist film, 51 ... p-type diffusion layer, 52 ... simultaneous erase line, 53 ... sense amplifier, 54 ... "0" write control line, 55: bipolar transistor, 62, 72, 82, 92 ... insulating layer, 116, 116 ', 120, 121 ... semiconductor layer

Claims (10)

[Claims] 1. A first electrode region and a second electrode region separated by a rectifying junction formed on a surface of a semiconductor substrate.
A switch element having an electrode region and a gate electrode formed via a gate insulating film on the substrate surface located at the edge of this junction; and a capacitor having a storage electrode, a capacitor insulating film, and a plate electrode. A semiconductor memory device comprising: a first electrode region of the switch element; and a storage electrode of the capacitor. 2. The semiconductor memory device according to claim 1, wherein said junction is a pn junction or a Schottky junction. 3. The storage electrode of the capacitor is embedded in a groove formed in the semiconductor substrate, the capacitor insulating film is formed on a wall surface of the groove, and the plate electrode is formed by the semiconductor substrate. 3. The semiconductor memory device according to claim 1, wherein an edge portion exposed on a substrate surface of the junction and at least a part of said gate electrode are formed above said groove. 4. The semiconductor substrate according to claim 1, wherein the semiconductor substrate has an insulating layer on a surface thereof and a semiconductor layer formed on the insulating layer, and the junction of the switch element is formed on the semiconductor layer. Semiconductor storage device. 5. A first semiconductor layer forming a bit line on an insulating layer formed on a semiconductor substrate, and a side wall surface region of a second semiconductor layer formed in a column on the first semiconductor layer. A first electrode region and a second electrode region separated by a rectifying junction formed so that an edge thereof is exposed to a side wall surface at a part of the second electrode region and the second electrode region located at an edge of the junction. A switching element having a gate electrode formed on the side wall surface of the semiconductor layer with a gate insulating film interposed therebetween, and a capacitor having a storage electrode, a capacitor insulating film, and a plate electrode; And the storage electrode of the capacitor are connected on the upper surface of the second semiconductor layer, and the second electrode region of the switch element is connected to the first semiconductor layer. Semiconductor memory apparatus. 6. A first electrode region and a second electrode region separated by a rectifying junction formed on a surface of a semiconductor substrate.
A switch element having an electrode region and a gate electrode formed via a gate insulating film on the substrate surface located at the edge of this junction; and a capacitor having a storage electrode, a capacitor insulating film, and a plate electrode. A semiconductor memory element, wherein the first electrode area of the switch element is connected to a storage electrode of the capacitor, and a plurality of the semiconductor memory elements are connected via a second electrode area of the switch element And a current flowing between the first and second electrode regions of the switch element is controlled by a voltage applied to the gate electrode. 7. A first switch element having three electrodes, a capacitor having a storage electrode and a plate electrode, and a first electrode of the first switch element is connected to the storage electrode. A semiconductor storage element, a first conductive wiring in which the plurality of semiconductor storage elements are connected via a second electrode of the switch element, and a second switch element connected to the first conductive wiring A second conductive wiring in which a plurality of the first conductive wirings are connected via the second switch element; and a sense amplifier for detecting a potential of the first conductive wiring. A voltage-current characteristic of a first electrode and a second electrode of the first switch element has a rectifying property, and when the voltage between the first and second electrodes is reverse-biased, the second electrode And a third electrode of the first switch element By changing a voltage, a current flowing between the first electrode and the second electrode is changed, and a potential at which a voltage between the first and second electrodes becomes a forward bias is changed to the second conductive property. A semiconductor memory device, wherein charges are simultaneously injected into storage electrodes of the capacitors of a plurality of semiconductor memory elements selected by the second switch element by applying a voltage to a wiring. 8. A first switch element having three electrodes, and a capacitor having a storage electrode and a plate electrode, wherein a first electrode of the first switch element is connected to the storage electrode. A semiconductor storage element, a conductive wiring in which the plurality of semiconductor storage elements are connected via a second electrode of the switch element, and a sense amplifier for detecting a potential of the conductive wiring; The voltage and current characteristics of the first electrode and the second electrode of the switch element have a rectifying property, and when the voltage between the first and second electrodes is reverse-biased, the second electrode and the first electrode Of the third switch element
The current flowing between the first electrode and the second electrode is changed by changing the voltage between the first and second electrodes. When the potential of the storage electrode is equal to or higher than V _{0 and} lower than V ₂ + Va, the first voltage is applied. State, the potential of the storage electrode is V ₂ + Va or more and V ₁ + Va
When the case where the voltage is less than −V ₂ is set to the second state, T is the time for applying V ₁ to the third electrode until the second state is reached, I
current flowing _d1 between the first and second electrodes upon application of a V ₁ to said third electrode, said first and second at the time of applying the V ₂ to the third electrode I _d2 Where Cs is the capacitance of the capacitor, Cb is the capacitance of the conductive wiring, Va is an arbitrary potential, and n is the number of memory cells connected in parallel to the conductive wiring.
V ₀ , V ₁ , and V ₂ are T × I _d1 ≧ Cs × (V ₁ + Va−V ₀ ) T × I _d2 << Cs × (V ₂ + Va−V ₀ ) V ₀ ≦ V ₂ + Va Cs / (Cs + Cb) × (V ₂ + Va) ≦ V ₁ −V ₂ n ≦ I _d1 / I _d2 9. A step of forming a capacitor having a storage electrode, a capacitor insulating film, and a plate electrode in a semiconductor substrate, and a step of forming a semiconductor layer having a first conductivity type so as to be connected to the storage electrode. Forming a gate insulating film on the surface of the semiconductor layer; forming a gate electrode on the gate insulating film so as to cover at least a part of the semiconductor layer; Forming a diffusion layer or a conductive layer having a second conductivity type such that a junction with the semiconductor layer having the first conductivity type is formed at a position facing the gate electrode; A method for manufacturing a semiconductor memory device, comprising: forming a film; and forming a conductive wiring connected to the second diffusion layer or the conductive layer. 10. A step of forming a diffusion layer or a conductive layer having a second conductivity type on a surface of a semiconductor layer having a first conductivity type, and forming the semiconductor layer having the first conductivity type and the second conductivity type.
Forming a gate electrode via a gate insulating film on the surface of the semiconductor layer where the edge of the junction between the diffusion layer having the conductivity type or the conductive layer is located, and forming an insulating film covering the gate electrode Forming a semiconductor layer having the first conductivity type or a diffusion layer having the second conductivity type or a storage electrode connected to the conductive layer; and forming a capacitor insulating film on the surface of the storage electrode. Forming a plate electrode through the intermediary of the semiconductor memory device.