JPH1093401A - Clock frequency multiplying circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain the clock frequency multiplying circuit not needing a fixed oscillator. SOLUTION: A NAND gate 12 provides an output of '0' when an input clock CLK is at '1' and the inverse of Q output of a flip-flop 5 via a delay adjustment circuit 9 is at '1'. A NAND gate 13 provides an output of '0' when the input clock CLK is at '0' and the inverse of Q output of a flip-flop 6 via a delay adjustment circuit 11 is at '1'. Similarly, a pulse is generated to an output CLKOUT of a NAND gate 16 for every rise and fall of the input clock CLK and the frequency is twice that of the frequency of the input clock CLK.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock frequency multiplying circuit, and more particularly to a clock frequency multiplying circuit for generating an output clock having a frequency twice the frequency of an input clock.

[0002]

2. Description of the Related Art Japanese Patent Application Laid-Open No. Sho 60-142623 discloses a technique of digitizing a conventional circuit of this kind.
FIG. 3 shows an example of the circuit and FIG. 4 shows an example of the operation timing waveform.

[0003] The circuit shown in FIG.
, A fixed oscillator 1 that generates a basic clock S1 that is an integral multiple of the basic frequency of the input clock, and a plurality of flip-flops F1 to F6.
And a plurality of gate circuits G1 to G11, and a cyclic shift register circuit 3 in which specific signal bits are cyclically shifted in synchronization with the basic clock.

Here, the gate circuit is incorporated so as to receive the output of the change point detection circuit 2 and control the shift destination of the information between the flip-flops. A loop for delaying a shift of a specific signal bit by a predetermined flip-flop according to a relationship with an output timing of the change point detection circuit 2;
A loop for bypassing a predetermined flip-flop and advancing the shift of a specific signal bit is formed.

The circuit of FIG. 3 operates at a speed six times the fundamental frequency of the input clock φIN, as shown in the waveform example of FIG.

In FIG. 3, a fixed oscillator 1 outputs a basic clock S1 having a frequency six times the basic frequency of an input clock φIN, such as a data stream. The circuit shown in FIG. 3 operates in synchronization with the basic clock S1.

The input clock φIN is applied to a change point detection circuit 2. As shown in FIG. 4, the edge signal S2 is output from the change point detection circuit 2 in response to both the rising and falling transition points of the input clock φIN. This edge signal S2 is
This is a pulse signal having a width equal to the period of the basic clock S1.

The cyclic shift register circuit 3 has six D-type flip-flops F1 to F6 and OR gates G1 and G
4, G11 and AND gates G2, G5, G7, G9
And NOR gates G3, G6, G8, and G10, and operates by receiving the basic clock S1 and the output S2 of the change point detection circuit 2 to generate an output clock φOUT.

Only one of the six flip-flops F1 to F6 is set, and the "1" bit cyclically shifts in the loop in synchronization with the basic clock S1. However, the above-mentioned loop is not constant, but changes as follows, and the phase tracking process is performed.

The main loop of the cyclic shift register circuit 3 is 6
The flip-flops F1 to F6 are all in a ring-connected state, and usually operate in that state. In this case, the basic clock S1 is frequency-divided by 1/6 in the circuit 3, and the frequency-divided signal is taken out from the fourth flip-flop F4 as the output clock φOUT.

While the output S2 (edge signal S2) of the change point detection circuit 2 is "0", the cyclic shift register circuit 3 operates in the above-mentioned main loop and is in a state where the current phase is held. . When the first-stage flip-flop F1 is set when the edge signal S2 becomes "1" (point A in FIG. 4), the main loop of the cyclic shift register circuit 3 is maintained, and the phase change Absent. When the cyclic shift is performed while maintaining this state, the phase of the circuit 3 is synchronized with the input clock φIN.

Unlike the above state, when the edge signal S2 becomes "1", the flip-flops F of the second to sixth stages are set.
Any one of 2 to F6 is set in this circuit 3
Is not synchronized with the input clock φIN.

When S2 = "1", flip-flop F2
Is set when the phase of the input clock φIN is delayed by 1/6 from the phase of the circuit 3 (point B in FIG. 4). In this case, the gate G3 is turned off when S2 = "1", and the set state of the flip-flop F2 is not transmitted to the next-stage flip-flop F3. Instead, the input D of the flip-flop F2 itself via the gates G2 and G1.
Will be returned to

That is, the main loop of the circuit 3 is temporarily cut off,
A self-delay loop connecting the input and output of the flip-flop F2 is formed. As a result, the shift operation of the circuit 3 is delayed by one cycle of the basic clock S1, and the phase of the circuit 3 (that is, the phase of the output clock φOUT) is changed to the input clock φIN.
To follow.

When S2 = "1", flip-flop F3
Is set in a state where the phase of the input clock φIN is delayed from the phase of the circuit 3 in the same manner as described above. In this case, the main loop connecting the flip-flops F3 and F4 is temporarily cut off by the gates G4, G5 and G6, and a self-delay loop connecting the input and output of the flip-flop F3 itself is formed, and the shift operation of the circuit 3 is delayed. .

When S2 = "1", flip-flop F6
Is set when the phase of the input clock φIN is 1/6 ahead of the phase of the circuit 3 (point C in FIG. 4). In this case, when S2 = "1", the gate G10 is turned off, and the set state of the flip-flop F6 is not transmitted to the next-stage flip-flop F1. Instead, the gate G9 is turned on, and the output Q =
“1” is input to the next-stage flip-flop F2 via the gates G9 and G1.

That is, a bi-pulse loop bypassing the flip-flop F1 is formed. As a result, the shift operation of the circuit 3 is advanced by one cycle of the basic clock S1. In this process, the phase of the output clock φOUT follows the input clock φIN.

When S2 = "1", flip-flop F5
Is set when the phase of the input clock φIN is ahead of the phase of the circuit 3 in the same manner as described above. In this case, the operation of the gates G7, G8, and G11 forms a bypass loop that bypasses the flip-flop F6 and connects the flip-flops F5 and F1. Therefore, the shift operation of this circuit is hastened, and the output clock φ
The phase of OUT follows the input clock φIN.

The reason why the flip-flop F4 is set when S2 = "1" is that the input clock φ
Assuming that IN noise or the like has occurred, the operation phase of the circuit 3 is not operated, and the current state is maintained. Therefore, flip-flops F4 and F5 are directly connected.

By the above operation, an output clock φOUT synchronized with the input clock φIN is obtained.

[0021]

According to the above configuration,
A digital PLL circuit according to the related art generates and outputs a clock signal having a frequency N times the input clock with reference to a basic clock.

However, this conventional technique has a problem that processing such as phase comparison / phase operation is required, and a basic clock from an oscillator is required for comparison reference in addition to an input clock.

An object of the present invention is to solve the problems of the prior art, the circuit configuration is simple, processing such as phase comparison / phase operation required for the prior art, and basic processing from a comparison reference oscillator are performed. An object of the present invention is to provide a circuit which does not require a clock and directly generates and outputs a clock signal having a frequency twice as high as the input clock from the input clock.

[0024]

According to the present invention, from the timing delayed by one-fourth cycle of the input clock from the rising edge of the input clock, the timing of the first rising edge of the input clock is reduced by one cycle.
A first pulse generating means for generating a pair of first and second pulses complementary to each other until a timing delayed by / 4 cycle, and from a timing delayed by 1/4 cycle with respect to a fall of the clock. A second pulse generating means for generating a pair of third and fourth pulses complementary to each other until the timing delayed by 1/4 cycle with respect to the next fall; There is provided a clock frequency multiplying circuit including a calculating means for performing a logical operation process on a pulse and the clock to generate a clock having a frequency twice as high as the frequency of the clock.

The first pulse generating means delays the D-type flip-flop operating in synchronization with the rising edge of the clock and the normal-phase output and the negative-phase output of the flip-flop by the quarter cycle. At least the first
And first and second delay means for generating a second pulse, wherein the second delay output is a data input of the flip-flop.

The second pulse generating means may include a D-type flip-flop operating in synchronization with the falling edge of the clock, and a positive-phase output and a negative-phase output of the flip-flop, each of which may be a 1/4 cycle. Third and fourth delay means for delaying the third and fourth pulses and providing the fourth delay output as a data input of the flip-flop.

And means for performing a logical AND operation between the delayed output of the first and second delay means and the clock, and a logical product of the delayed output of the third and fourth delay means and an inverted signal of the clock. It is characterized by having means for performing a logical product operation, and means for performing a logical product operation of these operation outputs to obtain a circuit output.

The operation of the present invention will be described below. From the timing delayed by a quarter cycle of the input clock from the rising edge of the input clock, to the timing delayed by a quarter cycle of the next rising edge of the input clock. Generating a pair of first and second pulses, and from a timing delayed by 1/4 cycle from the falling edge of the clock to a timing delayed by 1/4 cycle from the next falling edge. A pair of third and fourth pulses complementary to each other are generated. Then, a logical operation between the first to fourth pulses and the clock is performed to generate a clock having a frequency twice as high as that of the clock.

[0029]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. In FIG. 1, a D-type flip-flop 5 captures a logical value applied to each data (D) input at a rising edge of the input clock CLK, and a D-type flip-flop 6 captures a logical value applied to each data (D) input at a falling edge of the input clock CLK.

The inverter gate 7 receives the input clock CLK.
Invert the phase of I. The delay adjustment circuits 8 to 11 give each of the outputs of the flip-flops 5 and 6 a fixed time delay (for example, a time corresponding to １ ／ of the cycle of the input clock CLK). In the flip-flops 5 and 6, the Q output is initialized to a logical value "0" and the Q output is initialized to a logical value "1" by a reset signal RST bar.

The NAND gate 12 receives the input clock CL
When K is a logical value “1” and the Q bar output of the flip-flop 5 via the delay adjustment circuit 9 is a logical value “1”, a logical value “0” is output. Similarly, the NAND gate 13
When the input clock CLK has the logical value “0” and the bar output of the flip-flop 6 via the delay adjusting circuit 11 has the logical value “1”, the logical value “0” is output.

The NAND gate 14 receives the input clock CL
When K is the logical value “1” and the Q output of the flip-flop 5 via the delay adjustment circuit 8 is the logical value “1”, the logical value “0” is output. Similarly, when the input clock CLK has the logical value “0” and the delay adjustment circuit 1
The Q output of flip-flop 6 via 0 is a logical "1"
At the time, the logic value "0" is output.

The NAND gate 16 is connected to the NAND gate 1
When any one of the outputs 2 to 15 has the logical value “0”, the logical value “1” is output as the output clock CLKOUT.

The outputs of the delay adjusting circuits 9 and 11 are the data inputs of the flip-flops 5 and 6, respectively.

In the waveform diagram of FIG. 2, the reset signal RS
The input clock CLK is input to the flip-flops 5 and 6 while being initialized by T-bar.

At point A in FIG. 2, the input clock CLK
Is "1", the output j of the NAND gate 12 is
Becomes "0", and the output C of the NAND gate 16 becomes
The logical value of LKOUT becomes "1".

At this time, at the first rising edge of the input clock CLK, the flip-flop 5 initializes its own Q
The logic value "1" of the bar output c is taken. Thereafter, after the delay by the delay adjustment circuit 9 (period B in FIG. 2) (C in FIG. 2)
Point), the logical value of the output j of the NAND gate 12 becomes “1”, and the logical value of the output CLKOUT of the NAND gate 16 becomes “0”.

Next, at point D in FIG. 2, since the logical value of the input clock CLK is "0", the logical value of the output k of the NAND gate 13 is "0", and the logical value of the output CLKOUT of the NAND gate 16 is It becomes “1”.

At this time, at the first fall of the input clock CLK, the flip-flop 6 initializes its own Q
The logical value "1" of the bar output g is taken. Thereafter, after the delay by the delay adjustment circuit 11 (period E in FIG. 2) (F in FIG. 2).
Point), the logical value of the output k of the NAND gate 13 is “1”, the logical value of the output CLKOUT of the NAND gate 16 is “1”, and the output CLKOU of the NAND gate 16 is
The logical value of T is "0".

Similarly, a pulse is generated at the output CLKOUT of the NAND gate 16 every time the input clock CLK rises and falls, and its frequency is twice as high as that of the input clock CLK.

Where a is the output of the inverter gate 7,
b and f are the Q outputs of the flip-flops 5 and 6, d, e,
h and i are the outputs of the delay adjustment circuits 8, 9, 10, and 11,
m is the output of the NAND gates 15, 16.

[0043]

As described above, the present invention stably generates a high-speed clock having a double frequency synchronized with the input clock by generating pulses at positions corresponding to the rising and falling edges of the input clock. There is an effect that can be done.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a waveform diagram of the embodiment of the present invention shown in FIG.

FIG. 3 is a circuit diagram showing an example of a conventional clock frequency multiplier.

FIG. 4 is an operation waveform diagram of the circuit shown in FIG. 3;

[Explanation of symbols]

 5, 6 flip-flop 7 inverter gate 8-11 delay adjusting circuit 12-16 NAND gate

Claims (4)

[Claims] A pair of first and second pairs complementary to each other from a timing delayed by 1/4 cycle of the clock with respect to the rising of the input clock to a timing delayed by 1/4 cycle with respect to the next rising. A first pulse generating means for generating a second pulse; a timing from the timing delayed by 1/4 cycle with respect to the falling of the clock to the timing delayed by 1/4 cycle with respect to the next falling; A second pulse generating means for generating a pair of third and fourth pulses complementary to each other, and performing a logical operation process on the first to fourth pulses and the clock to double the frequency of the clock. And a calculating means for generating a clock. 2. The method according to claim 1, wherein the first pulse generating means delays a D-type flip-flop operating in synchronization with a rise of the clock, and outputs a normal-phase output and a negative-phase output of the flip-flop, respectively. 2. The method according to claim 1, further comprising first and second delay means for at least the first and second pulses, wherein the second delay output is a data input of the flip-flop. Clock frequency multiplier. 3. The second pulse generating means includes: a D-type flip-flop operating in synchronization with a falling edge of the clock; and a positive-phase output and a negative-phase output of the flip-flop, each of which has a period of １ ／ cycle. 3. The semiconductor device according to claim 2, further comprising third and fourth delay means for delaying the third and fourth pulses, wherein the fourth delay output is used as a data input of the flip-flop. Clock frequency multiplier circuit. 4. The arithmetic means comprises: means for performing an AND operation between the delayed outputs of the first and second delay means and the clock; and a delay output of the third and fourth delay means and the clock. 4. A clock frequency multiplying circuit according to claim 3, further comprising means for performing a logical product operation with an inverted signal of the above, and means for performing a logical product operation of these operation outputs to obtain a circuit output.