JPH1082840A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that can switch the operating mode without providing a testing terminal and act stably at the time of both normal operation and testing without generating an unstable area even though switching the operating mode. SOLUTION: A first circuit 3 and a second circuit 10 are driven respectively by a first power source 1 and a second power source 2. At the time of normal operation, the second power source 2 is set to operating potential. When an operating mode switching circuit 5 supplies an internal logic circuit 14 with a signal of an input terminal 6 sent through an input buffer 7, operation to be an original object is performed in the internal logic circuit 14, and its result is outputted to an output terminal 8 through a selector 18 and an output buffer 9. At the time of testing, on the other hand, the second power source 2 is set to earth potential. The operating mode switching circuit 5 by-passes the internal logic circuit 14 and sends the output of the input buffer 7 directly to the output buffer 9 through the selector 18 so as to be outputted from the output terminal 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as an LSI (Large Scale Integrated Circuit), and more particularly, to a test mode switching method for performing an operation test of a semiconductor device. .

[0002]

2. Description of the Related Art Conventionally, in testing a semiconductor device, a test pattern is input to the semiconductor device to determine a logical value of an output buffer, and a logic circuit provided inside the device is operated. However, if such a method is adopted, the required test pattern becomes extremely large, such as tens of thousands of patterns, as the circuit size increases, and the test time is also long in proportion to this. Had become. For this reason, in recent years, a technique has been used in which a test terminal is prepared for a semiconductor device, the device is switched to a test mode for testing, and a logic value of an output buffer is determined by bypassing a logic circuit inside the device. ing. Therefore, these methods will be described in detail below.

[First Prior Art] FIG. 7 is a block diagram showing a configuration of a semiconductor device according to a first prior art. This semiconductor device is driven by a first power supply 100 and a ground power supply 101. That is, the first power supply 100 is supplied to the first circuit 102 constituting the semiconductor device via the first power supply wiring 103, and the ground power supply 101 is connected to the first circuit 102 via the ground power supply wiring 104. You.

The semiconductor device has other operation states different from the normal operation state in addition to the normal operation state. To switch between these states, a control signal terminal 105 and a control signal input buffer 106 are provided. In need. Here, the normal operation state is a mode in which the semiconductor device is used for its intended use. On the other hand, another operation state means, for example, a mode for testing a semiconductor device.

[0005] First, the normal operation state is the control signal terminal 10.
5 is the “H” level (high level). In this case, the operation mode switching circuit 107 supplies the logical value given to the input terminal 108 to the internal logic circuit 110 via the input buffer 109, and outputs the operation result to the output terminal 112 via the output buffer 111. I do.

On the other hand, another operation state is when the input signal of the control signal terminal 105 is at "L" level (low level). In this case, the operation mode switching circuit 107
The logical value given to the input terminal 108 is
The data is output to the output terminal 112 via the output buffer 111 without passing through the output buffer 10. And such a switching process,
Based on the output of the control signal input buffer 106 provided via the control signal supply wiring 113, an inverter 114, AND gates 115 to 116, and a selector 117 constituting the operation mode switching circuit 107 are realized.

[Second Prior Art] FIG. 8 is a circuit diagram showing a configuration of a test circuit provided in a semiconductor device according to a second prior art, which is described in Japanese Patent Application Laid-Open No. 63-10538. Things. As shown in the figure, this circuit uses an input terminal used in a normal operation state as a control signal terminal 12.
0, the input buffer 121, the level determination circuits 122 to 123, the inverter 124, and the AND gate 1.
25. Here, the level determination circuit 122,
The threshold voltages of 123 are the potentials VTH and VT shown in FIG.
L is set. And with such a configuration,
An operation waveform as shown in FIG. 9 is obtained.

Now, it is assumed that the test circuit of FIG. 8 is applied to the semiconductor device of FIG. 7 in the first prior art. At this time, the input of “H” level (the potential VD in FIG. 9)
D) is the operating potential of the first power supply 100, and the “L” level input (potential GND in FIG. 9) is the ground potential. Also,
The following waveform is input as the input signal waveform of the control signal terminal 120. That is, when in the normal operation state or another operation state, the level determination circuits 122 and 123
Output the same logical value, and the AND gate 12
5 is set to the “L” level. With this, the operation mode switching circuit 107 is controlled so as to supply the output of the input buffer 121 to the internal logic circuit 110 (FIG. 1).

On the other hand, when the operation mode is switched, the level determination circuits 122 and 123 output "L" level and "H" level, respectively, so that the output of the AND gate 32b becomes "H" level. To With this, the setting of the operation mode switching circuit 107 is changed. Therefore, when the operation mode is switched, the potential of the input signal of the control signal terminal 120 is set near the middle between the potential VDD and the potential GND as illustrated.

Here, in the circuit of FIG. 8, as shown in FIG. 10, the actual signal waveform input to the control signal terminal 120 has a certain time width from the "H" level to the "L" level or its level. It changes in reverse. As a result, a spike waveform is generated in the output signal of the AND gate 125 in FIG. 8, and the operation mode switching circuit 10
7 may be erroneously set. In particular, this tends to be a problem when the waveform has rounding.

[Third Prior Art] FIG. 11 is a circuit diagram showing a main part of the configuration of a semiconductor device according to a third prior art, which is described in Japanese Patent Application Laid-Open No. Hei 7-12902. As shown in the figure, this circuit also shares an input terminal used in a normal operation state with the control signal terminal 130. The operation mode of the semiconductor device is controlled by the operation mode setting detection signal 131.

In this figure, V1 is the operating potential of the power supply, and V2 is the ground potential. The potential V4 is set to a higher potential than the sum of the operating potential V1 of the power supply and the threshold value of the MOS transistor (metal oxide semiconductor transistor) 132. Here, in this prior art, the potential V
4 is generated inside the semiconductor device 133 using an oscillation circuit. Reference numeral 134 in the figure denotes a control signal terminal 130.
Is an input buffer for sending the output of the above to an internal circuit (not shown).

Now, when a signal having an "H" level input as the operating potential of the power supply and an "L" level as the ground potential is input to the control signal terminal 130 as a normal signal, this signal is in the normal operating state or It will function as an input signal in another operating state. That is, in this case, since the MOS transistor 132 is off, the potential V4 is output to the operation mode setting detection signal 131 via the load resistor 135 as shown in FIG.

On the other hand, the potential V3 higher than the potential V4 is used as the operation mode setting signal on the control signal terminal 130.
, The MOS transistor 132 is turned on. As a result, as shown in FIG. 12, the operation mode setting detection signal 131 changes from the potential V4 to the operating potential V1 of the power supply.
, The operation mode switching in the semiconductor device can be recognized.

[Application to a Plurality of Power Sources] Next, an embodiment in which the above-described first prior art is applied to a semiconductor device having a plurality of types of power sources different from the ground power source in addition to the ground power source will be described. . FIG. 13 is a block diagram of a semiconductor device in such an embodiment. The same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted here.

Now, as shown in FIG.
The first circuit 140 is driven by the first power supply 100, and the second circuit 143 is driven by the second power supply 142 via the second power supply wiring 141. And
In a normal operation state, when the input signal of the control signal terminal 105 is at “H” level or “L” level, the operation mode switching circuit 107 supplies the logical value from the input terminal 108 to the internal logic circuit 110, Output operation result to output terminal 11
Output to 2. On the other hand, in another operation state, the logic value from the input terminal 108 is output to the output terminal 112 without passing through the internal logic circuit 110.

FIG. 14 is a plan view showing a case where the semiconductor device according to this embodiment is mounted on a semiconductor chip 150. In the drawing, an input / output buffer 151 serves both as an input buffer 109 and an output buffer 111, and has a logic cell. 152 realizes the internal logic circuit 110. Reference numeral 153 is a well-known bonding pad.

On the other hand, a mode in which the third prior art described above (see FIG. 11) is applied to a semiconductor device 133 having a plurality of different types of power sources in addition to the ground power source will be considered. Then, in this embodiment, when the potential V1 is used as the first power supply, the potential V4 can be supplied to the semiconductor device 133 as the second power supply, so that the potential V4 does not need to be generated inside the semiconductor device 133.

However, the control signal terminal 130 is used as an input terminal in a normal operating state or another operating state, and when a potential higher than the operating potential V1 of the power supply is inputted, the element of the CMOS (complementary MOS) circuit is used. This causes problems such as destruction. Further, in the third conventional technique, a device is devised to stabilize the circuit operation by inputting a potential higher than the operating potential V1 of the power supply. However, sharing the normal input terminal and the control signal terminal causes instability of the operation, and this problem is pointed out by the literature describing the third prior art.

[0020]

As described above, in the first prior art, the control signal terminal 105 and the control signal input buffer 106 are required in addition to the input terminal 108 and the input buffer which are usually used. And However, if such terminals must be provided extra, the number of signal terminals usable by the user is reduced.

On the other hand, the second and third prior arts have a configuration in which a normal input terminal and a control signal terminal are shared. However, if these techniques are applied to a semiconductor device having a plurality of types of power supplies as they are, the problems of the conventional techniques will be inherited as they are.

That is, as described above, in the second prior art, there is a possibility that a spike waveform may occur in the output signal of the AND gate 125 (see FIG. 8), so that the operating potential of the first power supply and the ground power supply If the operation mode switching signal is set between the potentials of the two, the operation mode switching circuit may be erroneously set.

On the other hand, according to the third prior art, when the control signal terminal 130 (see FIG. 11) is used as an input terminal in a normal operation state or another operation state, when a potential higher than the operating potential of the power supply is inputted. In addition, there is a problem that the element of the CMOS circuit is destroyed.

In the steady state, no power supply current flows.
In a MOS circuit, when a different potential is generated internally by using an oscillation circuit or the like, a steady current flows and the reliability of the semiconductor device may be reduced. In order to avoid such a problem as much as possible, in the third prior art,
It is conceivable to provide a power supply of However, using the second power supply only for the purpose of recognizing the switching of the operation mode has a problem in that the terminal of the semiconductor device is occupied. This is the same as the first prior art in which a control signal terminal needs to be separately prepared.

Further, in the third prior art, since it is necessary to add the MOS transistor 132 and the load resistor 135 in addition to the operation mode switching circuit, the circuit size of the semiconductor device necessarily increases. There are problems. The present invention has been made in view of the above points, and an object of the present invention is to realize an operation mode switching without providing a test terminal in a multi-power-supply operation semiconductor device to which a plurality of independent power supplies are supplied. It is another object of the present invention to provide a semiconductor device that operates stably both in normal use and during a test, and does not generate an unstable region when the operation mode is switched.

[0026]

In order to solve the above-mentioned problems, the invention according to claim 1 provides a ground power supply and first to n-th power supplies (n is a natural number of 2 or more) different from the ground power supply. A first circuit block to which the potential of the first power supply is supplied, and a second to n-th circuit block to which potentials of the second to n-th power supply are respectively supplied. And an operation mode switching means for supplying the potentials of the second to n-th power supplies to a control input terminal and switching an operation mode of the apparatus based on the potentials of the power supplies.

According to a second aspect of the present invention, in the first aspect, the second to n-th circuit blocks include:
A logic circuit for performing a predetermined operation based on a signal supplied to an input terminal of the first circuit block, wherein the operation mode switching means is supplied to the input terminal based on a potential at the control input terminal Any one of a signal and an output of each of the logic circuits is selected, and the selected signal is transmitted to an output terminal of the first circuit block.

According to a third aspect of the present invention, in the second aspect of the present invention, a bidirectional terminal or a tri-state terminal is provided instead of the output terminal, and the operation mode switching means includes a control input terminal. When the potential is a non-operating potential, enable / disable of the bidirectional terminal or the tristate terminal is controlled by a signal supplied to an input terminal different from the input terminal. The invention according to claim 4 is the same as the invention according to claim 2.
In the invention described above, a latch circuit is added to an input of each of the logic circuits, and the non-operating potential is set to a potential at which each of the logic circuits can hold its state value.

The invention described in claim 5 is the same as that in claim 1.
5. The invention according to claim 4, wherein the second to n-th circuit blocks do not operate when the potentials of the second to n-th power sources are non-operating potentials. . According to a sixth aspect of the present invention, in the first aspect of the invention, the operation mode switching means switches the operation mode based on a change in a potential of a power supply supplied to the control input terminal. .

According to a seventh aspect of the present invention, in the sixth aspect, each of the second to n-th circuit blocks includes a logic circuit for performing a predetermined operation, and is connected to the control input terminal. Initial setting means for initializing the operation mode when the applied power supply potential is a non-operating potential; and whether the power supply potential applied to the control input terminal has changed from the non-operating potential to the operating potential or a predetermined reference Mode change means for detecting a change from a potential to an operation potential and changing the operation mode, wherein each of the logic circuits performs a predetermined operation in accordance with the operation mode changed by the mode change means. It is characterized by performing.

According to an eighth aspect of the present invention, in the seventh aspect of the present invention, the mode change means includes at least one flip-flop and at least two flip-flops connected to the control input terminal and having different threshold values from each other. Wherein each of the combinational circuits or the transfer gates detects a change in the potential of the power supply at the control input terminal and changes the logic value of the flip-flop. According to a ninth aspect of the present invention, in any one of the first to eighth aspects, the potentials of the second to n-th power sources change between an operating potential and a ground potential. I have.

[0032]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] First, a semiconductor device having two types of power supplies in addition to a ground power supply will be described. FIG. 1 is a block diagram showing the configuration of the semiconductor device according to the present embodiment. As shown in FIG. 1, a first power supply 1 and a second power supply 2 correspond to the above two types of power supplies.

The first circuit 3 is a circuit driven by the first power supply 1 via the first power supply wiring 4, and includes an operation mode switching circuit 5, an input buffer 7 connected to the input terminal 6, An output buffer 9 to which an output terminal 8 is connected is provided. Further, the second circuit 10 is a circuit driven by the second power supply 2 via the second power supply wiring 11. The second circuit 10 includes a ground power supply wiring 12
The power supply is also connected to a ground power supply 13 through which the internal logic circuit 14 is provided. The internal logic circuit 14 is a circuit necessary for realizing the functions of the semiconductor device when the semiconductor device is used for its intended purpose.

Here, the configuration of the operation mode switching circuit 5 will be described in detail. The operation mode switching circuit 5 includes an inverter 15, AND gates 16 to 17, and a selector 18. The operation mode switching circuit 5 uses the second power supply 2 as one of the input signals, and the second power supply 2 is a selection signal of the selector 18. The inverter 15 and the AND gates 16 to 17 send the output signal of the input buffer 7 to either the selector 18 or the internal logic circuit 14 according to the level of the second power supply 2. The selector 18 outputs the output of the internal logic circuit 14 and the AND gate 1 according to the level of the second power supply 2 which is the selection signal.
6 to select one of the output signals of the input buffer 7. That is, the selector 18 sets the selection signal to “H”.
When the level is at the level, the output of the internal logic circuit 14 is selected, and when the selection signal is at the "L" level, the output of the AND gate 16 is selected.

FIG. 2 is a plan view showing a case where the semiconductor device according to the present embodiment is mounted on a semiconductor chip 20.
In the figure, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted here. In the figure,
The input / output buffer 21 doubles as the input buffer 7 and the output buffer 9 in FIG. 1 and is driven by the first power supply 1. Further, the operation mode switching circuit 5 is supplied with the operating potential of the first power supply 1 (that is, the potential required for the first circuit 1 to operate) via the first power supply wiring 4, and The second power supply 2 via the second power supply wiring 11
Is supplied as an input signal, and further connected to a ground power supply 13 via a ground power supply wiring 12. The logic cell 22 realizes the internal logic circuit 14, and is supplied with the operating potential or the ground potential of the second power supply 2 via the second power supply wiring 11. Reference numeral 23 denotes a well-known bonding pad.

Next, the operation of the semiconductor device having the above configuration will be described. First, a case where the second power supply 2 is at an operating potential as a normal operation state will be described. When the second power supply 2 is at the operating potential ("H" level), the output of the inverter 15 becomes "L" level, and the output of the AND gate 16 becomes "L".
L level. In contrast, AND gate 1
Numeral 7 outputs the logical value applied to the input terminal 6 and output from the input buffer 7 to the internal logic circuit 14 as it is.
In addition, the selector 18 outputs the second power supply 2 which is the selection signal to “
Since the output is at the “H” level, the output of the internal logic circuit 14 is selected, and the selected output is output to the output terminal 8 via the output buffer 9.

On the other hand, a case where the second power supply 2 is at the ground potential will be described as another operation state. When the second power supply 2 is at the ground potential, the output of the inverter 15 becomes "H" level, the AND gate 16 outputs the logical value of the input buffer 7 to the selector 18 as it is, and the output of the AND gate 17 is "L". Fixed to level. Further, the selector 18 selects the output of the AND gate 16 because the second power supply 2 which is the selection signal is at the “L” level, and this is output to the output terminal 8 via the output buffer 9. Further, at this time, since the second power supply 2 is at the ground potential, the internal logic circuit 14 does not operate.

Now, a case where the present embodiment is applied to the test of the semiconductor device shown in FIG. 2 will be described. First, as a normal operation state, the potentials of the first power supply 1, the second power supply 2, and the ground power supply 13 are assumed to be 5V, 3V, and 0V, respectively. Then, the input signal supplied from the bonding pad 23 is supplied to the operation mode switching circuit 5 via the input / output buffer 21. The operation mode switching circuit 5 treats the potential 3 V of the second power supply 2 supplied by the second power supply wiring 11 as “H” level, and supplies an input signal to the logic cell 22.

For this reason, the potential of the second power supply 2 of 3 V is applied to the logic cell 22 via the second power supply wiring 11.
And is connected to the potential 0 V of the ground power supply 13 via the ground power supply wiring 12. After performing a predetermined logical operation based on the input signal, the logical cell 22 outputs the operation result to the operation mode switching circuit 5. The operation mode switching circuit 5 outputs an output signal from the logic cell 22 to the bonding pad 23 via the input / output buffer 21.

On the other hand, as another operation state, the potentials of the first power supply 1, the second power supply 2 and the ground power supply 13 are set to 5 respectively.
V, 0V, and 0V. Then, the input signal supplied from the bonding pad 23 is transmitted to the input / output buffer 2.
1 and is supplied to the operation mode switching circuit 5.
The operation mode switching circuit 5 includes a second power supply wiring 11
Is treated as "L" level, and the input signal is supplied to the operation mode switching circuit 5. The operation mode switching circuit 5 outputs the input signal to the bonding pad 23 via the input / output buffer 21.

As described above, the test of the input / output buffer 21 used as the output buffer can be easily set by the input signal of the input / output buffer 21 used as the input buffer. That is, if there are two test patterns, the states of the “H” level and the “L” level can be realized, and only the input / output buffer 21 and the operation mode switching circuit 5 need to be operated.
Further, by setting the potential of the second power supply 2 to 0 V,
Logic cells 22 unnecessary for the test are separated.
The power supplied to the AND gate 17 may be different from the power supplied to each part of the operation mode switching circuit 5.

[Second Embodiment] In this embodiment, a semiconductor device having four types of power sources in addition to a ground power source will be described. FIG. 3 is a block diagram showing the configuration of the semiconductor device according to the first embodiment. Here, in FIG. 3, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted here.

Now, as shown in FIG.
Is a circuit operated by the first power supply 1 and includes an operation mode switching circuit 31, an input buffer 7, and an output buffer 9. In addition, the second circuit 32, the third circuit 33, the fourth
Circuit 34 includes a second power supply 2 and a third power supply 3
5, circuits operated by the fourth power supply 36, each having a logic circuit 37, a logic circuit 38, and a logic circuit 39. That is, these logic circuits are respectively connected to the second power supply 2,
It is configured to operate with a third power supply 35 and a fourth power supply 36.

Inverters 40 to 42, NAND gate (N
AND gates) 43a to 43c are selectors 45 to 47
Is a circuit for generating a selection signal for. These selectors perform logic circuits 37 to 39 in accordance with the generated selection signal.
And the output of the input buffer 7 is selected. Note that the third power supply wiring 48, the fourth power supply wiring 48,
Of the third power supply 35 and the fourth power supply
Is supplied to each section.

According to the selection signal from the NAND gate 43b, the selector 45 selects the output of the logic circuit 37 if the selection signal is at "H" level, and selects the output of the input buffer 7 if the selection signal is at "L" level. And sends it to the input of logic circuit 38. Similarly, the selector 46
Selects the output of the logic circuit 38 according to the selection signal from the NAND gate 43c if the selection signal is at "H" level, and selects the output of the input buffer 7 if the selection signal is at "L" level. To the input of the logic circuit 39.

The selector 47 selects one of the outputs of the input buffer 7 and the logic circuits 37 to 39 based on the outputs of the inverter 42 and the NAND gates 43a to 43b. More specifically, when the output of the NAND gate 43a is at "L" level, the output of the logic circuit 37 is selected,
When the output of the NAND gate 43b is at "L" level, the output of the logic circuit 38 is selected, and the output of the inverter 42 becomes "L".
When the output is low, the output of the logic circuit 39 is selected. When the outputs of the inverter 42 and the NAND gates 43a to 43b are all high, the selector 47 selects the output of the input buffer 7.

Next, the operation of the semiconductor device having the above configuration will be described. In the following, the operating potentials of the first power supply 1, the second power supply 2, the third power supply 35, and the fourth power supply 36 are 5V, 3V, 3V, and 2V, respectively, and the ground potential is 0V.
And First, as a normal operation state, the first power supply 1
It is assumed that the second power source 2, the third power source 35, and the fourth power source 36 are 5V, 3V, 3V, and 2V, respectively. In this case, since the outputs of the inverters 40 and 41 are both at "L" level, the outputs of the NAND gates 43a to 43c are all at "H" level, and the output of the inverter 42 is at "L" level.

On the other hand, the input signal given to the input terminal 6 is supplied to the input of the logic circuit 37 via the input buffer 7. On the other hand, the selector 45 selects the output of the logic circuit 37 and connects it to the input of the logic circuit 38, and the selector 46 connects the output of the logic circuit 38 to the input of the logic circuit 39. The selector 47 selects the output of the logic circuit 39, and the selected signal is output to the output terminal 8 via the output buffer 9.

Next, as other first operation states, a first power supply 1, a second power supply 2, a third power supply 35, and a fourth power supply 3
6 is assumed to be 5V, 3V, 0V, and 0V, respectively. In this case, since the outputs of the inverters 40, 41, and 42 become "L" level, "H" level, and "H" level, respectively, the output of the NAND gate 43a becomes "L" level.
The output of the NAND gate 43b goes high and the output of the NAND gate 43c goes high. On the other hand, the input signal given to the input terminal 6 is supplied to the logic circuit 37 via the input buffer 7. On the other hand, the selector 47 selects the output of the logic circuit 37 and outputs it to the output terminal 8 via the output buffer 9. At this time, since the third power supply 35 and the fourth power supply 36 are both at 0 V, the logic circuits 38 and 39 are not operated.

Next, a first power supply 1, a second power supply 2, a third power supply 35, and a fourth power supply 36 are set as other second operation states.
Are 5V, 0V, 3V, and 0V, respectively.
In this case, since the outputs of the inverters 40, 41, and 42 become "H" level, "L" level, and "H" level, respectively, the output of the NAND gate 43a becomes "H" level and the output of the NAND gate 43b becomes "L". The output of the NAND gate 43c becomes "H" level. On the other hand, input terminal 6
The input signal supplied to the input buffer 7 and the selector 4
5 to the input of the logic circuit 38. On the other hand,
The selector 47 selects the output of the logic circuit 38 and outputs it to the output terminal 8 via the output buffer 9. At this time, since both the second power supply 2 and the fourth power supply 36 are at 0 V, the logic circuits 37 and 39 do not operate.

Next, as another third operation state, the first power supply 1, the second power supply 2, the third power supply 35, and the fourth power supply 3
6 is assumed to be 5V, 0V, 0V, and 2V, respectively. In this case, since the outputs of the inverters 40, 41, and 42 become "H" level, "H" level, and "L" level, respectively, the outputs of the NAND gate 43a and the NAND gate 43b become "H" level, and the NAND gate 43c
Is at "L" level. On the other hand, the input signal given to the input terminal 6 is supplied to the input of the logic circuit 39 via the input buffer 7 and the selector 46. On the other hand, the selector 47 selects the output of the logic circuit 39 and outputs it to the output terminal 8 via the output buffer 9. At this time, since both the second power supply 2 and the third power supply 35 are at 0 V, the logic circuits 37 and 38 do not operate.

Next, as another fourth operation state, the first power supply 1, the second power supply 2, the third power supply 35, and the fourth power supply 3
6 is assumed to be 5V, 0V, 0V and 0V, respectively. In this case, the outputs of the inverters 40 to 42 are all "
Therefore, the output of the NAND gate 43a and the output of the NAND gate 43b both become "H" level, and the output of the NAND gate 43c becomes "L" level. The signal is directly supplied to the selector 47 via the buffer 7. On the other hand, the selector 4
7 selects the output of the input buffer 7 and outputs it to the output terminal 8 via the output buffer 9. At this time,
Since the second power supply 2, the third power supply 35, and the third power supply 36 are all at 0 V, the logic circuits 37 to 39 do not operate.

As described above, in the other first to third operating states, it is possible to perform a test for each circuit operated by a different power supply. In the other fourth operation state, the test of the input / output buffer 21 (see FIG. 2) used as the output buffer is possible as in the first embodiment. Also, as in the first embodiment, the potential of each power supply is set to 0 for circuits unnecessary for the test.
By setting V, this is separated.

By changing the combinational circuit provided in the operation mode switching circuit 31, for example, the logic circuit 37 and the logic circuit 38 can be operated, and the semiconductor device can be operated with the logic circuit 39 disconnected. It is possible.

In the operation mode switching circuit 31, the inverters 40 to 42 and the NAND gates 43a to 43
The threshold value of c is set higher or lower than usual, and a latch circuit is provided at each input of the logic circuits 37 to 39. In addition, a second potential different from the above-described operating potential and ground potential is set for each of the second power source 2, the third power source 35, and the fourth power source 36. These second potentials are set to, for example, 2V for the second power supply 2, 2V for the third power supply 35, and 1.5V for the fourth power supply 36, and these second potentials are respectively set. "
In this manner, the logic circuit 3 is configured to be recognized as the L level.
State values of 7 to 39 can be held.

[Third Embodiment] In this embodiment, among the embodiments of a semiconductor device having two kinds of power supplies in addition to the ground power supply, a different form from the first embodiment will be described. FIG. 4 is a block diagram showing the configuration of the semiconductor device according to the present embodiment. The same components as those in FIGS. 1 to 3 are denoted by the same reference numerals, and description thereof is omitted here.

Now, as shown in FIG.
Is a circuit operated by the first power supply 1 and includes an operation mode switching circuit 52, an input buffer 7, and an output buffer 9. The second circuit 53 is a circuit that operates on the second power supply 2, and includes an input buffer 7, an output buffer 9,
An internal logic circuit 59 is provided.

Here, the operation mode switching circuit 52
Level determination circuits 54 to 55, T-flip-flop 56
57, and a decoder 58. The level determination circuits 54 to 55 determine and output the level of the determined input signal, and the level determination threshold will be described later. In these T-flip-flops, reference numeral T denotes a clock input terminal, reference numeral R denotes a reset terminal, reference numeral Q denotes an output terminal, and reference numeral QB denotes an output terminal for outputting an inverted signal of a signal output from the output terminal Q. When the reset terminal R becomes "H" level, the T-flip-flop is reset. The decoder 58 decodes the two outputs of the T-flip-flops 56 to 57 into four signals and outputs these to the internal logic circuit 59.

The internal logic circuit 59 is set to various operation modes by a decode signal sent from the decoder 58. In FIG. 4, the T-flip-flop has a two-stage configuration. The following combinations are possible. Therefore, for example, according to the levels of the output terminals Q of the T-flip-flops 56 and 57, when these outputs are both at the “L” level, the normal operation is at the “H” level and the “L” level respectively. , Scan path test operation When “L” level and “H” level, respectively, operation for testing some functional blocks of the internal logic circuit 59 When both are “H” level, only the combination circuit test is performed. It is possible to assign such as operation.

On the other hand, the levels recognized by the level determination circuits 54 to 55 are set differently from those of ordinary logic elements as shown in FIG. That is, in FIG.
The region 70a is a region where the normal logic element recognizes the “H” level, and the region 70b is a region where the normal logic element recognizes the “L” level.

On the other hand, the level judgment circuit 54 sets "H"
Level, the area recognized as “L” level is the threshold potential V
_The area 71a and the area area 71b are set with _TH1 as a boundary. Similarly, the level determination circuit 55
The regions recognized as the H level and the L level are respectively divided into the region 72a and the region 72b with the threshold potential V _TH2 as a boundary.
Is set to Therefore, the level judgment circuit 54,
The difference between the levels 55 is the area 73 in the figure.

Next, the operation of the semiconductor device having the above configuration will be described. In the following, the operating potential of the first power supply 1 is set to 5
V, the operating potential of the second power supply 2 is 3.3 V, and the reference potential of the operating mode switching circuit 52 is 1. 5V, ground potential 0V
And In such a case, when the waveform shown in FIG. 6 is supplied as the second power supply 2, the level determination circuits 54 to 5
5 are as shown in FIG.

That is, when the potential of the second power supply 2 changes from 3.3 V, which is the operating potential, to 0 V (second potential), the level determination circuit 55 outputs the "H" level. Thereby, T-flip-flops 56 to 57
Are reset to "H" level, and the levels of these output terminals Q are initialized to "L" level. In addition,
At this time, the output of the level determination circuit 54 also changes from "L" level to "H" level. Next, when the potential of the second power supply 2 returns from 0 V to 3.3 V, the levels of the output terminals Q of the level determination circuits 55 and 54 are sequentially switched from the “H” level to the “L” level in this order. .

After that, the potential of the second power supply 2 becomes l. 5V (3rd
), Only the output of the level determination circuit 54 changes from “L” level to “H” level. Thereby, the clock input terminal T of the T-flip-flop 56
And the level of the output terminal Q of the T-flip-flop 56 is inverted from “L” level to “H” level. Note that the potential of the second power supply 2 is the threshold potential V _TH2
, The output of the level determination circuit 55 remains at the “L” level.

After that, when the potential of the second power supply 2 returns from 1.5 V to 3.3 V, the output of the level judgment circuit 54 becomes "
L "level. Then, the second power supply 2 is turned on to 3.3" again.
When the voltage is changed from V to 1.5 V, a clock enters the T-flip-flop 56 and the level of the output terminal Q thereof becomes "
Invert from H level to “L” level, that is, T
The level of the output terminal QB of the flip-flop 56 is "
The level changes from "L" level to "H" level.
The clock enters the flip-flop 57 and its output is inverted. Therefore, T-flip-flops 56 and 57
Are at "L" level and "H" level, respectively.

Thereafter, by changing the second power supply 2 in the same manner as described above, the T-flip-flops 56,
After all the outputs of 57 become “H” level,
The outputs of the T-flip-flops 56 and 57 both return to the “L” level. As long as the potential of the second power supply 2 does not fall below the threshold potential V _TH2 , the output of the level determination circuit 55 does not become “H” level, and the T-flip-flops 56 to
57 is never reset. In other words, these T-flip-flops can be reset by lowering the potential of the second power supply 2 to the ground potential.

As described above, the T-flip-flop 56
The output signal of the decoder 58 can be made different depending on the logical value output from the decoder 57. Therefore, a desired operation mode can be set in the internal logic circuit 59, and the first power supply 1 and the second power supply 2 have the respective operation potentials of 5
At 3.3 V, the semiconductor device can function in the set operation mode.

By changing the number of stages of the T-flip-flops, the number of required operation modes can be easily changed. In this embodiment, inverters are used as the level determination circuits 54 and 55. However, it is also possible to use various combinational circuits or transfer gates. When the logic circuit is bypassed, the input terminal may not be sent to the output terminal as it is, but the signal supplied to the input terminal may be inverted and sent to the output terminal.

In each of the above embodiments, the case where the output terminal is tested has been described. However, this may be applied to a bidirectional terminal or a tristate terminal. In such a case, the logical value of a certain input terminal is supplied to each of these terminals, and the logical value of another input terminal different from this input terminal is used as an enable signal for each of these terminals, so that the bidirectional terminal and the tristate terminal are used. What is necessary is just to control enable / disable. In this way, when performing a test depending on the setting of the logical value of the bidirectional terminal or the tristate terminal,
It is possible to easily set the logical values of these terminals.

Further, the present invention can take the following aspects in connection with the description of the claims. According to claim 10, the operation mode switching means selects an output of each of the logic circuits when the potential of the control input terminal is an operation potential, and selects the input terminal when the potential of the control input terminal is a non-operation potential. The semiconductor device according to claim 2, wherein a signal given to the semiconductor device is selected.

According to an eleventh aspect, the operation mode switching means selects a signal supplied to the input terminal when all the power supply potentials supplied to the control input terminal are non-operating potentials. If any of the potentials is the operating potential, a signal given to the input terminal is input to any of the logic circuits to which the operating potential is supplied, and the output of the logic circuit is selected. A semiconductor device according to claim 2 is considered.

According to a twelfth aspect, when the potential of the control input terminal is a non-operating potential, the operating mode switching means does not depend on the logic of a signal input to the input terminal.
3. The semiconductor device according to claim 2, further comprising input fixing means for setting inputs to the second to nth circuit blocks to fixed values.

According to a thirteenth aspect, a semiconductor device according to the twelfth aspect, wherein power sources having different potentials are supplied to the operation mode switching means and the input fixing means. According to a fourteenth aspect, the semiconductor device according to the second aspect is characterized in that a signal applied to the input terminal is sent as it is or logically inverted to the output terminal.

According to a fifteenth aspect, the non-operating potential is a ground potential.
The semiconductor device according to any one of items 0 to 12 is considered.
16. The semiconductor device according to claim 1, wherein power supplies having different potentials are supplied to the second to nth circuit blocks and the operation mode switching unit. Can be considered.

[0075]

As described above, according to the present invention,
Since the operation mode is switched based on the potentials of the second to n-th power supplies supplied to the semiconductor device, there is no need for a dedicated control terminal for switching the operation mode. The effect of not reducing the number of terminals can be obtained. In addition, because it adopts a configuration that does not share the control terminal and the signal input terminal,
When the semiconductor device is in the operation state, there is also an effect that there is no possibility that the operation mode switching means is erroneously set even if the input signal has a rounded waveform.

According to the second aspect of the present invention, one of the signal applied to the input terminal and the output of each logic circuit is selected based on the potential at the control input terminal and sent to the output terminal. By setting so that the signal given to the input terminal is selected, the signal of the input terminal is given to the output terminal by bypassing the logic circuit, and the logic value of the output terminal is easily determined in the test of the semiconductor device. Therefore, the required number of test patterns and the required test time can be significantly reduced.

According to the third aspect of the present invention, when the potential of the control input terminal is the non-operating potential, the logical value of the input terminal is supplied to the bidirectional terminal or the tristate terminal. The bi-directional terminal or tri-state terminal is controlled by the logical value of the input terminal of the semiconductor device. Therefore, even if the test of the semiconductor device depends on the setting of the logical value of the bi-directional terminal or tri-state terminal, the logical The effect is obtained that the value can be easily set.

According to the fourth aspect of the present invention, each logic circuit is provided with a latch circuit, and the non-operating potential is set to a potential at which each logic circuit can hold its state value without being set to the ground potential. Therefore, even if an unnecessary circuit is disconnected in the operation mode after switching the operation mode,
The effect is obtained that the state value of the separated circuit can be held.

According to the fifth aspect of the present invention, when the potential of the supplied power is the non-operating potential, each circuit block does not perform its operation. In the operation mode, an advantage is obtained in that an unnecessary circuit block can be separated to operate the semiconductor device.

According to the eighth aspect of the present invention, since a change in the power supply potential at the control input terminal is detected to change the logic value of the flip-flop, at least two types of power supplies are provided in addition to the ground potential. If the number of flip-flops is 2
The effect is obtained that an operation mode corresponding to the power can be set.

According to the ninth aspect of the present invention, since the range of change in the potential of each power supply is set between the operating potential and the ground potential, the risk of destroying elements of the semiconductor device can be reduced. Is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a plan view when the same device is mounted on a semiconductor chip 20.

FIG. 3 is a block diagram illustrating a configuration of a semiconductor device according to a second embodiment of the present invention;

FIG. 4 is a block diagram showing a configuration of a semiconductor device according to a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing a level determination circuit according to the first embodiment;
FIG. 5 is a diagram illustrating a relationship between a region recognized by 55 and a power supply potential.

FIG. 6 is a timing chart showing a relationship between a waveform of a second power supply and waveforms of level determination circuits 54 to 55 in the same embodiment.

FIG. 7 is a block diagram showing a configuration of a semiconductor device according to a first conventional technique.

FIG. 8 is a circuit diagram of a test circuit provided in a semiconductor device according to a second conventional technique.

FIG. 9 is a timing chart showing the operation of the test circuit.

FIG. 10 is a timing chart showing a circuit operation in the test circuit in the case where waveform rounding is considered.

FIG. 11 is a circuit diagram showing a main part of a configuration of a semiconductor device according to a third conventional technique.

FIG. 12 is a graph showing a relationship between a voltage input to a control signal terminal 130 and a voltage of an operation mode setting detection signal 131 in the device.

FIG. 13 is a block diagram in the case where the semiconductor device according to the first conventional technique is driven by two types of power supplies.

FIG. 14 is a plan view when the same device is mounted on a semiconductor chip 150.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... 1st power supply, 2 ... 2nd power supply, 3, 30, 51 ... 1st circuit, 4 ... 1st power supply wiring, 5, 31, 52 ...
Operation mode switching circuit, 6 input terminal, 7 input buffer, 8 output terminal, 9 output buffer, 10, 32,
53 ... second circuit, 11 ... second power supply wiring, 12 ...
Ground power supply wiring, 13: ground power supply, 14, 59: internal logic circuit, 15, 40 to 42: inverter, 16, 17
... AND gate, 18, 45-47 ... selector, 20 ...
Semiconductor chip, 21 input / output buffer, 22 logic cell, 23 bonding pad, 33 third circuit, 3
Reference numeral 4: fourth circuit, 35: third power supply, 36: fourth power supply, 37 to 39: logic circuit, 43a to 43c: NAND gate, 48: third power supply wiring, 49: fourth power supply Wiring, 54, 55 ... level judgment circuit, 56, 57 ... T
-Flip-flop, 58 ... decoder

Claims (9)

[Claims] 1. A ground power supply and a first power supply different from the ground power supply.
In a semiconductor device driven by an nth to nth (n is a natural number of 2 or more) power supplies, a first circuit block to which a potential of the first power supply is supplied, and a potential of the second to nth power supplies 2nd supplied respectively
To the n-th circuit block, and the potentials of the second to n-th power supplies are supplied to a control input terminal.
A semiconductor device comprising: an operation mode switching means for switching an operation mode of the device based on the potential of the power supply. 2. The second to n-th circuit blocks each include a logic circuit that performs a predetermined operation based on a signal supplied to an input terminal of the first circuit block, and the operation mode switching unit includes: Selecting one of a signal supplied to the input terminal and an output of each of the logic circuits based on a potential at the control input terminal, and transmitting the selected signal to an output terminal of the first circuit block. The semiconductor device according to claim 1, wherein: 3. The device according to claim 1, further comprising: a bidirectional terminal or a tri-state terminal in place of the output terminal, wherein the operation mode switching unit is configured to connect to the input terminal when a potential of the control input terminal is a non-operation potential. 3. The semiconductor device according to claim 2, wherein enable / disable of said bidirectional terminal or said tristate terminal is controlled by a signal supplied to another input terminal. 4. A circuit according to claim 2, wherein a latch circuit is added to an input of each of said logic circuits, and said non-operating potential is set to a potential at which each of said logic circuits can hold its state value. Semiconductor device. 5. The circuit according to claim 1, wherein the second to n-th circuit blocks do not operate when the potentials of the second to n-th power supplies are non-operating potentials. A semiconductor device according to any one of the preceding claims. 6. The semiconductor device according to claim 1, wherein the operation mode switching means switches the operation mode based on a change in a potential of a power supply supplied to the control input terminal. 7. The second to n-th circuit blocks each include a logic circuit for performing a predetermined operation, and when the potential of a power supply supplied to the control input terminal is a non-operating potential, an initial state of the operating mode is set. Initial setting means for setting, detecting that the potential of the power supply supplied to the control input terminal has changed from a non-operating potential to an operating potential or has changed from a predetermined reference potential to an operating potential, 7. The semiconductor device according to claim 6, further comprising: a mode changing unit for performing a change, wherein each of the logic circuits performs a predetermined operation according to the operation mode changed by the mode changing unit. 8. The mode changing means includes at least one flip-flop and at least two combination circuits or transfer gates connected to the control input terminal and having different threshold values from each other. 8. The semiconductor device according to claim 7, wherein the transfer gate changes a logical value of the flip-flop by detecting a change in a potential of a power supply at the control input terminal. 9. The device according to claim 1, wherein the potentials of said second to n-th power supplies change between an operating potential and a ground potential.
9. The semiconductor device according to claim 8.