JPH1079196A - Ferroelectric storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a ferroelectric storage device which can selectively use either one-Tr one-Cap constitution or two-Tr two-Cap constitution correspondingly to the application, can highly reliably operate at a high speed, and can be constituted to have a sufficiently large capacity. SOLUTION: In a ferroelectric storage device, a memory array is constituted by arranging basic memory cells M00-M158 composed of ferroelectric capacitors FC and switching transistors Tr which switch the electrically connecting and disconnecting states between bit lines and the first electrodes of the ferroelectric capacitors and reference basic memory cells RM00-RM158 in a matrix-like state and row decoders 6-9 which activate one word line corresponding to a designated address when one-Tr one-Cap mode is selected and two word lines corresponding to designated addresses when two-Tr two-Cap mode is selected are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a ferroelectric memory device utilizing polarization inversion of a ferroelectric.

[0002]

2. Description of the Related Art Various types of ferroelectric non-volatile memories utilizing the polarization reversal of a ferroelectric having hysteresis characteristics as shown in FIG. 2 have been proposed at present. In this case, one bit is constituted by two switching transistors and two ferroelectric capacitors (referred to as 2Tr-2Cap method).
One bit is constituted by one switching transistor and one ferroelectric capacitor (1Tr-1Ca)
p type) have been proposed.

FIG. 3 is a diagram showing a basic 1-bit configuration of a nonvolatile memory employing the 2Tr-2Cap method. This memory cell has a bit line B as shown in FIG.
Switching transistors Tr1 and Tr2 each composed of an n-channel MOS transistor having a drain connected to L1 and BL2, respectively;
One bit is constituted by two combinations of ferroelectric capacitors FC1 and FC2 in which one electrode is connected to the sources of r1 and Tr2. The gates of the switching transistors Tr1 and Tr2 share a common word line WL.
, And the other electrodes (plate electrodes) of the ferroelectric capacitors FC1 and FC2 are connected to a common plate line PL. The bit lines BL1 and BL2 are connected to a write and read circuit (not shown), and the word lines WL and plate lines PL are connected to a row decoder (not shown).

[0004] 2Tr-2Cap having such a structure
In the method, the ferroelectric films of the ferroelectric capacitors connected to the two pairs of bit lines in the write operation are polarized in opposite directions, and the polarization state is read in the read operation. Hereinafter, data writing and reading operations in the nonvolatile memory employing the 2Tr-2Cap method will be described with reference to timing charts of FIGS.

First, the write operation will be described with reference to FIG. At the time of writing, first, as shown by T1 in the figure, the ground GND level “0” is applied to the bit line BL1.
V, a power supply voltage V _CC is applied to the bit line BL2, and (V _CC +1 V) is applied to the word line WL. Note that the word line W
The reason why the set level of L is (V _CC +1 V) is that the threshold voltage Vth of the switching transistor is Vth <1 V
Therefore, the voltage is set to “+1 V” to prevent a potential drop due to the transistor. As a result, the switching transistors Tr1 and Tr2 become conductive, and a ground GND level, that is, a voltage of “0” V is applied to the bit line side electrode (one electrode) of the ferroelectric capacitor FC1,
The voltage V _{CC is} applied to the bit line side electrode of the ferroelectric capacitor FC2.
Is applied. At this time, the plate line PL is "0" V
(Ground level). As a result, only the ferroelectric capacitor FC2 has a polarization state from the bit line side electrode toward the plate electrode.

Thereafter, as shown at T2 in the figure, a power supply voltage V _CC is applied to the plate line PL, and subsequently, as shown at T3 in the figure, "0" V is applied to the plate line PL. That is, while the word line WL is held at the power supply voltage V _CC level with respect to the plate line PL, GND (0 V)
→ Apply a pulse of V _CC → GND (0V). As a result, while the polarization state of the ferroelectric capacitor FC2 is maintained in a direction from the bit line-side electrode toward the plate line-side electrode, polarization occurs in the ferroelectric capacitor FC1, and the polarization state from the plate electrode toward the bit line-side electrode. A polarization state is reached. That is, the ferroelectric capacitors FC1,
FC2 is polarized in the opposite direction.
Move to points D and B in the hysteresis curve shown in FIG.

Next, a read operation will be described with reference to FIG. First, as shown by T1 in FIG. 5, "0" V is applied to the bit lines BL1 and BL2, and thereafter, the bit lines are opened. Also at this time, (V _CC +1) is applied to the word line WL.
V). Next, as shown in figure T2, raises the potential of the plate line PL from the "0" V to the power supply voltage V _CC. Here, when the configuration of the memory cell is viewed from the plate line PL, the ferroelectric capacitor FC and the parasitic capacitance Cb of the bit line BL are represented by an equivalent circuit connected in series. When the voltage _rises from 0 "V to the power supply voltage Vcc, the potential output to the bit line BL differs depending on the polarization state of the ferroelectric.

That is, the polarization state of the ferroelectric capacitor FC2 moves from point B to point C in the hysteresis curve shown in FIG. On the other hand, the polarization state of the ferroelectric capacitor FC1 moves from the point D to the point C and does not reverse the polarization. Accordingly, the amount of charge movement accompanying the change in polarization is larger in the ferroelectric capacitor FC2 whose polarization is inverted than in the ferroelectric capacitor FC1 whose polarization is not inverted, and the potential of the bit line BL2 is higher than that of the bit line BL1. The difference between the bit line potentials is referred to as bit line B.
Reading is performed by driving a differential sense amplifier (not shown) to which L1 and BL2 are connected and latching them at V _CC and 0 V, respectively, depending on the magnitude of the potential. Finally, as shown by T3 in the figure, "0" is again applied to the plate line PL again.
By applying V, the ferroelectric capacitor FC2 whose polarization has been inverted is returned to the original polarization state. Thus, a series of read operations is completed.

As described above, the read operation in the non-volatile memory adopting the 2Tr-2Cap method involves an operation of latching data by increasing the potential of the plate line and a subsequent operation of rewriting data by decreasing the potential of the plate line PL. The operation is performed in two cycles.

FIG. 6 is a diagram showing a basic 1-bit configuration of a nonvolatile memory adopting the 1Tr-1Cap method. As shown in FIG. 6, this memory cell MC has an n-channel M having a drain connected to bit line BL1.
Switching transistor T composed of OS transistor
r1 and a ferroelectric capacitor FC1 having one electrode connected to the source of the switching transistor Tr1 constitute one bit. The gate of the switching transistor Tr1 is connected to the word line WL, and the ferroelectric capacitor FC1 is connected to the word line WL. The other electrode (plate electrode) is connected to the plate line PL. And this 1Tr
The non-volatile memory employing the -1Cap method includes a reference switching transistor RTr1 having a drain connected to a reference bit line BL2, and a reference ferroelectric material having one electrode connected to the source of the switching transistor RTr1. Capacitor RF
A reference cell RMC constituted by C1 is provided, the gate of the switching transistor RTr1 is connected to the reference word line RWL, and the other electrode of the ferroelectric capacitor RFC1 is connected to the reference plate line RPL. The ferroelectric capacitor RFC1 of the reference cell RMC is used as a normal dielectric to prevent polarization inversion, and the reference plate line RP
The capacitor area is set so that the change in the bit line potential when the voltage V _CC is applied to L is intermediate between the change in the bit line potential when the polarization of the memory cell MC is reversed and the non-polarization is reversed.

Next, data writing and reading operations in the nonvolatile memory adopting the 1Tr-1Cap method will be described with reference to timing charts of FIGS.

In the 1Tr-1Cap method, writing and reading are basically performed in the same manner as in the 2Tr-2Cap method. The difference in this case is that a potential difference is detected between each bit line connected to a normal memory cell and a bit line connected to a reference cell.

In data writing, voltage control of each line as shown in FIG. 7 is performed, and the polarization state of one ferroelectric capacitor is changed to the state 0 (S) in the hysteresis curve of FIG.
point D in state 0) or B in state 1
Writing 1 bit is performed by setting a point.

In a read operation, as shown in FIG. 8, a word line RWL and a plate line RPL for a reference cell are driven in addition to a normal word line WL and a plate line PL, and a bit line connected to the reference cell RMC is driven. The difference between the potential of BL2 and the potential corresponding to the polarization state of bit line BL1 to which the memory cell is connected is detected. Therefore, since the reference cell RMC is used without reversing the polarization, the reference word line RWL is set to fall earlier than the reference plate line RPL so as not to enter the rewrite operation.

The read operation in the non-volatile memory employing the 1Tr-1Cap method is composed of two cycles of detecting the plate line potential and rewriting data to the memory cells MC.

[0016]

As described above, a ferroelectric memory having a memory cell composed of a switching transistor and a ferroelectric capacitor has two transistors and two capacitors for storing 1-bit data. To form one memory cell (2Tr-2Cap configuration) and operate differentially. This is because it is difficult to produce a uniform ferroelectric thin film, and 1T
This is because a sufficient margin of the bit line potential could not be secured at the time of reading in order to configure and operate the memory cell with r-1Cap. That is, 2Tr-2Cap
Thus, a memory cell is configured by the above and differential operation is performed, thereby reducing read failure due to variation in bit line potential at the time of read.

In recent years, the film quality of the ferroelectric film has been improved due to the progress of the film forming technology, and one memory cell is composed of one switching transistor and one ferroelectric capacitor (1T).
r-1Cap configuration).

However, in order to operate in the 1Tr-1Cap configuration, it is necessary to generate a reference potential for giving low-level data and high-level data threshold values at the time of reading. Required. In the reference cell, the operation in the 1Tr-1Cap method is controlled more than that in the 2Tr-2Cap method in order to perform an operation different from that of a normal memory cell (in order to reduce the fatigue of the ferroelectric film and not to cause polarization inversion). Becomes complicated. Further, since the bit line voltage at the time of reading is also smaller than that of the 2Tr-2Cap method for reading differentially, the operation speed is 2Tr-2 for the 1Tr-1Cap method.
It is slower than the Cap method.

As described above, the 1Tr-1Cap structure can reduce the memory cell area and is suitable for increasing the capacity.
There are still problems in terms of reliability and high-speed operation. Therefore, the 1Tr-1Cap configuration is suitable for applications that focus on capacity rather than reliability and speed, and the 2Tr-2Cap configuration is suitable for applications that focus on reliability and high-speed operation.
It is desirable that one chip satisfy both of these requirements.

The present invention has been made in view of such circumstances, and its object is to provide 1Tr-1Cap according to the application.
It is an object of the present invention to provide a ferroelectric memory device that can select and use either the configuration or the 2Tr-2Cap configuration, can operate with high reliability and at high speed, and has a configuration that is satisfactory in terms of capacity.

[0021]

In order to achieve the above object, the present invention provides a ferroelectric memory for storing binary data according to a polarization direction of a ferroelectric substance according to a voltage applied to first and second electrodes. A basic memory cell comprising a body capacitor and a switching transistor for switching electrical conduction and non-conduction between a bit line and a first electrode of the ferroelectric capacitor according to the level of a word line is arranged in a matrix. A ferroelectric memory device having at least two operation modes, wherein one word line corresponding to an address is activated in a first operation mode, and a ferroelectric memory device is activated in a second operation mode. A first circuit for activating two word lines in accordance with the address designation and a word line selected by the first circuit in the first operation mode, and A voltage of a predetermined level is applied at a predetermined timing to the second electrode of the ferroelectric capacitor in the addressed basic memory cell, and the two words selected by the first circuit in the second operation mode A second circuit connected to each of the lines and applying a voltage of a predetermined level at a predetermined timing to each second electrode of the ferroelectric capacitor in at least the addressed basic memory cell.

According to the ferroelectric memory device of the present invention, the first
In the operation mode, one word line is selected and activated by the first circuit, and one bit is constituted by a switching transistor connected to the bit line and a ferroelectric capacitor connected in series to the switching transistor. A 1Tr-1Cap configuration that stores binary data according to the direction of polarization of the ferroelectric is realized. In the second operation mode, two word lines are selected and activated by the first circuit, and the switching transistor connected to the bit line and the ferroelectric capacitor connected in series to the switching transistor are connected. One combination of two sets constitutes one bit, each ferroelectric capacitor is polarized in a different direction, and a 2Tr-2Cap configuration that stores binary data according to the direction of the polarization is realized.

[0023]

FIG. 1 is a circuit diagram showing one embodiment of a ferroelectric memory device according to the present invention. This ferroelectric memory device includes a memory cell array 1, a sense amplifier group 2,
Column gate group 3, column decoder 4, plate line driver 5, address buffer 6, pre-row decoder 7, word line decoder 8, reference word line decoder 9,
Word line driver 10 and word line boost circuit 1
1. In FIG. 11, WL
0 to WL15 are word lines, RWL0 and RWL1 are reference word lines, BL0L, BL0R, BL1L, BL
1R,..., BL7L, BL7R, BL8L, BL8R indicate bit lines, PL0 to PL7 indicate plate lines, and RPL indicates a reference plate line.

In the memory cell array 1, basic memory cells M00 to M158 having a 1Tr-1Cap configuration including a switching transistor Tr formed of an NMOS transistor and a ferroelectric capacitor FC are arranged in a matrix, for example, a matrix of 16 rows and 8 columns. Have been. Basic memory cell M00 ~
Adjacent to the array area of M158, reference basic memory cells RM00 to RM18 having a 1Tr-1Cap configuration including a reference switching transistor RTr and a ferroelectric capacitor RFC are arranged in a matrix of 2 rows and 2 columns.

Then, two rows adjacent to each other, specifically, the first row and the second row, the third row and the fourth row,.
The plate electrodes of the ferroelectric capacitors FC of the basic memory cells in the sixth row are connected to common plate lines PL0 to PL7, respectively. Similarly, the plate electrodes of the ferroelectric capacitors RFC of the reference basic memory cells RM00 to RM08 and the reference basic memory cells RM10 of the remaining rows
RM18 to the plate electrodes of the ferroelectric capacitors RFC are connected to a common reference plate line RPL.

The first and second lines, the third and fourth lines,
.., The drains of the switching transistors Tr of the basic memory cells arranged in the same column
A pair of bit lines BL0L, BL0R, BL1L, BL1R,..., BL7 respectively connected to sense amplifiers 21 to 28 employing a folded bit line method.
L, BL7R, BL8L, BL8R.

More specifically, in FIG. 1, the drains of the switching transistors Tr of the basic memory cells M00, M02,..., M140 in the odd-numbered rows of the first column and the reference basic memory cell RM10 are commonly connected to the bit line BL0L. , Basic memory cells M01, M03,.
M150 and the drain of the switching transistor Tr of the reference basic memory cell RM00 are connected to the bit line BL0.
R is commonly connected. The drains of the switching transistors Tr of the odd-numbered basic memory cells M01, M22,..., M141 in the second column and the reference basic memory cell RM11 are commonly connected to the bit line BL1L, and the even-numbered basic memory cells M11 in the second column are connected. , M32,..., M151 and the drain of the switching transistor Tr of the reference basic memory cell RM01 are commonly connected to the bit line BL1R. Similarly, the switching transistors Tr of the basic memory cells M08, M28,.
Are commonly connected to the bit line BL8L, and the drains of the switching transistors Tr of the basic memory cells M18, M38,..., M158 and the reference basic memory cell RM08 in the even-numbered row in the eighth column are commonly connected to the bit line BL8R. ing.

Further, the gates of the switching transistors Tr of the basic memory cells arranged in the same row are connected to the common word lines WL0 to WL connected to the word line driver 10.
15, and reference word lines RWL0, RWL1
Connected to each other.

In this ferroelectric memory device, 1Tr-1C
The operation by the ap configuration and the operation by the 2Tr-2Cap configuration can be selectively taken. 1Tr-1Cap
When operating with the configuration, all of the basic memory cells M00 to M158 arranged in the memory cell array 1 are used as one storage cell, and the reference basic memory cells RM00 to RM18 are used. On the other hand, 2Tr-2Cap
When operating with the configuration, the first and second rows, the third and fourth rows
Row, ..., 2 arranged in the same column of the 15th and 16th rows
One basic memory cell is used as one set. For example, basic memory cells M00 and M10, M08 and M18, and M148 and M158. In the case of 2Tr-2Cap, the reference basic memory cells RM00 to RM18 are not used. That is, the reference word lines RWL0, RWL
1 is not activated.

Each of the plate lines PL0 to PL7 and the reference plate line RPL are connected to the plate driver 5.
Are connected in parallel with each other and driven collectively by the plate driver 5.

The bit lines BL0L and BL0R are connected to the sense amplifier 21 as described above, and the two output lines are connected to the column gates 3 made of NMOS transistors.
1L and 31R are provided. The sense amplifier 22 is connected to bit lines BL1L and BL1R, and the two output lines are provided with column gates 32L and 32R composed of NMOS transistors. Similarly, the sense amplifier 27 is connected to bit lines BL7L and BL7R, the two output lines are provided with column gates 37L and 37R made of NMOS transistors, and the sense amplifier 28 is connected to the bit line BL8L. , BL8R, and two output lines are provided with column gates 38L, 38R made of NMOS transistors. Then, the paired column gates 31L and 31R, 3
Output control signals S41, S42,..., S47, S48 of the column decoder 4 are supplied to the gate electrodes of 2L and 32R,..., 37L and 37R, and 38L and 38R, respectively.

The address buffer 6 includes an inverter 601
To 616, and transfer gates 617 to 624 connecting the sources and drains of the PMOS transistor and the NMOS transistor. The address information ADD0 to ADD3 for writing and reading is transmitted by the clock signal C.
Latched in accordance with LK and inverted clock signal / CLK, and output to pre-row decoder 7.

In the address buffer 6, the input terminal of the inverter 601 is connected to the input line of the address information ADD0, and the output terminal is connected to the input terminal of the inverter 606 via the transfer gate 617. Inverter 60
The output terminal 6 is connected to the input terminals of the inverters 605 and 613. The output terminal of the inverter 605 is connected to the connection point between the transfer gate 617 and the input terminal of the inverter 606 via the transfer gate 618, and the inverter 605, 606 and the transfer gate 618 are connected.
Constitutes a latch circuit. The input terminal of the inverter 602 is connected to the input line of the address information ADD1, and the output terminal is connected to the input terminal of the inverter 608 via the transfer gate 619. The output terminal of inverter 608 is connected to the input terminals of inverters 607 and 614. The output terminal of the inverter 607 is connected to the transfer gate 619 and the inverter 6 via the transfer gate 620.
A latch circuit is formed by the inverter 607, 608 and the transfer gate 620. The input terminal of the inverter 603 is connected to the input line of the address information ADD2, and the output terminal is connected to the input terminal of the inverter 610 via the transfer gate 621. The output terminal of inverter 610 is connected to the input terminals of inverters 609 and 615. The output terminal of the inverter 609 is connected to the transfer gate 622.
Is connected to a connection point between the transfer gate 621 and the input terminal of the inverter 610 through the inverters 609 and 6.
10 and the transfer gate 622 form a latch circuit. The input terminal of the inverter 604 is the address information ADD3
Of the transfer gate 623
Through to the input terminal of the inverter 612. The output terminal of inverter 612 is connected to the input terminals of inverters 611 and 616. The output terminal of the inverter 611 is connected to the connection point between the transfer gate 623 and the input terminal of the inverter 612 via the transfer gate 624, and the inverter 611, 612 and the transfer gate 624 form a latch circuit.

The pre-row decoder 7 includes an inverter 701
720, two-input NOR gates 721 and 722, and two-input NAND gates 723 to 730,
A word line and a reference word line to be driven are decoded based on a mode signal MD1 indicating which mode of operation, 1Tr-1Cap mode or 2Tr-2Cap mode, and the output of the address buffer 6, and the result is converted to a word line. Output to the decoder 8 and the reference word line decoder 9.

In the pre-row decoder 7, the input terminal of the inverter 701 is connected to the inverter 6 of the address buffer 6.
13 is connected to the output terminal of the NOR gate 7
22 is connected to one input terminal. The other input terminal of the NOR gate 722 is connected to the input line of the mode signal MD1, and the output terminal is connected to the input terminal of the inverter 709. The output terminal of inverter 709 is NA
It is connected to one input terminal of ND gates 724, 726. One input terminal of the NOR gate 721 is connected to the input line of the mode signal MD1, the other input terminal is connected to the output terminal of the inverter 613 of the address buffer 6, and the output terminal is connected to the input terminal of the inverter 708. . The output terminal of the inverter 708 is N
It is connected to one input terminal of AND gates 723 and 725.

The inverters 702, 705, 71
0, inverters 703, 706, 711 and inverters 704, 707, 712 are connected in series.
The input terminal of the inverter 702 is connected to the output terminal of the inverter 614 of the address buffer 6, and the connection point between the output terminal of the inverter 705 and the input terminal of the inverter 710 is connected to the other input terminals of the NAND gates 723 and 724. ing. The output terminal of the inverter 710 is connected to the other input terminals of the NAND gates 725 and 726. The input terminal of the inverter 703 is connected to the output terminal of the inverter 615 of the address buffer 6, and the connection point between the output terminal of the inverter 706 and the input terminal of the inverter 711 is connected to one input terminal of the NAND gates 727 and 728. . An output terminal of the inverter 711 is connected to one input terminal of the NAND gates 728 and 730. The input terminal of the inverter 704 is connected to the output terminal of the inverter 616 of the address buffer 6, and the connection point between the output terminal of the inverter 707 and the input terminal of the inverter 712 is connected to the other input terminals of the NAND gates 727 and 729. . The output terminal of the inverter 711 is connected to the other input terminal of the NAND gates 728 and 730. Further, the NAND gate 723
730 to 730 are output terminals of inverters 713 to 72, respectively.
0 is connected to the input terminal.

The word line decoder 8 has three input NAND gates 801 to 816 and NAND gates 801 to 8
Inverter 8 connected in series to 16 output terminals
17 to 832, and outputs to the word line driver 10 a signal to be addressed and to drive a word line according to the operation mode, based on the output of the pre-row decoder 7 and the word control signal CTLWL.

The first input terminals of the NAND gates 801 to 816 are commonly connected to an input line of the word control signal CTLWL. Second of NAND gates 801 to 804
Are commonly connected to the output terminal of the inverter 717 of the pre-row decoder 7, and the NAND gates 805-8
08 (not shown) is connected to the output terminal of the inverter 718 of the pre-row decoder 7,
The second input terminals of the gates 809 to 812 (not shown) are connected to the output terminal of the inverter 719 of the pre-row decoder 7, and the second input terminals of the NAND gates 813 to 816 (not shown) are connected to the pre-row decoder. 7 inverters 72
0 output terminal. Then, the third input terminals of the NAND gates 801, 805, 809, 813 are connected to the output terminal of the inverter 713 of the pre-row decoder 7, and the NAND gates 802, 806, 810, 81
4 is connected to the output terminal of the inverter 714 of the pre-row decoder 7, and the NAND gate 803
The third input terminals of 807, 811, 815 are connected to the output terminal of the inverter 715 of the pre-row decoder 7,
The third input terminals of the AND gates 804, 808, 812, 816 are connected to the output terminal of the inverter 716 of the pre-row decoder 7.

The reference word line decoder 9 comprises four input NAND gates 901 and 902 and inverters 903 and 904 connected in series to the output terminals of the NAND gates 901 and 902. Reference word control signal CTLRW
Based on L and the mode line MD1, a signal to drive the addressed reference word lines RWL0 and RWL1 is output to the word line driver 10.

The first input terminals of the NAND gates 901 and 902 are commonly connected to the input line of the mode signal MD1, and the second input terminal is connected to the reference word control signal CT.
Commonly connected to LRWL input line. NAND
The third input terminal of the gate 901 is connected to the output terminal of the inverter 716 of the pre-row decoder 7, and the fourth input terminal is connected to the output terminal of the inverter 714. The third input terminal of the NAND gate 901 is connected to the output terminal of the inverter 715 of the pre-row decoder 7, and the fourth input terminal is connected to the output terminal of the inverter 713.

The word line driver 10 is connected to the outputs of the inverters 817 to 832 of the word line decoder 8 and the outputs of the inverters 903 and 904 of the reference word line decoder. When the output of each inverter is at a high level, the word line WL0 ～WL15, is constituted by a reference word line RWL0, RWL1-level power supply voltage V _CC level from the ground level of or (V _CC + alpha) is driven so that the level driver, 101 to 118. Specifically, the word lines WL0 to WL16 are connected to the output terminals of the drivers 101 to 116, and the driver 117
Is connected to a reference word line RWL1 and the output terminal of the driver 118 is connected to a reference word line RWL0.

Next, the operation of the above configuration will be described. 1
When selecting the Tr-1Cap configuration, the mode signal M
D1 is input to the NOR gate 721 of the pre-row decoder 7 at the ground level. Thereby, the NOR gate 721
Operates as an inverter. Therefore, the predecoder to which the least significant bit (ADD0) of the row address is input operates similarly to the other predecoders.

For example, as a 4-bit row address

When [0000] is input, the outputs of the inverters 713 and 717 of the pre-row decoder 7 become high level.
At this time, the word control signal CTLWL is supplied to the row decoder 8 at a high level. Therefore, in the row decoder 8, only the output of the NAND gate 801 goes high, and only the output of the inverter 817 goes high. As a result, the word line WL0 is driven (selected) to the predetermined level by the word line driver 10.

At the same time, at the time of reading, the reference word control signal CTLRWL is input to the reference word line decoder 9 at a high level. As a result, in this case, the output of the NOR gate 901 becomes high level,
The output of gate 902 goes low, and reference word line RWL0 is driven to a predetermined level.

Thereafter, the cell plate is driven to a predetermined level by the plate line driver 5, and one of the bit lines BL0L, BL1L,..., BL8L of the bit line pair receives the data of the memory cells M10 to M18 and the other bit line. B
Reference potentials from reference cells RM00 to RM08 are output to L0R, BL1R,..., BL8R. Then, the output potential difference of the bit line pair is
Data is output through the column gates 31L, 31R and -38L, 38R, which are amplified by .about.28 and controlled in conduction by the column decoder 4. As described above, 1Tr-1
Cap operation is realized.

On the other hand, when the 2Tr-2Cap configuration is selected, the mode signal MD1 is input to the NOR gate 721 of the pre-row decoder 7 at the power supply voltage _VDD level. As a result, the output of the NOR gate 721 always outputs a low level regardless of the least significant bit (ADD0) of the row address.

Therefore, for example, as a 4-bit row address

When [0000] is input, the outputs of the inverters 713, 714, and 717 of the pre-row decoder 7 become high level. At this time, the word control signal CTL
WL is supplied to the row decoder 8 at a high level. Therefore, in the row decoder 8, only the outputs of the NAND gates 801 and 892 go high, and only the outputs of the inverters 817 and 818 go high.
As a result, the word line driver 10 controls the word line WL0.
And WL1 are simultaneously driven (selected) to a predetermined level. At this time, the word lines selected at the same time must be word lines connected to memory cells having a common cell plate.

Thereafter, the cell plate is driven to a predetermined level by the plate line driver 5, and a pair of memory cells selected by the two word lines WL0, WL1 and the column decoder 4, for example, a bit line pair from M00, M10. BL
The differential data is output to 0L and BL0R. In the case of the 2Tr-2Cap operation, since the reference cell does not need to be operated, the reference word line decoder 9 is controlled to the disabled state by the mode signal MD1.

In the 2Tr-2Cap configuration, since data is differentially output to the bit line pair, 1Tr-1Cap
The potential difference between the pair of bit lines can be made larger than in the case of the p configuration, so that high-speed / stable operation is possible. On the other hand, the memory capacity is の of the 1Tr-1Cap configuration. Therefore, depending on the application, the 2Tr-2Cap configuration can be easily selected when importance is placed on high reliability and high speed, and the 1Tr-1Cap configuration can be easily selected when importance is placed on capacity.

As described above, according to the present embodiment, the address information ADD0-AD for writing and reading is used.
D3 is a clock signal CLK and an inverted clock signal / C
Address buffer 6 which latches in accordance with LK and outputs it to pre-row decoder 7, 1Tr-1Cap mode or 2T
A word line to be driven and a reference word line are decoded based on a mode signal MD1 indicating which mode of the r-2Cap mode is to be operated, and an output of the address buffer 6, and the results are decoded into a word line decoder 8 and a reference word. A pre-row decoder 7 that outputs to the line decoder 9, and a signal to be addressed and to drive a word line corresponding to an operation mode is output to the word line driver 10 based on the output of the pre-row decoder 7 and the word control signal CTLWL. And the output of the pre-row decoder 7 and the reference word control signal CTL.
A reference word line decoder 9 for outputting a signal to drive the addressed reference word lines RWL0 and RWL1 to the word line driver 10 based on the RWL and the mode line MD1, and outputs of the invers 817 to 832 of the word line decoder 8. And the outputs of the inverters 903 and 904 of the reference word line decoder,
When the output of each inverter is at a high level, the word line W
L0 to WL15, reference word lines RWL0, RW
L1 power supply voltage V _CC level the level from the ground level, or is provided with the word line driver 10 for driving so as to (V _CC + alpha) level, the level of the mode signal MD1 is an external signal supply voltage V _DD By switching to the ground or ground level, the 2Tr-2Cap configuration can be used if high reliability or high speed is important, depending on the application.
When capacity is important, the 1Tr-1Cap configuration can be easily selected. In addition, a so-called external 1Tr-
The 1Cap / 2Tr-2Cap switching terminal is connected to the power supply voltage V
_By simply fixing to either _DD or ground level, the mode is automatically switched internally, which has the advantage that control is easy. In the case of the 2Tr-2Cap configuration, data is differentially output to the bit line pair, so that the potential difference between the bit line pairs can be made larger than in the case of the 1Tr-1Cap configuration, thereby enabling high-speed / stable operation. In the case of a 1Tr-1Cap configuration, the memory capacity is 2Tr.
2 times that of the 2Cap configuration.

[0051]

As described above, according to the present invention,
If high reliability or high speed is important for the application, 2
When the capacity is important for the Tr-2Cap configuration, 1Tr
-1Cap configuration can be easily selected. 2Tr
In the case of the -2Cap configuration, data is differentially output to the bit line pair, so that the potential difference between the bit line pairs can be made larger than in the case of the 1Tr-1Cap configuration, thereby enabling high-speed / stable operation. On the other hand, the memory capacity is 1Tr-1C
In the case of the ap configuration, it is twice that in the 2Tr-2Cap configuration. Also, for example, external 1Tr-Cap, 2Tr-2
Simply fixing the Cap switching terminal to one of the high level and the low level automatically switches the mode internally, thereby providing an advantage that control becomes easy.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a ferroelectric memory device according to the present invention.

FIG. 2 is a diagram illustrating a hysteresis characteristic of a ferroelectric capacitor.

FIG. 3 is a diagram showing a basic 1-bit configuration of a nonvolatile memory employing a 2Tr-2Cap method.

FIG. 4 is a timing chart of a potential applied to each terminal at the time of writing in a ferroelectric nonvolatile memory employing a 2Tr-2Cap method.

FIG. 5 is a timing chart of a potential applied to each terminal when reading out a ferroelectric nonvolatile memory employing the 2Tr-2Cap method.

FIG. 6 is a diagram showing a basic 1-bit configuration of a nonvolatile memory employing a 1Tr-1Cap method.

FIG. 7 is a timing chart of the potential applied to each terminal at the time of writing in the ferroelectric nonvolatile memory employing the 1Tr-1Cap method.

FIG. 8 is a timing chart of a potential applied to each terminal when reading out a ferroelectric nonvolatile memory employing the 1Tr-1Cap method.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... memory cell array, 2 ... sense amplifier group, 3 ... column gate group, 4 ... column decoder, 5 ... plate line driver, 6 ... address buffer, 7 ... pre-row decoder,
8 Word line decoder, 9 Reference word line decoder, 10 Word line driver, 11 Word line boost circuit 11, WL0 to WL15 Word line, RWL0,
RWL1: Reference word line, BL0L, BL0
R, BL1L, BL1R, BL7L, BL7R, BL8
L, BL8R: bit line, PL0 to PL7: plate line, RPL: reference plate line, Tr: switching transistor, RTr: switching transistor for reference, FC: ferroelectric capacitor, RFC ...
Reference ferroelectric capacitors, M00 to M158 ... basic memory cells, RM00 to RM18 ... reference basic memory cells.

Claims (5)

[Claims] 1. A ferroelectric capacitor for storing binary data according to a polarization direction of a ferroelectric according to a voltage applied to first and second electrodes, and a bit line according to a word line level. A memory cell array is formed by arranging basic memory cells each including a switching transistor that switches between an electrically conductive state and a non-conductive state with a first electrode of a ferroelectric capacitor, and forms a memory cell array. A dielectric memory device, comprising: activating one word line according to an address designation in a first operation mode, and activating two word lines according to an address designation in a second operation mode. In the first operation mode, at least one of the basic memory cells connected to the word line activated by the first circuit and addressed. A predetermined level of voltage is applied at a predetermined timing to the second electrode of the dielectric capacitor,
In the second operation mode, a predetermined level of voltage is applied to at least each second electrode of the ferroelectric capacitor in the addressed basic memory cell, which is connected to each of the two word lines activated by the first circuit. And a second circuit for applying the same at a predetermined timing. 2. The first circuit according to claim 1, wherein the first circuit is connected to an external signal.
2. The ferroelectric memory device according to claim 1, wherein switching between selecting one word line and selecting two word lines is performed. 3. The ferroelectric memory device according to claim 1, wherein said memory cell array has a structure based on a folded bit line system in which data is read and written by a potential difference between two paired bit lines. 4. The switching transistor of an even-numbered basic memory cell in the same column is connected to a first bit line, and the switching transistor of an odd-numbered basic memory cell is connected to a second bit line. 4. The ferroelectric memory according to claim 3, wherein the second electrodes of the ferroelectric capacitors of the even-numbered and odd-numbered basic memory cells are connected to a common plate line, and wherein the second circuit applies a predetermined voltage to the plate line. Dielectric storage device. 5. A ferroelectric capacitor for storing binary data according to a polarization direction of a ferroelectric according to a voltage applied to first and second electrodes, and a bit line according to a level of a reference word line. A switching transistor for switching between an electrically conductive state and a non-conductive state with the first electrode of the ferroelectric capacitor, the selected basic memory cell being connected to a bit line paired with the connected bit line; 4. The ferroelectric memory according to claim 3, comprising: a reference basic memory cell; and a third circuit that activates the reference word line in a first operation mode and holds the reference word line in an inactive state in a second operation mode. apparatus.