JPH1079402A - Semiconductor package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor package, capable of reducing chip size without reducing the number of external connection terminals. SOLUTION: A semiconductor package is formed by a semiconductor chip 2 on which a plurality of electrode pads 3 is formed, an insulation film 7 layered on a lead pattern 6 with an external size of the film being larger than an external size of the chip, a wiring film 5, consisting of the first wiring area 5a, an inner area of the film opening 8, the second wiring area 5b, an outer area of the film opening 8 which is along a chip circumference, a plurality of external connection terminals 9 formed over the first and second wiring areas 5a and 5b, a plurality of leads 10 extending from the first and second wiring areas 5a and 5b to the film opening 8 and connected to the electrode pad 3, and has a sealing resin 12 between the semiconductor chip 2 and an external ring 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package having a super lead structure by joining a semiconductor chip to a novel lead frame.

[0002]

2. Description of the Related Art FIG. 7 shows a conventional semiconductor package that can be mounted on a printed wiring board or the like via an organic substrate having external connection terminals such as solder balls. In FIG. 7, a semiconductor chip 51 is mounted on the surface of a multi-layer organic wiring substrate 50 of about 2 to 6 layers using an organic material. The electrode pads of the semiconductor chip 51 and the wiring film 52 formed on the surface of the multilayer organic wiring substrate 50 are connected by wire bonding using gold wires 53 or the like.

A solder ball (external connection terminal) 55 that is electrically connected to the wiring film 52 on the front surface through a through hole 54 is provided on the back surface of the multilayer organic wiring board 50. It faces outside from the opening of the solder resist film 56. The semiconductor chip 51 is sealed together with the gold wire 53 by a sealing resin 57.

[0004] In the semiconductor package 58 having the above structure, the solder balls 55 formed on the back surface are connected to the printed wiring board 59. Further, the multilayer organic wiring board 50 is often called a ball grid array (BGA) because a large number of solder balls 55 are arranged in a grid pattern. It is called a BGA package.

[0005]

However, in the above-mentioned conventional semiconductor package 58, since the electrode pads of the semiconductor chip 51 and the wiring film 52 of the multilayer organic wiring substrate 50 are connected by wire bonding, the wiring pitch is reduced. There was a limit to reducing the size of Also, in other semiconductor packages called, for example, TCP (tape carrier package), a lead pattern is formed by etching a copper foil attached on an insulating film base. Therefore, there is a limit in increasing the number of pins.

Therefore, the present applicant has already proposed a semiconductor package having a super multi-pin structure by joining a novel lead frame and a semiconductor chip. FIG. 8 shows an example of a semiconductor package having a super multi-pin structure, and a manufacturing procedure thereof will be briefly described below. First, in manufacturing a lead frame, as shown in FIG. 9A, a metal base 61 having a three-layer structure is prepared. This metal base 61
A substrate made of copper or a copper alloy (hereinafter, referred to as a copper substrate) 62
Is formed by forming an aluminium film 63 on the surface thereof and forming a nickel film 64 thereon. Next, as shown in FIG. 9B, a plurality of lead patterns 65 are formed on the surface of the metal base 61 by electrolytic copper plating. Next, FIG.
As shown in (c), a slit 66 for defining the outer shape of each chip of the lead frame is formed. Next, FIG.
As shown in FIG. 3D, an insulating film 67 is laminated on the lead pattern 65, thereby forming the lead pattern 65.
Then, a wiring film 68 including the insulating film 67 is formed. A plurality of leads 69 extend from the wiring film 68 corresponding to the lead patterns 65.

Next, as shown in FIG. 10A, an external connection terminal 70 is formed on the lead pattern 65 covered with the insulating film 67 by electrolytic plating. Next, as shown in FIGS.
The copper substrate 6 of the metal base 61 is left so as to leave one portion.
2. The aluminum film 63 and the nickel film 64 are sequentially removed by selective etching, respectively, whereby the lead patterns 65 (including the leads 69) are separated and made independent. Next, as shown in FIG. 10D, bumps 7 are attached to the tips of the leads 69 extending from the wiring film 67.
Form 2 Thus, the lead frame 73 before the mounting of the semiconductor chip is completed.

Thereafter, when assembling the semiconductor chip to the lead frame 73, the semiconductor chip 75 is positioned and fixed to the back surface of the wiring film 68 via an adhesive sheet 74 as shown in FIG. Next, FIG.
As shown in FIG. 1B, the tip of each lead 69 is connected to the electrode pad 76 of the semiconductor chip 75 via the bump 72. Next, as shown in FIG. 11C, a sealing resin 77 is injected between the semiconductor chip 75 and the outer ring 71, and the sealing resin 77 is cured to integrate peripheral components. Lastly, as shown in FIG. 11D, unnecessary portions are cut off at the outer peripheral edge of the outer ring 71 to complete the semiconductor package 78 having the super multi-pin structure shown in FIG.

In this semiconductor package 78, at the stage of manufacturing the lead frame 73, a lead pattern 68 is formed on the metal base 61 by electrolytic copper plating, and the external connection terminals 70 are formed on the lead pattern 65 by electrolytic plating. , A multi-pin structure exceeding the limit up to that point has been realized. Further, since the metal base 61 is selectively etched to leave the outer ring 71 and the outer ring 71 forms the outer shape of the package, the positional accuracy between the outer shape of the package and the external connection terminals 70 is guaranteed. This facilitates alignment during package mounting. Further, a so-called CSP (chip size package) structure in which the package size is kept at the same level as the chip size has also been realized.

However, in the case of the semiconductor package 78 described above, the wiring film 65 is mounted on the semiconductor chip 75 via the adhesive sheet 74, and the external connection terminals 70 are formed on the wiring film 65. There were the following inconveniences. That is, the external connection terminal 70
Is reduced to the limit level, the number of external connection terminals 70 that can be provided on the wiring film 65 is limited by the size of the semiconductor chip 75.
Therefore, in order to reduce the chip size, the number of the external connection terminals 70 must be reduced, and as a result, the number of external connection terminals 70 is reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor package capable of reducing the chip size without reducing the number of external connection terminals. It is in.

[0012]

SUMMARY OF THE INVENTION The present invention has been made to achieve the above-mentioned object, and comprises a semiconductor chip having a plurality of electrode pads formed on a peripheral portion of a chip surface; It is arranged and formed, and has a structure in which an insulating film is laminated on the lead pattern. The outer dimensions of the film are set to be larger than the outer dimensions of the semiconductor chip, and a film opening along the periphery of the semiconductor chip is provided. A wiring film having a first wiring region inside the film opening and a second wiring region outside the film opening, and a wiring extending from the first wiring region to the second wiring region. A plurality of external connection terminals protrudingly formed on the film, extending from the first wiring region and the second wiring region to the film openings, respectively; A plurality of leads whose extending ends are connected to the electrode pads of the semiconductor chip, an outer ring provided so as to surround the semiconductor chip, and a sealing resin filled between the semiconductor chip and the outer ring. Is provided.

In the semiconductor package having the above configuration,
The wiring area of the wiring film is expanded to the first wiring area arranged on the semiconductor chip and to the second wiring area arranged at the periphery of the chip, and external connection is made over these first and second wiring areas. Since the terminals are formed, the number of external connection terminals on the wiring film is not limited by the chip size. Therefore, it is possible to reduce the chip size without reducing the number of external connection terminals.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a side sectional view showing an embodiment of a semiconductor package according to the present invention, and FIG. 2 is a bottom view of a main part thereof. In the configuration of the semiconductor package 1 shown in the drawing, a plurality of electrode pads 3 are formed on the surface of the semiconductor chip 2 (the lower surface of the chip in FIG. 1) over the periphery thereof. A wiring film 5 is arranged and formed on the front surface side (pad formation surface side) of the semiconductor chip 2 via an adhesive sheet 4. This wiring film 5
Has a structure in which an insulating film 7 is laminated on a lead pattern 6, and the outer dimensions of the film are set larger than the outer dimensions of the semiconductor chip 2. The wiring film 5 is provided with a film opening 8 along the periphery of the chip. This film opening 8 is
The tip of a lead described later is connected to the electrode pad 3 of the semiconductor chip 2.
This serves as a so-called bond hole for connection to the semiconductor chip 2, and is formed in a slit shape following the pad arrangement on the semiconductor chip 2.

The adhesive sheet 4 has a thickness of, for example, 150
It is made of a thermoplastic polyimide adhesive sheet or a polyolefin-based adhesive sheet having a thickness of about μm. In addition to bonding the semiconductor chip 2 and the wiring film 5, the semiconductor chip 2
, Which also exists inside the pad formation region and serves as a buffer material for protecting the element formation region.

In the wiring film 5 described above, the first wiring region 5a is located on the inner side of the film opening 8 and the second wiring region 5b is located on the outer side. . The first wiring region 5a and the second wiring region 5b are connected to each other at abutting portions of the film openings 8. That is, as shown in FIG. 2, the abutting portion of each film opening 8 is hung by a part 7a of the insulating film 7, and a hanger lead 6a is laid over the hung portion to reinforce it. . Also, on the wiring film 5, a plurality of external connection terminals 9 extend from the first wiring region 5a to the second wiring region 5b.
Are formed. Each external connection terminal 9 is located at the end (land) of the above-described lead pattern 6, and is formed to project, for example, in a ball shape. Incidentally, dummy ball-shaped protrusions 9a having the same structure as the external connection terminals 9 are also provided at both ends of the above-mentioned suspension leads 6a, and both ends of the suspension leads 6a are insulated by the rivet action of the ball-shaped protrusions 9a. It is fastened to 7.

Further, a plurality of leads 10 extend from the first wiring region 5a and the second wiring region 5b toward the film opening 8, respectively. These leads 10 correspond to the lead patterns 6 formed in the first and second wiring regions 5a and 5b, and correspond to the first wiring regions 5a and 5b.
The lead 10 extends from a to the outside of the package,
Leads 10 extend from the second wiring region 5b toward the inside of the package. The extending end (tip) of each lead 10 is connected to an electrode pad 3 formed on the semiconductor chip 2. Incidentally, a support lead 10a (FIG. 2) serving as a dummy which is not involved in circuit connection is bridged in an appropriate place of each film opening 8 separately from the above-mentioned lead 10. The support lead 10a is for connecting and supporting the first wiring region 5a and the second wiring region 5b, like the suspension lead 6a described above.

On the other hand, outside the semiconductor chip 2, an outer diameter ring 11 is provided so as to surround the semiconductor chip 2. The outer ring 11 is provided with the wiring film 5 (the second wiring area 5b).
Are formed in a ring shape along the periphery of the semiconductor package 1, thereby forming the outer shape of the semiconductor package 1. Further, an epoxy-based or silicone-based sealing resin 12 is filled between the semiconductor chip 2 and the outer diameter ring 11, and peripheral components are integrally fixed by the sealing resin 12.

Incidentally, the second wiring area 5b of the wiring film 5 is provided with an adhesive sheet 4a of the same quality as the adhesive sheet 4 described above.
Is pasted. The adhesive sheet 4a is used to reduce environmental stress (mainly thermal stress) during and after mounting the package on a printed circuit board (not shown). What is necessary is just to provide it suitably in consideration of flexibility etc.

Next, a series of manufacturing procedures of the semiconductor package 1 in the present embodiment will be described with reference to FIGS. First, in manufacturing a lead frame, as shown in FIG. 3A, a metal base 21 made of a laminated plate having a three-layer structure is prepared. This metal base 21
An aluminum film 23 having a thickness of about 4.5 μm is formed on the surface of a substrate (hereinafter, referred to as a copper substrate) 22 made of copper or a copper alloy having a thickness of about 150 μm, for example, by vapor deposition. The film 24 is formed.

Of these, the copper substrate 22 does not itself become a lead, but is eventually cut away except for an outer ring portion (described later). However, in forming a very fine lead pattern, Indispensable. The aluminum film 23 corresponds to an etching stop film for preventing the surface side of the metal base 21 from being etched when the copper substrate 22 is etched in a subsequent step. The nickel film 24 corresponds to a base for electrolytic plating for forming a lead pattern on the surface of the metal base 21, that is, a plating base film.

As the metal base 21, for example, a chromium film having a thickness of about 0.5 μm is formed as an adhesion film between the aluminum film 23 and the nickel film 24 in order to enhance the adhesion between them. Is also good. Further, a thin copper film may be formed instead of the nickel film 24 as the plating base film.

Next, as shown in FIG. 3B, a plurality of lead patterns 6 made of, for example, copper having a thickness of 20 to 30 μm are formed on the surface of the metal base 21, ie, the surface of the nickel film 4 by selective plating. I do. The selective plating here is performed by selectively covering the surface of the metal base 21 with a resist pattern (not shown) and performing electrolytic copper plating using the resist pattern as a mask. At this time, the formation region of the lead pattern 6 using the resist pattern as a mask is set to be larger than the bonding region of the semiconductor chip 2 described later. In forming the lead pattern 6, the suspension lead 6a and the support lead 1 shown in FIG.
0a is also formed at the same time.

Next, as shown in FIG. 3C, an insulating film 7 made of, for example, a polyimide film having a thickness of about 25 μm is laminated on the lead pattern 6 formed by electrolytic copper plating. Then, the wiring film 5 including the insulating film 7 is formed. At this time, by patterning the insulating film 7 using a well-known photolithography technique, a film opening 8 for lead bonding is formed together with small holes for plating the external connection terminals 9 described later. At this time, the wiring film 5 is divided into a first wiring region 5a and a second wiring region 5b, and a plurality of leads 10 extend from each of the regions 5a and 5b toward the film opening 8. Become. Next, as shown in FIG. 3D, the metal base 21 is selectively etched from both sides to form a slit 2 for defining the outer shape of each chip of the lead frame.
5 and holes (not shown) for facilitating manufacture.

Subsequently, as shown in FIG. 4A, a ball-shaped external connection terminal 9 is formed at the end of the lead pattern 6 covered with the insulating film 7 using the insulating film 7 as a mask. The external connection terminals 9 are formed by forming a nickel core of about 90 μm by electrolytic plating at the end of the lead pattern 6 exposed on the insulating film 7 and subjecting the core surface to gold plating of 0.1 μm, Alternatively, it can be obtained by forming a nickel core of about 80 μm by electrolytic plating and applying a solder plating of about 20 μm to the surface of the core.

Subsequently, as shown in FIG. 4B, the copper substrate 22 of the metal base 21 is removed by selective etching so that the outer ring 11 is left. During this etching, the aluminum film 23 acts as an etching stopper, and only the copper substrate 22 is removed. next,
As shown in FIG. 4C, the aluminum film 23 of the metal base 21 is removed by selective etching, and the nickel film 24 is further removed by selective etching to separate each lead pattern 6 (including the lead 10). Let it. Next, as shown in FIG.
A bump 26 made of aluminum is formed at the tip of each lead 10 extending from the second wiring regions 5a and 5b by, for example, a sputtering method or an evaporation method. Thus, the lead frame 27 before the mounting of the semiconductor chip is completed.

Thereafter, when assembling the semiconductor chip to the lead frame 27, as shown in FIG. 5A, the semiconductor chip is placed on the back side of the wiring film 5 (first wiring region 5a) via the adhesive sheet 4. The chip 2 is positioned and fixed. At this time, the first wiring region 5a of the wiring film 5 is arranged on the semiconductor chip 2, and the second wiring region 5b is arranged on the periphery of the chip. Also, the tips (bumps 2) of the leads 10 extending from the first and second wiring regions 5a and 5b are provided.
6) is in a state of facing the electrode pad 3 on the semiconductor chip 2. Next, as shown in FIG. 5B, the tips of the respective leads 10 are connected to the electrode pads 3 of the semiconductor chip 2 via the bumps 26 by single point bonding. This single point bonding is performed via the film opening 8 of the wiring film 5. Then
As shown in FIG. 5C, an epoxy-based or silicone-based sealing resin 1 is provided between the semiconductor chip 2 and the outer ring 11.
2 is injected by potting, and this is cured to integrate peripheral components. Finally, as shown in FIG. 5D, unnecessary portions are cut off at the outer peripheral edge of the outer ring 11 to complete the semiconductor package 1 shown in FIG.

As described above, in the semiconductor package 1 of the present embodiment, the wiring region of the wiring film 5 is added to the first wiring region 5a provided on the semiconductor chip 2 and the second wiring region 5a provided on the periphery of the chip. To the wiring area 5b of
Since the external connection terminals 9 are formed over the respective wiring regions 5a and 5b, the number of the external connection terminals 9 is not limited by the chip size. Therefore, the size of the semiconductor chip 2 can be reduced without reducing the number of the external connection terminals 9.

The arrangement of the external connection terminals 9 in the second wiring region 5b can be set arbitrarily according to the desired number of terminals. However, as the terminal arrangement increases, the second wiring region 5b increases accordingly. Therefore, there is a concern that the flexure or undulation of the film becomes remarkable and the height of the external connection terminals 9 becomes uneven. In the following, another embodiment of the present invention made to solve such a concern will be described.

FIG. 6 is a side sectional view showing another embodiment of the semiconductor package according to the present invention. In the illustrated semiconductor package 1, as a characteristic portion, a reinforcing plate 13 is attached to a second wiring region 5 b of the wiring film 5 via an adhesive sheet 4 a. The reinforcing plate 13 is made of a metal material such as aluminum, for example, and is incorporated between the semiconductor chip 2 and the outer ring 11.
The thickness of the adhesive sheets 4 and 4a is set to be the same so that the back surface (upper surface in the drawing) of the reinforcing plate 13 and the chip back surface are flush with each other, and the thickness of the reinforcing plate 13 is the same as that of the semiconductor chip 2. Is set to Then, between the semiconductor chip 2 and the outer ring 11, the inside and outside of the reinforcing plate 13 are filled with the sealing resin 12.

In the semiconductor package 1, since the second wiring region 5b located at the peripheral portion of the chip is supported by the reinforcing plate 13, bending and undulation of the film in the second wiring region 5b are suppressed. Therefore, even if the terminal arrangement in the second wiring region 5b increases, the wiring film 5
The height of the external connection terminal 9 above can be kept uniform. In addition, since the back surface of the reinforcing plate 13 and the back surface of the chip are flush with each other, the semiconductor chip 2 and the reinforcing plate 13 are placed on the same reference plane when assembling the package. Wiring film 5 through 4a
It is possible to make the heights of the external connection terminals 9 on the wiring film 5 uniform and highly accurate by a simple operation such as pasting.

The present invention is not limited to the case where the lead pattern is formed by electrolytic copper plating as described above, but a copper foil is attached on an insulating film of polyimide or the like, and this is etched to form the lead pattern. The same can be applied to the above.

[0033]

As described above, according to the present invention, the wiring area of the wiring film (the area where the external connection terminals are formed) is reduced.
Since the first wiring region arranged on the semiconductor chip is expanded to the second wiring region arranged on the periphery of the chip in addition to the first wiring region, the chip size is reduced without reducing the number of external connection terminals. be able to. As a result, it is possible to sufficiently cope with future miniaturization of semiconductor chips. At the same time, the number of external connection terminals can be increased without increasing the size of the semiconductor chip, which is effective in further increasing the number of pins.

[Brief description of the drawings]

FIG. 1 is a side sectional view showing one embodiment of a semiconductor package according to the present invention.

FIG. 2 is a bottom view of an essential part showing one embodiment of a semiconductor package according to the present invention.

FIG. 3 is a manufacturing process diagram (part 1) of the lead frame in the embodiment.

FIG. 4 is a manufacturing process diagram (part 2) of the lead frame in the embodiment.

FIG. 5 is a manufacturing process diagram of the semiconductor package in the embodiment.

FIG. 6 is a side sectional view showing another embodiment of the semiconductor package according to the present invention.

FIG. 7 is a side sectional view showing a conventional BGA package.

FIG. 8 is a side sectional view showing an example of a semiconductor package having a super multi-pin structure.

FIG. 9 is a manufacturing process diagram (part 1) of a lead frame for a super multi-pin structure.

FIG. 10 is a manufacturing process diagram (part 2) of a lead frame for an ultra-multi-pin structure.

FIG. 11 is a manufacturing process diagram of a semiconductor package for a super multi-pin structure.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor package 2 semiconductor chip 3 electrode pad 5 wiring film 5a first wiring area 5b
Second wiring area 6 Lead pattern 7 Insulating film 8 Film opening 9 External connection terminal 10 Lead 11 Outer ring 12 Sealing resin 13 Reinforcement plate

Claims (2)

[Claims] A semiconductor chip having a plurality of electrode pads formed on a peripheral portion of a surface of the chip; a semiconductor chip disposed on a surface side of the semiconductor chip;
It has a structure in which an insulating film is laminated on a lead pattern, the outer dimensions of the film are set to be larger than the outer dimensions of the semiconductor chip, and a film opening is provided along a peripheral portion of the semiconductor chip, and A wiring film having a first wiring region inside the film opening and a second wiring region outside the film opening; and a wiring film extending from the first wiring region to the second wiring region. A plurality of external connection terminals protruding from the first wiring region and the second wiring region, each extending to the film opening, and having an extended end connected to the electrode pad of the semiconductor chip. A plurality of leads, an outer ring provided so as to surround the semiconductor chip, and a space between the semiconductor chip and the outer ring. And a sealing resin. 2. The semiconductor package according to claim 1, wherein a reinforcing plate is joined to the second wiring region of the wiring film between the semiconductor chip and the outer ring.