JPH1063641A - Product sum circuit with shift - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a product sum circuit capable of simultaneously executing product sum operation and arithmetic shift processing in one machine cycle. SOLUTION: The product sum circuit is connected to 1st to 3rd regiters for storing data and provided with a 1st shifting circuit 21 for executing the arithmetic left shift of 1st input data outputted from the 1st register by '0' or prescribed bits in accordance with a 1st shift control signal, a multiplier 22 for executing multiplying operation between 2nd input data from the 2nd register and the output of the 1st shift circuit, an adder 23 for adding 3rd input data from the 3rd register to the multiplied output of the multiplier 22, and a 2nd shifting circuit 24 for executing the arithmetic right shift of the output of the adder 23 by '0' or prescribed bits in accordance with a 2nd shift control signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a product-sum circuit used in a digital signal processor (DSP) or the like.
The present invention relates to an improvement of a multiply-accumulate circuit capable of performing an accurate and high-precision operation with a small number of instruction cycles.

[0002]

2. Description of the Related Art Various product-sum circuits have been proposed in which a multiplier for obtaining a product of a multiplier and a multiplicand and an adder for obtaining a sum of the result of the multiplication and the result of the next multiplication are combined. In particular, DSP
The product-sum circuit provided therein is generally a combination of a multiplication circuit using a Booth algorithm and a normal addition circuit.

Such a product-sum circuit is central in recent multimedia-related technologies because it is necessary to perform product-sum operations many times in compression processing and the like.

[0004] On the other hand, in a multiplication circuit in such a DSP, it is general practice to make the data format correspond to a fixed point composed of a sign bit and bits below the decimal point. By adopting such a data format, any numerical data can be represented by -1 or more and less than +1 and the hardware can be simplified.

In order to perform the multiplication operation with higher accuracy,
DSPs are required to be able to perform double precision calculations. In the double precision operation, it is necessary to perform a product-sum operation such as obtaining a partial product and then obtaining a sum thereof in order to multiply a multiplicand of a normal double bit number and a multiplicand.

[0006]

However, in the case of a fixed-point data format, for numerical data of 1 or more or numerical data smaller than -1, once -1 to 1 is set.
In order to normalize to the range of +1, the multiplicand corresponding to the numerical data corresponding to 、, ４, １ ／ is read from the table, multiplied, and then multiplied by 2, 4, and 8 again. Normalization processing is required. Since the denormalization of the numerical data can be realized by a kind of data bit shift, the operation result is shifted by a corresponding shift amount by a shift circuit.

In addition, in the operation with double precision, a step of shifting data bits is necessary in order to perform digit alignment of a partial product. After the digit alignment of the partial product, the sum with the other partial products is obtained.

Therefore, using a conventional multiply-accumulate circuit, it is possible to multiply numerical data that does not fit in the data format,
When performing an operation with double precision, it is necessary to frequently execute a data shift instruction, and a DS in which such an operation frequently occurs.
In P, the number of instructions increased.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multiply-accumulate circuit capable of realizing a more accurate and accurate operation with a small number of instructions.

Another object of the present invention is to provide a product-sum circuit in which a shift circuit is optimized and added.

[0011]

SUMMARY OF THE INVENTION According to the present invention, there is provided an electronic apparatus comprising: first, second, and third registers for holding data, and receiving first input data from the first register; A first shift circuit that performs arithmetic left shift of 0 or a predetermined bit in accordance with a first shift control signal, and performs a multiplication operation on second input data from the second register and an output of the first shift circuit. This is achieved by providing a multiply-accumulate circuit, comprising: a multiplication circuit; and an addition circuit that performs an addition operation of the third input data from the third register and the multiplication output of the multiplication circuit. .

Further, according to the present invention, the above object is achieved by connecting first, second, and third registers for holding data, wherein the first input data from the first register and the second A multiplication circuit that performs a multiplication operation with the second input data from the register, an addition circuit that performs an addition operation of the third input data from the third register and the multiplication output of the multiplication circuit, A second shift circuit for arithmetically shifting the output of the circuit by 0 or a predetermined bit arithmetically right in accordance with a second shift control signal.

The present invention further achieves the above object by a sum-of-products circuit having both the first and second shift circuits.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. However, the technical scope of the present invention is not limitedly interpreted by such embodiments.

FIG. 1 shows a DS according to an embodiment of the present invention.
It is a schematic block diagram of P. In the DSP of FIG. 1, the program counter PC is supplied with the system clock CLK and counts up in a machine cycle. The output of the program counter PC is given as an address to the ROM in which the instruction code is stored. The instruction code corresponding to the address from the ROM is stored in the instruction register IR.
0, IR1, and their instruction codes are decoded by the decoder DEC to supply control signals to each block.

The AALUs 1 and 2 are address operation circuits for calculating the addresses of the memory RAMs 1 and 2, and the data of the memory RAMs 1 and 2 corresponding to the addresses calculated by the ALUs 1 and 2 pass through the A bus Abus and the B bus Bbus. The result is stored in the registers reg 1 and reg 2, multiplied by the product-sum circuit 10, added to the value in the register reg 3, and the final operation result is stored in the register reg 3.

Instruction registers IR0, IR
By providing two 1s, pipeline processing becomes possible. Further, since two buses Abus and Bbus are provided, two memory RAMs are provided in one machine cycle.
It becomes possible to transfer two data simultaneously from 1,2 to two registers reg1,2.

FIG. 2 is a block diagram of the memory RA by the DSP of FIG.
FIG. 11 is a timing flowchart in a case where a multiplier in M1 is multiplied by a multiplicand in a memory RAM2 to add a value in a register reg3. In this example, when the program counter PC is n-1, the instruction code "Transfer data from the memory RAM1 to the register reg1" is read from the instruction memory ROM, and the instruction register IR0 is read in the next machine cycle (n).
To be stored. At the same time, the instruction code "Transfer data from memory RAM2 to register reg2" in the memory ROM is read according to n of the program counter PC, and stored in the instruction register IR0 in the next machine cycle (n + 1). At that time, the first instruction code is transferred to the instruction register IR1.

In the machine cycle (n + 1), the decoder D
Address operation circuit AALU according to control signal from EC
1, an address is calculated, an address value for the memory RAM1 is generated, and in a machine cycle (n + 2), a multiplier data corresponding to the address value is stored in the register reg1.
Given to. Similarly, the multiplicand is stored in the register reg2 in the next machine cycle.

In the machine cycle (n + 3), the accumulator 1
In 0, the multiplication operation of the data in the registers reg1 and 2 and the addition operation of the register reg3 are executed, and the final operation result is stored in the register reg3.

By simultaneously using the two buses Abus and Bbus, the registers res
Two data can be simultaneously transferred to g1 and g2. In that case, it can be reduced by one machine cycle as compared with the example of FIG.

FIG. 3 is a diagram for explaining an example in which data is formatted in a fixed point. (A) of the figure shows the data format, which is composed of a sign bit S and a bit indicating a decimal part. Therefore, in the example of this data format, the range of numerical values that can be expressed is −1 or more and less than +1.

FIG. 2B illustrates a process in which a multiplicand D2 of +1 or more, which cannot be handled by such a data format, is raised to the multiplier data D1. In this example, the multiplicand D2 is multiplied by 1/4 and a coefficient normalized so as to be adaptable to the data format is used. Normally, coefficient data corresponding to the multiplicand is read out from a coefficient table stored in a ROM or the like and supplied to the product-sum circuit. After multiplication of both data D1 and D2, the data is multiplied by 4 for denormalization. Specifically, the final data D3 (s) is obtained by shifting leftward by 2 bits.
This shift is called arithmetic left shift processing. Therefore, arithmetic left shift processing is required by the number of bits at the time of the first normalization.

As described above, in order to calculate a number which cannot correspond to the data format in the product-sum unit 10, a coefficient normalized from the above-described coefficient table is given to the product-sum unit 10, multiplied, and then denormalized. Is performed, and an addition operation is further performed. Therefore, it is necessary to additionally execute arithmetic left shift processing for denormalization as a program instruction.

FIG. 4 is a diagram for explaining the case of multiplying double precision data. Double-precision data is, for example, data composed of 20 bits, but composed of 40 bits, which is twice the number of bits. When multiplying these data using a product-sum circuit configured for 20-bit data, as shown in FIG. 4, the data Da is divided into 20-bit data A1 and A2, and the data Db is also 20 bits. The data is divided into bit-by-bit data B1 and B2, and the respective partial products are added. That is, the partial products A0 × B0, A1
× B0, A0 × B1, and A1 × B1 are added after performing necessary digit alignment. Therefore, the partial product A0 ×
B0 needs to be shifted to the right by 20 bits to perform digit alignment, and the partial products A0 × B0, A1 × B0, A0 × B1
It is necessary to shift right also the accumulated data of.

The multiplication result data D finally obtained is simply 80-bit data. Therefore, the data C1 and C0 of the lower 40 digits are generally discarded.
Such truncation is truncated due to overflow from the format when performing each arithmetic right shift. The truncation of the lower bits does not affect the precision.

As described above, when multiplying by double-precision data, arithmetic right shift processing is required, and in order for the product-sum circuit 10 in FIG. Processing instructions need to be executed.

FIG. 5 is a schematic block diagram of a product-sum circuit with a shift circuit according to an embodiment of the present invention. A multiplication circuit 22 for multiplying the multiplier B and the multiplicand A as in the prior art, and an addition circuit 23 for adding the data C and the multiplication result. Furthermore, in this example, when a multiplicand that cannot be applied to the fixed-point format is given by a normalized coefficient,
Shift circuit 21 for performing arithmetic left shift for the inverse normalization
Is provided before the multiplication circuit 22. In addition, a shift circuit 24 for performing arithmetic right shift processing for digit alignment of partial products when performing double-precision arithmetic is provided downstream of the adder circuit 23.

With this configuration, the arithmetic left shift processing when performing the multiplication operation with the normalized multiplicand A and the arithmetic right shift processing required for the double precision operation are collectively performed by the code of the multiplication instruction. Can be done.

For example, when a normalized coefficient is read from the above-described coefficient table and given to the product-sum circuit 10 as a multiplicand, the normalized shift amount is added to the instruction code, so that the product-sum circuit It becomes possible to perform arithmetic left shift processing for denormalization together with the product-sum operation in 10. The presence or absence of the shift and the shift amount are determined by the shift circuit 2
It is controlled in accordance with a shift bit SF given as a control signal to 1. Although the arithmetic left shift may be performed after multiplication, the data after multiplication usually has a problem that the number of bits increases and the scale of the shift circuit becomes large. Therefore, in the example of FIG. Is provided.

Therefore, while two machine cycles of the multiplication instruction code and the arithmetic left shift processing instruction code were conventionally required, the product-sum circuit of FIG. Since a left shift process can be performed for the purpose of completion, the arithmetic process can be completed in one machine cycle.

Next, when performing multiplication with double precision, FIG.
In the product-sum circuit, the program is as follows.

[0033]

[Table 1]

On the other hand, a program in the case of using a circuit without the conventional shift circuit 24 is as follows.

[0035]

[Table 2]

The above example is an example in which the double precision multiplication shown in FIG. 4 is performed, and the 40-bit data D in the AX register is
This is an example of an assembler program that multiplies a by 40-bit data Db in a BX register and stores the multiplication result in a DX register. The AX register is, for example, as shown in FIG.
, And the BX register corresponds to, for example, the register reg1. The DX register corresponds to, for example, the register reg3 in FIG.

In the above example of the program I, the left column is an operation code and the right column is an operand. In this program example, first, “MULUA DX, A0, B
0 ”, the data A0 and B0 are multiplied, the multiplied value (partial product) is arithmetically shifted right by 20 bits, and the result is
Store in X register. This arithmetic right shift processing is performed as shown in FIG.
Is performed by the shift circuit 24 in the sum-of-products circuit. Therefore,
A 20-bit right shift command is given by control signal ASF. As described above, by using the product-sum circuit of FIG. 5, multiplication and arithmetic right shift can be performed with one instruction code and one machine cycle.

In the program I, "MSMS D
X, A1, B0 ”, and multiplies the data A1 and B0 by D
Add the data in the X register. Next, "MSMSA
DX, A0, B1 "and multiply the data A0 and B1 by D
The data of the X register is added, and arithmetic right shift processing of 20 bits is performed and stored in the DX register. Since the arithmetic right shift process is also performed by the shift circuit 24 in FIG. 5, the multiplication and the arithmetic right shift can be performed in one instruction code and one machine cycle in the same manner as described above.

Finally, the data A1 and B1 are multiplied by "MSM DX, A1, B1" and the data in the DX register is added, and the final double-precision multiplication result is stored in the DX register.

When a product-sum circuit without a conventional shift circuit is used for the program I, a shift instruction "LSR" for digit alignment is used as in program II.
“DX, 20” and “ASR DX, 20” need to be executed, which requires two machine cycles more time than when using the product-sum circuit with the shift circuit 24 in FIG.

An example of an assembler program relating to the fixed-point data format is not particularly shown, and the merits of the product-sum circuit of FIG. 5 are apparent. As described above, the use of the shift circuit 21 eliminates the need for the instruction cycle of the arithmetic left shift processing, and can shorten the machine cycle as compared with a conventional product-sum circuit without the shift circuit 21.

FIG. 6 is a detailed block circuit diagram of the product-sum circuit of FIG. In this circuit example, 4-bit data A1 to A4 as a multiplicand and 4-bit data B1 to B4 as a multiplier
The multiplication circuit 22 of B4 and the addition circuit 23 of the multiplication result and the data C are shown. The operation result is shown in data X1 to X11 extended to 11 bits.

The shift circuit 21 in FIG. 6 performs arithmetic left shift processing on data that cannot be adapted to the fixed-point data format and has been normalized for denormalization. In this example, an instruction of no shift, 1-bit shift or 2-bit shift is given by the control signals SF1 and SF2, and accordingly, the 4-bit data A1 to A4 are not shifted, or 1-bit or 2-bit data is not processed. Performs arithmetic left shift processing. The shift circuit 21 is therefore composed of 6-bit circuits 211 to 216, and each circuit selects which bit to input according to the control signals SF1 and SF2.

The multiplication circuit 22 is an example constituted by the Booth algorithm. This algorithm is described in, for example, "Digital Signal Processing System" published by The University of Tokyo Press, written by Yoshihiro Mochida, Nobuaki Takahashi, Toshitaka Tsuda, Koichi Honma,
Etc., as is generally known. According to Booth's algorithm, the combination of bits of the multiplier is decoded, the multiplicand is appropriately shifted according to the decoding result, and addition and subtraction are performed, so that the number of times of addition and subtraction of the partial product can be reduced. The circuit can be simplified.

The example of the multiplication circuit 22 includes multipliers B1 to B4
Booth decoders 221 and 222, exclusive OR circuits 223 and 224 of a control signal SG for instructing addition and subtraction and a decode signal, and 3-bit shift bits SFB1 and SFB2, respectively, to appropriately output the shift circuit 21. Booth selectors 225 to 236 for shifting, and adders 237 to 2 for respectively adding outputs of the booth selectors
45. As a result, the result of multiplication of the two data A and B is output as data M1 to M11.

The addition circuit 23 calculates the data M
1 to M11 and adders 250 to 260 for calculating the sum of the data C1 to C11. When a carry bit occurs, each adder gives the carry bit to a higher-order adder.

The shift circuit 24 is composed of eleven selectors, and performs a 4-bit arithmetic right shift process according to the shift control signal ASF. When a right shift is commanded, in this example, the outputs of the adders 254 to 260 are
4 (1) to 24 (7), and 24 (7)
For 24 to (11), 0 is forcibly selected. When the arithmetic right shift processing is not required, the shift processing is not performed.

In the case of multiplication of 4-bit data B and 6-bit data obtained by shifting 4-bit data A, a 10-bit output is sufficient as the operation result. However, in a program routine in which the product-sum operation is repeated many times, even if the product-sum operation result overflows the 10 bits in the middle, the bit can be retained without losing the bit.
In the example of FIG. 6, the adder circuit 23 has an extra bit (X11) for one bit.
And a shift circuit 24. Needless to say, the shift circuit 24 and the adder circuit 23 may be provided with a plurality of extra bits.

In the product-sum circuits shown in FIGS. 5 and 6, shift circuits 21 and 24 are individually controlled by control signals SF and ASF. Of course, the arithmetic left shift process and the arithmetic right shift process may be executed by both shift circuits within one machine cycle.

Although FIGS. 5 and 6 show an example of the product-sum circuit provided with both the shift circuits 21 and 24, the present invention can be applied to a product-sum circuit provided with either one of the shift circuits. Can achieve the purpose.

[0051]

As described above, according to the present invention, in the multiply-accumulate circuit, an arithmetic left shift circuit for inverse normalization for normalized coefficients corresponding to a fixed-point data format, Added an arithmetic right shift circuit required for double precision arithmetic etc. As a result, it is possible to omit a shift instruction that has been conventionally executed in a machine cycle different from the product-sum operation, thereby enabling an operation in a short machine cycle.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a DSP according to an embodiment of the present invention.

2 multiplies a multiplier in a memory RAM1 and a multiplicand in a memory RAM2 by a DSP of FIG.
It is a timing flowchart figure in case of performing addition with the value in eg3.

FIG. 3 is a diagram illustrating an example in which data is formatted in a fixed point.

FIG. 4 is a diagram illustrating a case of multiplying double precision data.

FIG. 5 is a schematic block diagram of a product-sum circuit with a shift circuit according to the embodiment of the present invention.

FIG. 6 is a detailed block circuit diagram of the product-sum circuit of FIG. 5;

[Explanation of symbols]

 Reference Signs List 10 sum-of-products circuit 21 shift circuit (first shift circuit) 22 multiplication circuit 23 addition circuit 24 shift circuit (second shift circuit) reg1,2,3 register

Claims (7)

[Claims] 1. A first, second, and third register for holding data, wherein first input data from the first register is arithmetically operated with 0 or a predetermined bit according to a first shift control signal. A first shift circuit for shifting; a multiplication circuit for performing a multiplication operation of second input data from the second register and an output of the first shift circuit; and a third circuit from the third register. A product-sum circuit, comprising: an addition circuit that performs an addition operation on input data and a multiplication output of the multiplication circuit. And a second register connected to the first register for storing data, wherein the first input data from the first register and the second input data from the second register are connected to each other. A multiplication circuit for performing a multiplication operation; an addition circuit for performing an addition operation of the third input data from the third register and a multiplication output of the multiplication circuit; and an output of the addition circuit according to a second shift control signal. A second shift circuit for performing an arithmetic right shift of 0 or a predetermined bit. 3. The first input data from the first register is connected to first, second, and third registers for holding data, and the first input data from the first register is arithmetically operated by a 0 or a predetermined bit according to a first shift control signal. A first shift circuit for shifting; a multiplication circuit for performing a multiplication operation of second input data from the second register and an output of the first shift circuit; and a third circuit from the third register. An addition circuit for performing an addition operation of the input data and a multiplication output of the multiplication circuit; and a second shift circuit for arithmetically shifting the output of the addition circuit by 0 or a predetermined bit to the right according to a second shift control signal. A sum-of-products circuit. 4. The multiply-accumulate circuit according to claim 2, wherein said second shift circuit is larger than the number of bits obtained by adding the number of bits of said first input data and the number of bits of second input data. It is characterized in that it is configured to correspond to the number of bits. 5. The multiply-accumulate circuit according to claim 3, wherein said second shift circuit is larger than the number of bits obtained by adding the number of bits of said first shift circuit and the number of bits of second input data. It is characterized in that it is configured to correspond to the number of bits. 6. The multiply-accumulate circuit according to claim 1, wherein said adder circuit has a larger number of bits than the number of bits obtained by adding the number of bits of said first shift circuit and the number of bits of second input data. It is characterized by being constituted so that it can respond to. 7. The multiply-accumulate circuit according to claim 2, wherein said adder circuit sets the number of bits larger than the number of bits obtained by adding the number of bits of the first input data and the number of bits of the second input data. It is characterized in that it is configured to be compatible.