JPH1055687A - Non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a disturbance/retention characteristic by dividing writing data comprising one page into a plurality of parts, counting the number of MSB in a divided unit, and inversing data conforming to its counted value. SOLUTION: In a counter 16 in storing write data in a page buffer 15 in writing, the number in which bit data of a prescribed number being high threshold voltage Vth is zero are counted. When the number is 1/2 page or more, '0' is set to a flag bit, when it is lower, '1' is set to the flag bit, the flag bit is stored in a memory cell array 11c by a writing/reading control circuit 12c. At the same time, when a flag bit is '0', inversed data of write data is written in memory cell arrays 11a, 11b by control circuits 12a, 12b, when a flag bit is '1', writing bit is written in a normal state. At the read-out, a flag bit also is read out simultaneously, when a flag bit is '0', a logic level of read- out data is inversed, when a flag bit is '1', data is outputted as it is.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-level nonvolatile semiconductor memory device for storing at least three-level data in a memory cell.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor nonvolatile memory device such as an EPROM or a flash memory, a binary memory cell in which data having two values of "0" and "1" is recorded in one memory transistor. The structure is normal. However, in response to a recent demand for increasing the capacity of a semiconductor nonvolatile memory device, a so-called multi-level semiconductor nonvolatile memory device that records at least three or more values of data in one memory transistor has been proposed. (For example, "A M
multi-Level 32Mb Flash Mem
ory "'95 ISSCC p132-).

FIG. 2 is a diagram showing the relationship between the threshold voltage Vth level and the data content when two-bit quaternary data is recorded in one memory transistor in a NOR type flash memory. .

In FIG. 2, the horizontal axis represents the threshold voltage Vth of the memory transistor, and the vertical axis represents the distribution frequency of the memory transistor. The content of 2-bit data constituting data to be recorded in one memory transistor is represented by [D2, D1], and [D2, D1] =
[1,1], [1,0], [0,1], [0,0]
State exists. That is, there are four states: data “0”, data “1”, data “2”, and data “3”.

In the case of a general NOR type flash memory, an erased state (data "0"), a first program state (data "1"), a second program state (data "2"), a third program state In order to program the memory transistor to the state (data “3”), first, the write data is applied to the bit line voltage (drain voltage) and the word line voltage (gate) for the memory transistors of data “1” to data “3”. Voltage) is set to a constant program voltage. Thereafter, the word line voltage is set to a predetermined determination level to perform reading, and if there is a memory transistor with insufficient writing, rewriting is performed.
This operation is repeated until it is determined that all the memory transistors to be written are sufficiently written. Next, the same operation is performed on the memory transistor of the write data “2” and the write data “3”, and finally the same operation is performed on the memory transistor of the write data “3”, thereby controlling the threshold voltage Vth. I do.

[0006]

In the case of a conventional 1-bit / 1-cell flash memory, as shown in FIG. 3, data on the high threshold voltage Vth side is disturbed.
(Disturb) / Retention (Retention) causes the threshold voltage Vth to transition to the slightly lower threshold voltage Vth side as shown by the broken line in the figure, but if it is higher than the word line voltage, there is no problem. There was no problem.

However, in the case of a multi-valued memory, as shown in FIG. 4, the boundary of data determination is narrow, and the state of the threshold voltage Vth is far from the threshold voltage Vth in the ultraviolet erasing state (UV). That is, there is a problem that the higher the threshold voltage Vth is, the more easily disturb / retention is received, and if there is a large amount of write data in the high threshold voltage Vth state, it is difficult to hold the data.

This problem will be further described with reference to FIG. In FIG. 4, the solid line shows the distribution of the threshold voltage Vth immediately after writing, the dotted line shows the distribution of the threshold voltage Vth in the case of receiving the read disturb / retention, and the dashed line shows the determination level.

In the case where multi-valued data is not used, data is correctly read even if the threshold voltage Vth slightly changes.
As can be seen from FIG. 4, in the case of multi-valued data, reading becomes more difficult as the threshold voltage Vth is higher.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a nonvolatile semiconductor memory device capable of improving disturb / retention characteristics.

[0011]

In order to achieve the above object, according to the present invention, the amount of charge stored in a charge storage portion changes according to an applied voltage, and the threshold voltage changes according to the change. A nonvolatile semiconductor memory device having a plurality of memory cells and writing multi-valued data of three or more values into a memory cell in page units, wherein at the time of writing, write data constituting one page is divided into a plurality of pieces, and the entire page is written. A determination circuit for determining whether bit data indicating a distribution of a higher threshold voltage in the division unit is larger or smaller than a value set based on the number of divisions, and generating flag data indicating the result; If the flag memory cell for storing the flag data and the flag data indicate that there is more distribution with the higher threshold voltage, the logic level of the write data is inverted. In the case where it is indicated that the distribution of the higher threshold voltage is small, the write data is written at the input logic level while the flag data is written in the flag memory cell. And a writing circuit for storing

In addition, at the time of reading, a read circuit for reading flag data from the flag memory cell together with the data, and when the flag bits indicate that the distribution with the higher threshold voltage is higher, the logic of the read data is high. An output circuit for inverting the level and outputting the data so as to indicate that the distribution of the higher threshold voltage is less, and to output the logical level of the read data as it is at the logical level.

According to the nonvolatile semiconductor memory device of the present invention, at the time of fetching page write data, write data constituting one page is divided into a plurality of pieces, and the number of MSBs (side bits) in the division unit is counted. In accordance with the count value, if the distribution of data far from the ultraviolet erasing state (UV) is large, the data is inverted,
Increase the distribution of data close to UV. Thereby, the disturb / retention characteristics are improved.

[0014]

FIG. 1 is a block diagram showing one embodiment of a nonvolatile semiconductor memory device according to the present invention. The nonvolatile semiconductor memory device 10 includes ordinary memory cell arrays 11a and 11b, a flag memory cell array 11c, ordinary memory cell array write / read control circuits 12a and 12b, and a flag memory cell array write / read.
Read control circuit 12c, input buffers 13-0 to 13-
3, an output buffer 14-0 to 14-3, a page buffer 15, a counter 16, and a level selection circuit 17.

In the memory cell arrays 11a and 11b, for example, a floating gate type nonvolatile memory cell transistor is a NAND type or a DINOR (DIvided N).
(OR) type. The multi-level data input from the input terminals IO0 and IO1 are recorded in the memory cell array 11a, and the multi-level data input from the input terminals IO2 and IO3 are recorded in the memory cell array 11b.

The flag memory cell array 11c is a flag bit data indicating whether or not the recording data to the memory cell arrays 11a and 11b was recorded at the logical level (normal rotation state) at the time of input or was recorded in the inverted state. Is recorded. As the flag bit data, data of logic “1” is recorded when data is written in the normal state, and data of logic “0” is recorded when data is written in the inverted state.

Write / read control circuit 12a has a data latch circuit arranged at the time of writing, for example, for each bit line or for each bit line pair, and is temporarily stored in page buffer 15 and output from level selection circuit 17. Terminal IO0
N, the write data in the normal rotation state or the inverted data output from IO1N are stored in the data latch circuit,
The data is written to the addressed memory cell of the memory cell array 11a. At the time of reading, for example, the word line voltage set according to the threshold voltage is sequentially changed, and the write data to the selected memory cell is output to the bit line and sequentially output via the data buses IO01 and IO02. Output to the buffers 14-0 and 14-1.

At the time of writing, the write / read control circuit 12b has a data latch circuit arranged, for example, for each bit line or each bit line pair, and is temporarily stored in the page buffer 15 and output from the level selection circuit 17. Terminal IO
The non-inverted write data or inverted data output from 2N and IO3N is stored in the data latch circuit, and written to the addressed memory cell of the memory cell array 11b. At the time of reading, for example, the word line voltage set in accordance with the threshold voltage is sequentially changed, and the write data to the selected memory cell is output to the bit line and sequentially output via the data buses IO03 and IO04. Output to the buffers 14-2 and 14-3.

At the time of writing, the write / read control circuit 12c receives the flag bit data output from the counter 16 and writes the data into predetermined memory cells of the memory cell array 11c. At the time of reading, the memory cell array 11a,
The flag bit data corresponding to the read data from 11b is read and output to output buffers 14-0 and 14-1 and 14-2 and 14-3.

The input buffer 13-0 has an input / output terminal IO.
The write bit data input from 0 is input to the page buffer 15. The input buffer 13-1 inputs the write bit data input from the input / output terminal IO1 to the page buffer 15 and the counter 16. The input buffer 13-2 causes the page buffer 15 to input the write bit data input from the input / output terminal IO2. The input buffer 13-3 inputs the write bit data input from the input / output terminal IO3 to the page buffer 15 and the counter 16.

Output buffers 14-0 and 14-1 output data bus I / O from write / read control circuit 12a at the time of reading.
O01 and IO02 hold the data read out, respectively,
According to the contents of the flag bit data output from write / read control circuit 12c, the logic levels of the held data are kept in the normal state or inverted and output terminals IO0, IO1
Respectively. Specifically, when the flag bit data is logic "1", the signal is output in the normal rotation state, and when the flag bit data is logic "0", the signal is inverted and output.

Output buffers 14-2 and 14-3 output data bus I / O from write / read control circuit 12b at the time of reading.
Hold the data read to O03 and IO04 respectively,
According to the contents of the flag bit data output from write / read control circuit 12c, the logic levels of the held data are kept in the normal state or inverted and output terminals IO2, IO3
Respectively. Specifically, when the flag bit data is logic “1”, the output is performed in the normal rotation state, and when the flag bit data is logic “0”, the logic level is inverted and output.

The page buffer 15 stores n-bit (4 bits in this embodiment) write data via the input buffer.

The counter 16 has a high threshold voltage when storing write data in the page buffer 15 at the time of writing. In this example, the number of write bit data input to the input / output terminals IO1 and IO3 is "0". Is counted, and when the number is equal to or more than a half page (the number is “2” in the present embodiment), for example, logic “0”, the number is smaller than a half page (the number “ 1 "
Or "0"), the flag bit data S16 of logic "1" is output to the write / read control circuit 12c via the level selection circuit 17 and the bus IO05.

When the flag bit data S16 is "1", the level selection circuit 17 keeps the logic level of the write data stored in the page buffer 15 in the normal state and the flag bit data S16 becomes "0". In the case of, the logical level of the write data stored in the page buffer 15 is inverted and the output terminals IO0N, IO1N, I
Data buses IO01, IO02, IO from O2N, IO3N
03, output to IO04.

In the nonvolatile semiconductor memory device of this embodiment, during writing, attention is paid to the fact that the low threshold voltage side shown in FIG. Data, in this example IO1 and I
If the number of O3 is "0" is counted, and if the number is more than 1/2 page, for example, "0" is set to the flag bit and the flag bit is written to the write data latch of the write / read control circuit 12c. Store in circuit. Then, writing is performed by storing the inverted data of the write data in the data latch circuits of the write / read control circuits 12a and 12b. As a result, the data on the low threshold voltage Vth side increases, and the disturb / retention characteristics are improved.

The specific operation of the above configuration will be described below. First, the write operation will be described.
Input from input terminals IO0 to IO3, input buffer 1
The write data via 3-0 to 13-3 is temporarily stored in the page buffer. The input buffer 13-
The write bit data input to 1, 13-3 is input to the counter 16.

In the counter 16, input / output terminals IO1 and IO1
The number of write bit data input to O3 is "0" is counted, and when the number is "2" which is equal to or more than a half page, for example, logic "0", the number is half In the case of "1" or "0", which is less than one page, flag bit data S16 of logic "1" is generated and output to the write / read control circuit 12c via the level selection circuit 17 and the bus IO05. .

In the level selection circuit 17, when the flag bit data S16 is "1", the write data stored in the page buffer 15 is output to the output terminals IO0N, IO1N, IO2N while keeping its logical level in the normal state. ,
Data buses IO01, IO02, IO03, IO from IO3N
Output to 04. On the other hand, when the flag bit data S16 is "0", the logical level of the write data stored in the page buffer 15 is inverted, and the inverted data is output to the output terminals IO0N, IO1N, IO2N, IO3N.
Are output to the data buses IO01, IO02, IO03, IO04. Then, the write bit data is input to corresponding write / read control circuits 12a and 12b.

In the write / read control circuit 12a, the write data or inverted data output from the output terminals IO0N and IO1N of the level selection circuit 17 in the non-inverted state is stored in the data latch circuit, and the memory cell array 11a
Is written to the addressed memory cell. Similarly, in the write / read control circuit 12b, the level selection circuit 1
The write data or inverted data in the normal rotation state output from the output terminals IO2N and IO3N of No. 7 are stored in the data latch circuit, and written into the addressed memory cells of the memory cell array 11b.

At this time, the write / read control circuit 12
In c, the flag bit data from the counter 16 is stored in the latch circuit, and the recording data to the memory cell arrays 11a and 11b is recorded in the corresponding recell array 11c at the input level (normal rotation state) or inverted. Flag bit data indicating whether or not recording was performed in the state is recorded.

Next, the read operation will be described. In the write / read control circuits 12a and 12b, for example, the word line voltage set according to the threshold voltage is sequentially changed, and the write data to the selected memory cell is output to the bit line, and the output buffer 14 is sequentially output. −0,14−
1, and 14-2 and 14-3. At this time, in the write / read control circuit 12c, the flag bit data corresponding to the read data from the memory cell arrays 11a and 11b is read and the output buffer 14-
0, 14-1, and 14-2, 14-3.

Output buffers 14-0, 14-1 and 1
In 4-2 and 14-3, when the flag bit data is "0", the data stored in the memory cell is determined to be inverted data, and the logical level of the read data is inverted and output. On the other hand, the flag bit data is “1”
In this case, the read data is output at the read logic level.

As described above, according to the present embodiment, at the time of writing, the page buffer 1 of the write data is used.
5, the counter 16 counts the number of the predetermined plurality of bit data having the high threshold voltage Vth of "0", and if the number is equal to or more than 1/2 page, the counter 16 sets the flag bit. The flag bit is set to "0" and set to "0" when the value is lower than a half page, and the flag bit is set by the write / read control circuit 12c to the memory cell array 11c.
And when the flag bit is “0”, the inverted data of the write data is written to the write / read control circuit 12.
a, 12b, the data is written to the memory cell arrays 11a, 11b. If the flag bit is "1", the write data is written as it is in the normal rotation state. At the time of reading, the flag bit is read at the same time, and the flag bit is "0".
In this case, the logical level of the read data is inverted and output, and when the flag bit is "1", the read data is output as it is, so that the low threshold voltage Vth
The data on the side increases, and the disturb / retention characteristics can be improved.

[0035]

As described above, according to the present invention,
A non-volatile semiconductor memory device capable of improving disturb / retention characteristics can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a semiconductor nonvolatile memory device according to the present invention.

FIG. 2 is a diagram showing a relationship between a threshold voltage Vth level and data content when data of two bits and having four values is recorded in one memory transistor in a NAND flash memory.

FIG. 3 is a diagram for explaining the influence of disturbance and retention of a binary memory.

FIG. 4 is a diagram for explaining the influence of disturbance and retention of a four-valued memory.

[Explanation of symbols]

Reference numeral 10: nonvolatile semiconductor memory device; 11a, 11b: memory cell array; 11c: flag memory cell array;
2a, 12b: normal memory cell array write / read control circuit, 12c: flag memory cell array write / read
Read control circuit, 13-0 to 13-3 ... input buffer, 1
4-0 to 14-3: output buffer page, 15: buffer, 16: counter, 17: level selection circuit.

Claims (6)

[Claims] A plurality of memory cells, each of which has a plurality of memory cells whose charge amount changes in accordance with an applied voltage and whose threshold voltage changes in accordance with the change, and which stores multi-valued data of three or more values. What is claimed is: 1. A non-volatile semiconductor memory device in which a page is written into a memory cell, wherein at the time of writing, write data constituting one page is divided into a plurality, and a distribution of a higher threshold voltage in the division unit in the entire page A determination circuit that determines whether the bit data indicating is larger or smaller than a set value based on the number of divisions and generates flag data indicating the result, a flag memory cell for storing the flag data, and the flag If the data indicates that the distribution with the higher threshold voltage is higher, the logic level of the write data is inverted and the data is written to the memory cell, and the threshold voltage is increased. A non-volatile semiconductor memory having a write circuit for writing the write data at the input logic level while storing the flag data in the flag memory cell. apparatus. 2. A read circuit for reading flag data from the flag memory cell together with data at the time of reading, and a logic of read data when a flag bit indicates that there is more distribution with a higher threshold voltage. 2. The output circuit according to claim 1, further comprising an output circuit for outputting the logic level of the read data as the read logic level when the level is inverted and the distribution of the higher threshold voltage is small. Non-volatile semiconductor storage device. 3. The nonvolatile semiconductor memory device according to claim 1, wherein the set value of said discriminating circuit is a half of the total number of bit data indicating a higher distribution of the threshold voltage in one entire page. 4. A plurality of memory cells in which the amount of charge stored in a charge storage unit changes according to an applied voltage and a threshold voltage changes according to the change, and multi-value data having three or more values are stored. A non-volatile semiconductor memory device that writes data to memory cells in page units, comprising: a page buffer for storing input write data at the time of writing;
A counter that counts the number of bit data indicating the distribution of the higher threshold voltage in the division unit in the entire page and generates flag data indicating whether or not the counted value is equal to or greater than a preset value; If the flag memory cell for storing the flag data and the flag data indicate that the distribution with the higher threshold voltage is higher, the logical level of the write data stored in the page buffer is inverted. A write circuit for writing data to the memory cell and writing the write data stored in the page buffer at the input logic level when the higher threshold voltage distribution is less. Non-volatile semiconductor storage device. 5. A read circuit for reading flag data from said flag memory cell together with data at the time of reading, and a logic of read data when a flag bit indicates that there is more distribution with a higher threshold voltage. 5. The output circuit according to claim 4, further comprising an output circuit for inverting the level and outputting the logic level of the read data as the read logic level when the higher threshold voltage distribution is less. Non-volatile semiconductor storage device. 6. The nonvolatile semiconductor memory device according to claim 4, wherein the set value of said counter is a half of the total number of bit data indicating the higher distribution of the threshold voltage in the entire page.