JPH1051017A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the semiconductor device in which a substrate potential is made stable and a semiconductor substrate material is utilized effectively so as to reduce the material cost. SOLUTION: A CMOS inverter 3 is formed on a front side 2a of a P-type single crystal silicon substrate 2 and a single crystal silicon solar battery 4 is formed on a rear side 2b of the same substrate 2. Then the solar battery 4 supplies power to the CMOS inverter 3 via electrodes 68, 69. Thus, the semiconductor substrate material is utilized effectively, the material cost is reduced and the entire semiconductor device 1 is made small. The electrodes 68, 69 are extended up to the front side 2a from the rear side 2b of the substrate 2 through a side face 2c and formed simultaneously with electrodes 41D, 51D, 44, 54, 41S, 51S. Thus, the solar battery 4 and the CMOS inverter 3 are connected simply and easily during the semiconductor manufacture process without provision of the wiring process.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device.

[0002]

2. Description of the Related Art In recent years, with the spread of portable communication devices and information devices, it has been proposed to use a solar cell as a power source for portable devices in order to reduce the size and weight of these portable devices. . In this case, after separately manufacturing a semiconductor substrate on which an integrated circuit forming an internal circuit of the device is formed and a semiconductor substrate on which a solar cell for a power supply of the integrated circuit is formed, both substrates are supplied with power. A method of connecting with a power line is used.

Japanese Patent Application Laid-Open No. 56-68888 (G09F 9/35, G02F 1/133, G09F 9/00) discloses that a metal reflection for a liquid crystal cell is formed on one principal surface of a large-area semiconductor substrate for solid-state display. A display device is disclosed in which unit picture elements composed of electrode liquid crystal driving elements are arranged in a two-dimensional matrix, and a solar cell composed of a diffusion layer and a transparent electrode is formed on another main surface of the substrate. In this display device, a PMOS transistor as a liquid crystal driving element is provided on one main surface of an n-type silicon substrate,
One metal electrode of the solar cell is formed. Also,
A P-type diffusion layer for a solar cell is formed on another main surface of the n-type silicon substrate, and the other electrode of the solar cell is formed on the P-type diffusion layer for a solar cell. The other electrode of the solar cell is a transparent electrode made of an ITO (Indium Tin Oxide) film. The P-type diffusion layer for a solar cell is a PMO
It is formed at the same time as the P-type diffusion layer serving as the source / drain region of the S transistor, and is formed by gas diffusion using BBr ₃ or solid phase diffusion using BN.

As described above, in the display device described in the publication, a liquid crystal driving element and a solar cell as a power supply of the liquid crystal driving element are formed on the front and back of one semiconductor substrate, respectively. Therefore, the semiconductor substrate material can be effectively used, and the material cost can be reduced. In addition, the size of the entire device can be reduced.

However, since the P-type diffusion layer for a solar cell is formed directly on the back surface of the n-type silicon substrate, the substrate potential is apt to be unstable, which causes a problem that the liquid crystal driving element malfunctions.

[0006]

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to stabilize the substrate potential and make effective use of the semiconductor substrate material. It is to provide a semiconductor device which can reduce costs.

[0007]

SUMMARY OF THE INVENTION The gist of the present invention is that the invention includes a device formed on a semiconductor substrate and a solar cell formed on the same semiconductor substrate.

According to a second aspect of the present invention, there is provided a semiconductor substrate (2) and a device (3) formed on the semiconductor substrate.
And a solar cell (4, 30) formed on the same semiconductor substrate.
2,402), and a conductive film (61) or an insulating film (102) formed between the solar cell and the semiconductor substrate, wherein power is supplied from the solar cell to the device. And

According to a third aspect of the present invention, a semiconductor substrate (2), a device (3) formed on one main surface (2a) of the semiconductor substrate, and the other main surface (2) of the same semiconductor substrate.
b) Solar cell (4, 302, 402) formed thereon
And a conductive film (61) or an insulating film (102) formed between the solar cell and the semiconductor substrate. The gist is that power is supplied from the solar cell to the device.

According to a fourth aspect of the present invention, there is provided a semiconductor substrate (2), a device (3) formed on the semiconductor substrate, and a solar cell formed on the device via an insulating film (202). (4), wherein power is supplied from the solar cell to the device.

According to a fifth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, the conductive film (61) is a back electrode of the solar cell. .

According to a sixth aspect of the present invention, in the semiconductor device according to the third aspect, the conductive layer (6) extending from one main surface of the semiconductor substrate to the other main surface through the side surface (2c).
8, 69), and the gist thereof is to use the conductive layer as a power line for supplying power from the solar cell to the device.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic sectional view of a semiconductor device 1 according to the first embodiment. The semiconductor device 1 includes a CMOS inverter 3 formed on one main surface (hereinafter, referred to as a surface) 2a of a P-type single-crystal silicon substrate 2 and another main surface (hereinafter, referred to as a main surface) 2
And a single-crystal silicon solar cell 4 formed on a rear surface 2b.

A field oxide film 5 is formed on the surface 2a of the substrate 2 by using the LOCOS method. On the surface 2a of the substrate 2 exposed from the field oxide film 5, a CMOS
An NMOS transistor 6 and a PMOS transistor 7 constituting the inverter 3 are formed.

The NMOS transistor 6 is connected to the source region 1
1S, a drain region 11D, a channel region 12, a gate oxide film 13, and a gate electrode 14. Source region 11S and drain region 11D are formed of an N-type diffusion layer formed on surface 2a of substrate 2. The channel region 12 is formed on the substrate 2 between the regions 11S and 11D. Gate electrode 14 is formed on channel region 12 via gate oxide film 13.

The PMOS transistor 7 is connected to the source region 2
1S, a drain region 21D, a channel region 22, a gate oxide film 23, and a gate electrode 24, and are formed on an N well 31 formed on the surface 2a of the substrate 2. The source region 21S and the drain region 21D
The P-type diffusion layer is formed on the well 31. The channel region 22 includes an N well 31 between the regions 21S and 21D.
Is formed on. Gate electrode 24 is formed on channel region 22 via gate oxide film 23.

An interlayer insulating film 32 is formed on the entire surface 2a of the substrate 2 including the transistors 6 and 7. The respective gate electrodes 14 and 24 are respectively connected to the respective gate electrodes 44 and 54 via contact holes formed in the interlayer insulating film 32.
It is connected to the. The source regions 11S and 21S are connected to the source electrodes 41S and 51S via contact holes formed in the interlayer insulating film 32, respectively. Each drain region 11D, 21D is connected to each drain electrode 41D, 51D via a contact hole formed in the interlayer insulating film 32, respectively.

Each of the gate electrodes 44 and 54 extends on the interlayer insulating film 32 and is connected to each other. The drain electrodes 41D and 51D also extend on the interlayer insulating film 32 and are connected to each other.

On the back surface 2b of the substrate 2, a back electrode 61, a P-type diffusion layer 62,
The diffused layer 63, the transparent electrode 64, and the antireflection film 65 are formed in this order.

The back electrode 61 is made of various metals (aluminum, gold,
Silver, cobalt, titanium, and other high melting point metal) films. The metal used for the back electrode 61 is required to have high reflectance and to be hardly diffused into the substrate 2 and the P-type diffusion layer 62.

P-type diffusion layer 62 and N-type diffusion layer 63 are made of single crystal silicon. The transparent electrode 64 (thickness: 1 μm or less) is made of an ITO film. The antireflection film 65 is made of a silicon nitride film.

Each of the layers 62 and 63 and the transparent electrode 64 include
A contact hole 67 reaching the back electrode 61 is formed. An antireflection film 65 extends on the inner wall of the contact hole 67. The back electrode 61 is connected to the plus electrode 68 via a contact hole 67. Therefore, the layers 62 and 63 and the transparent electrode 64 are insulated from the positive electrode 68 by the antireflection film 65 on the inner wall of the contact hole 67.

The transparent electrode 64 is connected to the negative electrode 6 through a contact hole 70 formed in the anti-reflection film 65.
9 is connected. An insulating film 71 on the side surface 2c of the substrate 2;
Are formed. The electrodes 68 and 69 are formed on the insulating film 71 and extend from the back surface 2b of the substrate 2 to the front surface 2a through the side surface 2c. The plus electrode 68 is connected to the source electrode 51S, and the minus electrode 69 is connected to the source electrode 41S. That is, each electrode 6
Reference numerals 8 and 69 function as power lines for supplying power from the single-crystal silicon solar cell 4 to the CMOS inverter 3.

Next, a method for manufacturing the semiconductor device 1 will be described. Step 1: The surface 2a of the substrate 2 is covered with a photoresist. Step 2: A single-crystal silicon solar cell 4 is formed on the back surface 2b of the substrate 2 by using the following method.

[First Manufacturing Method] Step 2-1: Metal ions for forming the back electrode 61 are implanted into the entire back surface 2b of the substrate 2. At this time, ion implantation conditions are appropriately selected, and a predetermined concentration of metal ions are implanted at a predetermined depth from the surface of the substrate 2 to form a back electrode 61 having a desired thickness in the substrate 2.

Step 2-2: P on the entire back surface 2b of the substrate 2
P-type impurity ions for forming the P-type diffusion layer 62 are implanted. At this time, ion implantation conditions are appropriately selected, and a predetermined concentration of P-type impurity ions are implanted at a predetermined depth from the surface of the substrate 2 so that the P-type diffusion layer 62 having a desired thickness is formed in the substrate 2. To form

Step 2-3: N is applied to the entire back surface 2b of the substrate 2.
N-type impurity ions for forming the N-type diffusion layer 63 are implanted. At this time, ion implantation conditions are appropriately selected and N-type impurity ions of a predetermined concentration are implanted at a predetermined depth from the surface of the substrate 2 so that the N-type diffusion layer 63 having a desired film thickness is formed in the substrate 2. To form

Step 2-4: By performing a heat treatment, the impurity ions implanted into the respective layers 62 and 63 are activated, and the respective layers 62 and 63 are recrystallized. The method of recrystallization of each of the layers 62 and 63 by the heat treatment includes laser beam,
There are a melt recrystallization method using an electron beam and a heater, a solid phase growth method, and the like.

[Second Manufacturing Method] Step 2-1: A back electrode 61 made of a metal film is formed on the entire back surface 2b of the substrate 2 by using a PVD (Physical Vapor Deposition) method.

Step 2-2: CVD (Chemical V) in which a P-type impurity (diborane (B ₂ H ₆ ) or the like) is added to the raw material gas
A doped polysilicon film to be a P-type diffusion layer 62 is formed on the back electrode 61 by using an apor deposition method.

Step 2-3: Using a CVD method in which an N-type impurity (phosphine (PH ₃ ) or the like) is added to the raw material gas,
On the P-type diffusion layer 62, a doped polysilicon film to be the N-type diffusion layer 63 is formed.

Step 2-4: By performing a heat treatment, the impurity ions in each doped polysilicon film are activated, and each doped polysilicon film is recrystallized to form each layer 62 of single-crystal silicon. 63 is formed.

Step 3: A transparent electrode 64 made of an ITO film is formed on the N-type diffusion layer 63. Step 4: A contact hole 67 is formed in each of the layers 62 and 63 and the transparent electrode 64 by using anisotropic etching.

Step 5: An antireflection film 65 made of a silicon nitride film is formed on the entire back surface 2b of the substrate 2 including the inner wall of the contact hole 67 by the CVD method. Step 6: A contact hole 70 is formed in the antireflection film 65 by using anisotropic etching, and the back electrode 61 is exposed from the bottom surface of the contact hole 67.

Step 7: The photoresist covering the front surface 2a of the substrate 2 is removed, and the back surface 2b of the substrate 2 is covered with the photoresist. Step 8: On the surface 2a of the substrate 2, a field oxide film 5, N
A well 31, an NMOS transistor 6, a PMOS transistor 7, and an interlayer insulating film 32 are sequentially formed. Examples of the material of the interlayer insulating film 32 include a silicon oxide film, a silicon nitride film, and silicate glass (PSG, BPSG, etc.).

Step 9: The photoresist covering the back surface 2b of the substrate 2 is removed, and the insulating film 7 is formed on the side surface 2c of the substrate 2.
Form one. Examples of the material of the insulating film 71 include a silicon oxide film, a silicon nitride film, a coating insulating film such as a SOG (Spin On Glass) film and a polyimide resin film.

Step 10: A contact hole is formed in the interlayer insulating film 32. Step 11: Using the PVD method, the entire surface (front surface 2a, back surface 2b, side surface 2c) of the substrate 2 including the inside of each contact hole
Then, a metal film is formed. Next, after applying a photoresist on the metal film, a resist pattern is formed through an exposure step and a development step. In the exposure step, the entire surface of the substrate 2 is exposed by rotating the substrate 2 while scanning the beam in the form of a beam having a minute diameter with ultraviolet rays. Subsequently, the electrodes 41D, 51D, and 4D are etched by etching the metal film using the resist pattern as an etching mask.
4, 54, 41S, 51S, 68, and 69 are simultaneously formed. As a result, the semiconductor device 1 is completed.

As described above, according to the present embodiment, the following operations and effects can be obtained. (1) CMOS is formed on the surface 2a of the P-type single crystal silicon substrate 2.
An inverter 3 is formed, and a single-crystal silicon solar cell 4 is formed on the back surface 2 b of the same substrate 2. Then, from the single crystal silicon solar cell 4 via the respective electrodes 68 and 69,
Power is supplied to the CMOS inverter 3. Therefore, the semiconductor substrate material can be effectively used, and the material cost can be reduced. In addition, the entire semiconductor device 1 can be reduced in size.

(2) The P-type diffusion layer 62 constituting the single-crystal silicon solar cell 4 is connected to the substrate 2 via the back electrode 61. Therefore, the potential of the substrate 2 can be stabilized, and malfunction of the CMOS inverter 3 can be prevented.

(3) Since the conductivity of each of the diffusion layers 62 and 63 constituting the single-crystal silicon solar cell 4 can be freely set, the performance of the single-crystal silicon solar cell 4 can be improved. In order to adjust the conductivity of each of the diffusion layers 62 and 63, in the first manufacturing method, the steps 2-2 and 2-2 are performed.
The conditions for implanting impurity ions in 2-3 may be arbitrarily set. Further, in the second manufacturing method, the step 2-
The amount of the impurity added by the CVD method in 2, 2-3 may be arbitrarily set.

(4) Each of the electrodes 68 and 69 extends from the back surface 2b of the substrate 2 to the front surface 2a through the side surface 2c. Each of the electrodes 68 and 69 is connected to each of the electrodes 41D and 51.
D, 44, 54, 41S, and 51S are formed at the same time.
Therefore, the connection between the single crystal silicon solar cell 4 and the CMOS inverter 3 can be easily and easily made in the semiconductor manufacturing process without providing a wiring step.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. In this embodiment, the same components as those in the first embodiment have the same reference numerals, and a detailed description thereof will be omitted.

FIG. 2 shows a semiconductor device 101 according to the second embodiment.
FIG. In the semiconductor device 101, the first
The only difference from the semiconductor device 1 of the embodiment is that an insulating film 102 is formed between the substrate 2 and the back electrode 61. There are the following methods for forming the insulating film 102.

[First Forming Method] Before the step 2-1 in the first manufacturing method of the first embodiment, a SIMOX (Sepa
A step of implanting oxygen ions into the entire rear surface 2b of the substrate 2 by using a ratio by implanted oxygen method is added.
At this time, ion implantation conditions are appropriately selected, and oxygen ions of a predetermined concentration are implanted at a predetermined depth from the surface of the substrate 2, thereby forming an insulating film made of a silicon oxide film having a desired thickness in the substrate 2. 102 is formed.

[Second Forming Method] Before the step 2-1 in the first manufacturing method of the first embodiment, the back surface 2b of the substrate 2
A step of implanting nitrogen ions over the entire surface is added. At this time, ion implantation conditions are appropriately selected, and nitrogen ions of a predetermined concentration are implanted at a predetermined depth from the surface of the substrate 2 to thereby form an insulating film made of a silicon nitride film having a desired thickness in the substrate 2. 102 is formed.

[Third Forming Method] Before the step 2-1 in the second manufacturing method of the first embodiment, the back surface 2b of the substrate 2
A step of forming an insulating film 102 made of a silicon oxide film or a silicon nitride film by using a CVD method over the entire surface is added.

[Fourth Forming Method] Before the step 2-1 in the second manufacturing method of the first embodiment, the back surface 2b of the substrate 2
A step of forming an insulating film 102 made of a silicon oxide film over the entire surface by using a thermal oxidation method is added.

In the method of manufacturing the semiconductor device 101, steps other than the step of forming the insulating film 102 are the same as those of the first embodiment. Thus, in the present embodiment, C
The MOS inverter 3 and the single crystal silicon solar cell 4
It is electrically separated completely by the insulating film 102. Therefore, the operation of the single-crystal silicon solar cell 4 does not affect the potential of the substrate 2. Therefore, according to the present embodiment, the potential of the substrate 2 can be further stabilized than in the first embodiment, and malfunction of the CMOS inverter 3 can be reliably prevented.

The other functions and effects of this embodiment are the same as those of the first embodiment. (Third Embodiment) Hereinafter, a third embodiment of the present invention will be described with reference to the drawings. In this embodiment,
The same components as those in the first embodiment have the same reference numerals, and a detailed description thereof will be omitted.

FIG. 3 shows a semiconductor device 201 according to the third embodiment.
FIG. In the semiconductor device 201, the first
The difference from the semiconductor device 1 of the embodiment is as follows.

(1) Each electrode 41D, 51D, 44, 5
On the 4, 41S, 51S and the interlayer insulating film 32, an interlayer insulating film 202 is formed. Examples of the material of the interlayer insulating film 202 include a silicon oxide film, a silicon nitride film, and silicate glass (PSG, BPSG, etc.).

(2) The back electrode 6 is formed on the interlayer insulating film 202.
1, P-type diffusion layer 62, N-type diffusion layer 63, transparent electrode 64,
The anti-reflection film 65 is formed in this order. (3) The back electrode 61 is connected to the source electrode 51S via a contact hole 203 formed in the interlayer insulating film 202. Therefore, the back electrode 61 formed in the contact hole 203 functions as a positive electrode.

(4) Each layer 61 to 63 and interlayer insulating film 2
02 has a contact hole 204 formed therein.
An insulating film 205 is formed on the inner wall of the contact hole 204. The transparent electrode 64 is connected to the source electrode 41S via the contact hole 204. Therefore, each of the layers 61 to 63 and the transparent electrode 64 are
05. Further, the transparent electrode 64 formed in the contact hole 204 functions as a negative electrode.

Next, a method for manufacturing the semiconductor device 201 will be described. Step 1: On the surface 2a of the substrate 2, a field oxide film 5, N
Well 31, NMOS transistor 6, PMOS transistor 7, interlayer insulating film 32, electrodes 41D, 51D, 4
4, 54, 41S and 51S are sequentially formed.

Step 2: Each electrode 41D,
An interlayer insulating film 202 is formed on 51D, 44, 54, 41S, 51S and the interlayer insulating film 32. Step 3: A contact hole 203 is formed in the interlayer insulating film 202 by using anisotropic etching.

Step 4: The back electrode 61 made of a metal film is formed on the interlayer insulating film 202 including the inside of the contact hole 203 by using the PVD method. Next, the layers 62 and 63 are formed by the same steps as in the second manufacturing method of the first embodiment.

Step 5: Each layer 6 is formed using anisotropic etching.
1 to 63 and the contact hole 2 in the interlayer insulating film 202.
04 is formed. Step 6: An insulating film 205 is formed on the inner wall of the contact hole 204 by using the CVD method. Next, the source electrode 41 is removed from the bottom of the contact hole 204 by etching.
S is exposed.

Step 7: A transparent electrode 64 made of an ITO film is formed on the N-type diffusion layer 63 including the inside of the contact hole 204. An antireflection film 65 made of a silicon nitride film is formed on the transparent electrode 64 by using the CVD method. As a result, the semiconductor device 201 is completed.

As described above, according to the present embodiment, the following operations and effects can be obtained. (1) CMOS is formed on the surface 2a of the P-type single crystal silicon substrate 2.
An inverter 3 is formed, and a single-crystal silicon solar cell 4 is formed on the CMOS inverter 3 via an interlayer insulating film 202. Then, from the single-crystal silicon solar cell 4, via a back electrode 61 functioning as a positive electrode and a transparent electrode 64 functioning as a negative electrode, C
Power is supplied to the MOS inverter 3. Therefore,
The semiconductor substrate material can be used effectively, and the material cost can be reduced. In addition, the entire semiconductor device 1 can be reduced in size.

(2) The CMOS inverter 3 and the single crystal silicon solar cell 4 are electrically completely separated by the interlayer insulating film 202. Therefore, the operation of the single-crystal silicon solar cell 4 does not affect the potential of the substrate 2. Therefore, the potential of the substrate 2 can be further stabilized than in the first embodiment, and the malfunction of the CMOS inverter 3 can be reliably prevented.

(3) Since the conductivity of each of the diffusion layers 62 and 63 constituting the single-crystal silicon solar cell 4 can be freely set, the performance of the single-crystal silicon solar cell 4 can be improved.

(4) Single crystal silicon solar cell 4 and CMO
The connection with the S inverter 3 is made through each contact hole 20.
3, 204, the back electrode 61 and the transparent electrode 64. Therefore, the single crystal silicon solar cell 4 and the CMOS inverter 3 can be provided without providing a wiring process.
Can be easily and easily made in the semiconductor manufacturing process.

(5) The back electrode 61 is made of a metal film having a high reflectance. Therefore, the CMOS inverter 3 can be shielded from light by the back electrode 61, and the CM
Malfunction of the OS inverter 3 can be prevented.

(Fourth Embodiment) Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings. In this embodiment, the same components as those in the first embodiment have the same reference numerals, and a detailed description thereof will be omitted.

FIG. 4 shows a semiconductor device 301 according to the fourth embodiment.
FIG. In the semiconductor device 301, the first
The difference from the semiconductor device 1 of the embodiment is as follows.

(1) The semiconductor device 301 includes a CMOS inverter 3 formed on the front surface 2a of the substrate 2 and a stacked amorphous silicon solar cell 302 formed on the back surface 2b of the substrate 2.

(2) On the back surface 2b of the substrate 2, an insulating film 10
2. The back electrode 61, each of the photoelectric conversion layers 303 to 305, the transparent electrode 64, and the antireflection film 65 that constitute the stacked amorphous silicon solar cell 302 are formed in this order. That is, the stacked amorphous silicon solar cell 30
2 has a configuration in which the stacked photoelectric conversion layers 303 to 305 are electrically connected in series.

The photoelectric conversion layer 303 includes an N-type diffusion layer 310,
An I (Intrinsic) type layer 311 and a P type diffusion layer 312 are formed. The N-type diffusion layer 310 (thickness: 200 ° or less) is an amorphous silicon film having an optical gap of 1.5 to 1.6 eV.

The I-type layer 311 (film thickness: 500 to 1000)
Å) is made of a germanium amorphous silicon film having an optical gap of 1.3 to 1.45 eV. P-type diffusion layer 31
2 (thickness: 100 ° or less) has an optical gap of 1.7 to
It is made of 1.85 eV amorphous silicon carbide film.

The photoelectric conversion layer 304 includes an N-type diffusion layer 310,
It is formed of an I-type layer 313 and a P-type diffusion layer 312.
The I-type layer 313 (thickness: 2000 to 5000 °) is made of a germanium amorphous silicon film or an amorphous silicon film having an optical gap of 1.45 to 1.6 eV.

The photoelectric conversion layer 305 includes an N-type diffusion layer 310,
It is formed from an I-type layer 314 and a P-type diffusion layer 312.
The I-type layer 314 (thickness: 1000 ° or less) is made of an amorphous silicon carbide film or an amorphous silicon film having an optical gap of 1.6 to 1.8 eV.

(3) In each of the photoelectric conversion layers 303 to 305 and the transparent electrode 64, a contact hole 320 reaching the back electrode 61 is formed. Contact hole 32
The anti-reflection film 65 extends on the inner wall of the “0”. The back electrode 61 is connected to the negative electrode 69 via the contact hole 320. Therefore, the photoelectric conversion layers 303 to 305, the transparent electrode 64, and the negative electrode 69 are insulated by the antireflection film 65 on the inner wall of the contact hole 320.

(4) The transparent electrode 64 is connected to the positive electrode 68 via a contact hole 321 formed in the antireflection film 65. In the method of manufacturing the semiconductor device 301, the insulating layer 102 is formed by the same method as in the second embodiment, and the back electrode 61 is formed by the same method as the second method of the first embodiment. Each of the layers 310 to 314 forming the conversion layers 303 to 305 is formed using a CVD method in which an impurity is added to a source gas.

As described above, according to the present embodiment, the following operations and effects can be obtained. (1) CMOS is formed on the surface 2a of the P-type single crystal silicon substrate 2.
An inverter 3 is formed, and a stacked amorphous silicon solar cell 302 is formed on the back surface 2 b of the same substrate 2. Then, the stacked amorphous silicon solar cell 30
Power is supplied to the CMOS inverter 3 from the second through the respective electrodes 68 and 69. Therefore, the semiconductor substrate material can be effectively used, and the material cost can be reduced. In addition, the entire semiconductor device 1 can be reduced in size.

(2) The CMOS inverter 3 and the stacked amorphous silicon solar cell 302 are completely completely electrically separated by the insulating film 102. Therefore, the potential of the substrate 2 is not affected by the operation of the stacked amorphous silicon solar cell 302. Therefore, similarly to the second embodiment, it is possible to stabilize the potential of the substrate 2 and reliably prevent the CMOS inverter 3 from malfunctioning.

(3) Since the conductivity of each of the layers 310 to 314 of the photoelectric conversion layers 303 to 305 constituting the stacked amorphous silicon solar cell 302 can be set freely, the stacked amorphous silicon solar cell 302
Performance can be improved. In addition, each layer 310-314
In order to adjust the conductivity, the amount of impurities added by the CVD method may be set arbitrarily.

(4) Each of the electrodes 68 and 69 extends from the back surface 2b of the substrate 2 to the front surface 2a through the side surface 2c. Each of the electrodes 68 and 69 is connected to each of the electrodes 41D and 51.
D, 44, 54, 41S, and 51S are formed at the same time.
Therefore, the connection between the stacked amorphous silicon solar cell 302 and the CMOS inverter 3 can be easily and easily performed in the semiconductor manufacturing process without providing a wiring step.

(5) In the first to third embodiments, the output voltage of the single-crystal silicon solar cell 4 (the voltage between the positive electrode 68 and the negative electrode 69) is about 0.5V. Therefore, when the threshold voltages of the transistors 6 and 7 constituting the CMOS inverter 3 are high and the power supply voltage of the CMOS inverter 3 is high, it may be difficult to drive the CMOS inverter 3 with the single crystal silicon solar cell 4. .

On the other hand, the stacked amorphous silicon solar cell 302 has three photoelectric conversion layers 303 to 305.
Are electrically connected in series. Then, the output voltage of each of the photoelectric conversion layers 303 to 305 (voltage between the N-type diffusion layer 310 and the P-type diffusion layer 312)
Is about 0.5V. Therefore, the output voltage of the stacked amorphous silicon solar cell 302 is
~ 1.5V which is the sum of the output voltages of
It is easy to use for driving the CMOS inverter 3.

(Fifth Embodiment) Hereinafter, a fifth embodiment of the present invention will be described with reference to the drawings. In the present embodiment, the same components as those in the fourth embodiment have the same reference numerals, and a detailed description thereof will be omitted.

FIG. 5 shows a semiconductor device 401 of the fifth embodiment.
FIG. In the semiconductor device 401, the fourth
The difference from the semiconductor device 301 of the embodiment is as follows.

(1) The semiconductor device 301 comprises a CMOS inverter 3 formed on the front surface 2a of the substrate 2 and an integrated amorphous silicon solar cell 402 formed on the back surface 2b of the substrate 2.

(2) The integrated amorphous silicon solar cell 402 is formed from the photovoltaic elements 403a to 403c. Each of the photovoltaic elements 403a to 403c is arranged on the insulating film 102 formed on the back surface 2b of the substrate 2, and is electrically connected in series. That is, the integrated amorphous silicon solar cell 402 is
b each of the photovoltaic elements 403a to 403
03c are electrically connected in series.
An antireflection film 6 is formed on each of the photovoltaic elements 403a to 403c.
5 are formed.

(3) Each photovoltaic element 403a-403c
Are formed from a back electrode 61, a photoelectric conversion layer 404, and a transparent electrode 64. The photoelectric conversion layer 404 includes the N-type diffusion layer 3
10, an I-type layer 405, and a P-type diffusion layer 312. The I-type layer 311 (thickness: 3000 to 7000 °) is made of an amorphous silicon film.

The photovoltaic elements 403a, 403 adjacent to each other
03b is a photovoltaic element 4
03a is the transparent electrode 64 of the other photovoltaic element 403b
Are electrically connected in series by extending to the back electrode 61. Similarly, adjacent photovoltaic elements 40
3b and 403c are electrically connected in series by the transparent electrode 64 of one photovoltaic element 403b extending to the back electrode 61 of the other photovoltaic element 403c in the adjacent portion. . As a result, three photovoltaic elements 4
03a to 403c are electrically connected in series.

(4) A contact hole 410 reaching the conductive layer 61 is formed in the photovoltaic element 403a. An anti-reflection film 65 extends on the inner wall of the contact hole 410. Then, the photovoltaic element 403a
The conductive layer 61 is connected to the negative electrode 69 via the contact hole 410.

(5) Transparent electrode 6 of photovoltaic element 403c
4 is a contact hole 4 formed in the antireflection film 65.
11 is connected to the positive electrode 68.
In the method of manufacturing the semiconductor device 401, the insulating layer 10
2 is formed by the same method as in the second embodiment, and the back electrode 61 is formed by the same method as in the second manufacturing method of the first embodiment, and the respective layers 3 forming the photoelectric conversion layer 404 are formed.
10,405,312 are Cs obtained by adding impurities to the raw material gas.
It is formed by using the VD method.

As described above, according to the present embodiment, the following operations and effects can be obtained. (1) CMOS is formed on the surface 2a of the P-type single crystal silicon substrate 2.
An inverter 3 is formed, and an integrated amorphous silicon solar cell 402 is formed on the back surface 2 b of the same substrate 2. Then, the integrated amorphous silicon solar cell 40
Power is supplied to the CMOS inverter 3 from the second through the respective electrodes 68 and 69. Therefore, the semiconductor substrate material can be effectively used, and the material cost can be reduced. In addition, the entire semiconductor device 1 can be reduced in size.

(2) The CMOS inverter 3 and the integrated amorphous silicon solar cell 402 are completely electrically separated from each other by the insulating film 102. Therefore, the potential of the substrate 2 is not affected by the operation of the integrated amorphous silicon solar cell 402. Therefore, similarly to the second embodiment, it is possible to stabilize the potential of the substrate 2 and reliably prevent the CMOS inverter 3 from malfunctioning.

(3) Each layer 310 and 4 of the photoelectric conversion layer 404 constituting the integrated amorphous silicon solar cell 402
The conductivity of the integrated amorphous silicon solar cell 402 can be improved because the conductivity of the integrated amorphous silicon solar cell 402 can be freely set. Each layer 310, 405,
In order to adjust the conductivity of 312, the amount of impurities added by the CVD method may be arbitrarily set.

(4) Each of the electrodes 68 and 69 extends from the back surface 2b of the substrate 2 to the front surface 2a through the side surface 2c. Each of the electrodes 68 and 69 is connected to each of the electrodes 41D and 51.
D, 44, 54, 41S, and 51S are formed at the same time.
Therefore, the connection between the integrated amorphous silicon solar cell 402 and the CMOS inverter 3 can be easily and easily made in the semiconductor manufacturing process without providing a wiring step.

(5) The integrated amorphous silicon solar cell 402 has a configuration in which three photovoltaic elements 403a to 403c are electrically connected in series. And
The output voltage (voltage between the N-type diffusion layer 310 and the P-type diffusion layer 312) of each of the photovoltaic elements 403a to 403c is about 0.5V. Accordingly, the output voltage of the integrated amorphous silicon solar cell 402 is as high as about 1.5 V, which is the sum of the output voltages of the photovoltaic elements 403a to 403c, and is easy to use for driving the CMOS inverter 3.

The above embodiments may be modified as follows, and even in such a case, the same operation and effect can be obtained. (1) The electrodes 68 and 69 are replaced with wires. In this case, it is necessary to provide a wiring step for connecting the solar cells 4, 302, 402 and the CMOS inverter 3, but other operations and effects are the same as those of the above embodiments.

(2) Each electrode 68, 69 is made of metal,
It is formed using an organic conductive material such as polypyrrole, polyaniline, or polyacene. (3) Replace the solar cells 4, 302, 402 with polysilicon solar cells.

(4) As the material of the insulating film 102, an insulating resin film such as a polyimide resin film is used. (5) As the material of the back electrode 61, a doped polysilicon film, an organic conductive material film, or the like is used.

(6) The CMOS inverter 3 is replaced with an appropriate integrated circuit. Examples of such an integrated circuit include a semiconductor memory, various logic circuits, and a pixel portion of a liquid crystal display device in which liquid crystal driving elements such as MOS transistors and capacitors are arranged.

Further, the CMOS inverter 3 is replaced with a single electronic component such as a power transistor. (7) In the first or second embodiment, the DC output voltage of the single-crystal silicon solar cell 4 is supplied to an oscillator composed of an IIL or a MOS transistor having a small threshold voltage, and is converted into an AC voltage. The AC voltage is boosted and rectified by a transformer or a multi-stage cock / croft circuit to obtain a desired voltage. In this way, a high power supply voltage can be obtained even when the single-crystal silicon solar cell 4 is used, and the CMOS inverter 3 can be easily driven.

(8) The fourth embodiment and the third embodiment are used together. That is, the surface 2 of the P-type single crystal silicon substrate 2
1A, a CMOS inverter 3 is formed, and a stacked amorphous silicon solar cell 302 is formed on the CMOS inverter 3 via an interlayer insulating film 202.

(9) The fifth embodiment and the third embodiment are used together. That is, the surface 2 of the P-type single crystal silicon substrate 2
a, the CMOS inverter 3 is formed, and the integrated amorphous silicon solar cell 402 is formed on the CMOS inverter 3 via the interlayer insulating film 202.

(10) The P-type single-crystal silicon substrate 2 is replaced with an N-type single-crystal silicon substrate. (11) Normally, since the size of the semiconductor substrate 2 on which the integrated circuit is formed is as small as several mm to several tens of mm square, the size (light collecting area) of the solar cells 4, 302, 402 formed on the substrate 2 is also Therefore, it is difficult to increase the output power of the solar cell. In such a case, the solar cells 4, 302, 40
If 2 is used as an auxiliary power supply or a backup power supply, the effects described in the above embodiments can be obtained to some extent.

In recent years, in order to increase the capacity of a semiconductor memory or the like, a large number of functional chips for forming an integrated circuit are formed on a single wafer, and the entire wafer is cut into one without separating the functional chips. A wafer-scale integrated circuit device used as one device has been developed. When the above embodiments are applied to a wafer-scale integrated circuit device, the solar cells 4, 3
02, 402 can be formed, and the condensing area of the solar cells 4, 302, 402 can be increased. Therefore, the effects described in the above embodiments can be sufficiently obtained.

Although the embodiments have been described above, technical ideas other than the claims that can be grasped from the embodiments will be described below together with their effects. (A) In the semiconductor device according to any one of claims 1 to 6, the solar cell is a stacked amorphous solar cell (302) including a plurality of stacked photoelectric conversion layers (303 to 305). Semiconductor device.

(B) In the semiconductor device according to any one of claims 1 to 6, the solar cell comprises a plurality of photovoltaic elements (403) integrated planarly on a semiconductor substrate.
a to 403c), wherein each photovoltaic element is electrically connected in series.

According to (a) and (b), the output voltage of the solar cell can be increased, and a device having a high power supply voltage can be easily driven.
By the way, in this specification, the members according to the configuration of the present invention are defined as follows. (A) The device includes not only the CMOS inverter 3 but also a single memory such as a semiconductor memory, various logic circuits, a pixel portion of a liquid crystal display device in which liquid crystal driving elements such as MOS transistors and capacitors are arranged, and a power transistor. It also includes parts and the like.

(B) Solar cells include not only single-crystal silicon solar cells and amorphous silicon solar cells, but also polysilicon solar cells and compound solar cells. (C) The conductive film or the conductive layer includes not only a metal film but also a doped polysilicon film, an organic conductive material film, and the like.

(D) The insulating film includes not only a silicon oxide film and a silicon nitride film but also an insulating resin film and the like.

[0108]

According to the invention as set forth in any one of the first to sixth aspects, it is possible to reduce the material cost by effectively utilizing the semiconductor substrate material while stabilizing the substrate potential. A semiconductor device can be provided.

According to the second aspect of the present invention, since the device and the solar cell for powering the device are formed on the same semiconductor substrate, the material cost can be reduced by effectively utilizing the semiconductor substrate material. Can be. Further, since the conductive film or the insulating film is formed between the diffusion layer constituting the solar cell and the semiconductor substrate, the substrate potential can be stabilized.

According to the third aspect of the present invention, the device is formed on one main surface of the semiconductor substrate and the solar cell for power supply of the device is formed on the other main surface. Can be used effectively to reduce material costs. Further, since the conductive film or the insulating film is formed between the diffusion layer constituting the solar cell and the semiconductor substrate, the substrate potential can be stabilized.

According to the fourth aspect of the present invention, since a device is formed on a semiconductor substrate and a solar cell for powering the device is formed on the device, the material of the semiconductor substrate is effectively utilized. Material costs can be reduced. Further, since the insulating film is formed between the solar cell and the semiconductor substrate, the substrate potential can be stabilized.

According to the fifth aspect of the present invention, since the back electrode of the solar cell is used as the conductive film, the configuration can be simplified as compared with the case where the conductive film is provided separately from the solar cell. And cost can be reduced.

According to the sixth aspect of the present invention, since the conductive layer formed on the semiconductor substrate is used as the power line of the solar cell, the manufacturing process is more complicated than the case where a wire connecting the solar cell and the device is provided. It becomes simple and cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a first embodiment.

FIG. 2 is a schematic sectional view of a second embodiment.

FIG. 3 is a schematic sectional view of a third embodiment.

FIG. 4 is a schematic sectional view of a fourth embodiment.

FIG. 5 is a schematic sectional view of a fifth embodiment.

[Explanation of symbols]

 2 Single-crystal silicon substrate as semiconductor substrate 2a One main surface (front surface) of semiconductor substrate 2b Other main surface (back surface) of semiconductor substrate 2c Side surface of semiconductor substrate 3 CMOS inverter as device 4 Single crystal Silicon solar cell 61 ... Back electrode as conductive film 62 ... P-type diffusion layer 68 ... Positive electrode as conductive layer 69 ... Negative electrode as conductive layer 102 ... Insulating film 202 ... Interlayer insulating film 302 ... Laminated amorphous silicon Solar cell 310 ... N-type diffusion layer 402 ... Integrated amorphous silicon solar cell

Claims (6)

[Claims] 1. A semiconductor device comprising a device formed on a semiconductor substrate and a solar cell formed on the same semiconductor substrate. 2. A semiconductor substrate (2), a device (3) formed on the semiconductor substrate, and a solar cell (4, 302, 4) formed on the same semiconductor substrate.
02), and a conductive film (61) or an insulating film (102) formed between the solar cell and the semiconductor substrate, wherein power is supplied from the solar cell to the device. 3. A semiconductor substrate (2), a device (3) formed on one main surface (2a) of the semiconductor substrate, and a solar cell formed on another main surface (2b) of the same semiconductor substrate. A battery (4, 302, 402) and a conductive film (61) or an insulating film (102) formed between the solar cell and the semiconductor substrate, and power is supplied from the solar cell to the device. Semiconductor device. 4. A semiconductor substrate (2), a device (3) formed on the semiconductor substrate, and a solar cell (4) formed on the device via an insulating film (202); A semiconductor device in which power is supplied from the solar cell to the device. 5. The semiconductor device according to claim 1, wherein said conductive film is a back electrode of said solar cell. 6. The semiconductor device according to claim 3, wherein
A conductive layer (68, 69) extending from one main surface of the semiconductor substrate to the other main surface through the side surface (2c), and the conductive layer is used for supplying power from the solar cell to the device. A semiconductor device used as a power line.