JPH1050724A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the tail current at a lower power voltage of an insulated gate bipolar transistor IGBT improved to provide a low lifetime region by the ion beam irradiation, without increasing the withstand voltage deterioration, leakage current and ON-voltage. SOLUTION: An n<-> type base layer 11 is formed so that the width of a non-depletion region is 40μm or more. A first irradiation of Hu2+ forms a first low lifetime layer 21 having a deeper recombination level in the base layer 10 at about 20μm off from a p type collector layer 18 and second irradiation of H<2+> forms a second low lifetime layer 22 having a shallower recombination level at about 60μm off from the p type collector layer 18. Thus approximately the entire excessively remaining nondepleted region 11a is converted into a low lifetime one.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a conductivity modulation type semiconductor device, and more particularly, to an IGBT.
(Insulated Gate Bipolar Transistor) is used for an insulated gate bipolar transistor.

[0002]

2. Description of the Related Art Conventionally, IGBTs have been MOS-FETs.
And BJT can be understood as a composite structure,
The structure and basic operation are well known (for example, see Japanese Patent Application Laid-Open No. 57-120369).

FIG. 6 shows a schematic configuration of an IGBT taking an N-channel type as an example. For example, P-type collector layer 1
01, a high resistance N ⁻ -type base layer 102 having a low impurity concentration.
Are formed. The surface of the N ⁻ -type base layer 102 is formed with a P
A type base layer 103 and an N ⁺ type emitter layer 104 are selectively formed on the surface of the P type base layer 103.

A thin insulating film 105 is formed on the surfaces of the N ⁻ type base layer 102 and the P type base layer 103.
, A polysilicon gate electrode 106 is provided. Further, the N ⁺ -type emitter layer 104 and the P ⁺
On the surface of the mold base layer 103, a metal emitter electrode 107 is provided so as to short-circuit each other.

Further, the polysilicon gate electrode 10
6 and the metal collector electrode 109 connected to the P-type collector layer 101.
Are provided respectively.

Next, a general method for manufacturing the above-described N-channel type IGBT will be described. First, the P-type collector layer 1
01 as a P ⁺ type substrate, and an N ⁻ type base layer 1 thereon.
02 is vapor-phase grown to form a P ⁺ -N ^- wafer.

After that, an insulating film 105 is formed on the surface of the N ⁻ type base layer 102, and a polysilicon gate electrode 106 is formed thereon. Next, the polysilicon gate electrode 106 is partially opened, and the P-type base layer 103 is formed using the opening as a mask. Also, the P-type base layer 103
The upper insulating film 105 is partially opened, and an N ⁺ -type emitter layer 104 is formed using the polysilicon gate electrode 106 and the insulating film 105 as a mask.

Then, an insulating film 105 is formed again on the polysilicon gate electrode 106 and the P-type base layer 103, and after the insulating film 105 is partially removed, the polysilicon gate electrode 106 and the N ⁺ -type emitter layer 104 are removed. A metal is deposited on an exposed portion of the P-type base layer 103 including the metal gate electrode 108 and the metal emitter electrode 107.

[0009] Thereafter, a metal collector electrode 109 is formed under the P ⁺ type collector layer 101, and the IGB shown in FIG.
T is obtained. It should be noted that, even when a P ⁺ -N ^- wafer in which the N ^- type base layer 102 is an N ^- type substrate and the P-type collector layer 101 is provided by impurity diffusion is used, the IGB
T is obtained.

Next, the operation principle of the above-described N-channel type IGBT will be described. When the IGBT is turned on, the metal emitter electrode 107 is grounded and the metal collector electrode 1 is turned on.
09 with the positive voltage applied to the metal gate electrode 10
8 is realized by applying a positive voltage to the metal emitter electrode 107.

[0011] That is, when a positive voltage is applied to the metal gate electrode 108, similarly to the MOS-FET, an inversion channel is formed on the surface of the P-type base layer 103, through the inversion channel from the N ⁺ -type emitter layer 104 Electrons flow into the N ⁻ type base layer 102.

[0012] In contrast, the P-type collector layer 101 N ^- injection of holes so as to satisfy the charge neutrality condition type base layer 102 takes place, P type collector layer 101 and the N ^- the mold base layer 102 The PN junction is in a forward bias state.
As a result, the conductivity of the N ⁻ type base layer 102 is modulated, and the element is brought into a conductive state.

As described above, the ON state of the IGBT is caused by the fact that the high resistance N ⁻ -type base layer 102 is modulated by conductivity modulation.
The resistance component becomes extremely small. For this reason, even in a high-breakdown-voltage element having a low concentration of the N ⁻ -type base layer 102 and a high withstand voltage, an extremely low ON resistance can be obtained.

On the other hand, the turn-off of the IGBT is realized by applying a negative voltage to the metal gate electrode 108 and to the metal emitter electrode 107. That is, when a negative voltage is applied to the metal gate electrode 108, the inversion channel disappears and the flow of electrons from the N ⁺ -type emitter layer 104 stops. However, electrons still exist in the N ⁻ -type base layer 102.

Most of the holes accumulated in the N ⁻ type base layer 102 flow out to the metal emitter electrode 107 through the P type base layer 103, but part of the holes accumulate in the N ⁻ type base layer 10.
Recombine with the electrons present in 2 and disappear.

When all the holes accumulated in the N ^- type base layer 102 have disappeared, the device enters a blocking state and the turn-off is completed. The IGBT is an excellent element showing an extremely low on-resistance among the high withstand voltage elements. However, since it is a minority carrier element, the IGBT has a turn-off time of MOS-
It is longer than unipolar elements such as FETs.

In order to shorten the turn-off time of the IGBT, conventionally, as shown in FIG. 7, for example, as shown in FIG. 7, diffusion of heavy metals such as Au or Pt, or irradiation of neutrons, gamma rays, electron beams, or the like, has been carried out. ^- type base layer 1
A method of reducing the carrier lifetime by generating a defect 110 serving as a recombination center in the entire region of 02 is adopted.

However, in this method, the turn-off time is improved, but at the same time, the carrier lifetime in the entire area of the N ⁻ type base layer 102 is shortened, so that the conduction in the entire area of the N ⁻ type base layer 102 is reduced. The degree of degree modulation also decreases, and there is a problem that the low on-resistance characteristic which is the greatest advantage of the IGBT is deteriorated.

In recent years, instead of the above-described lifetime control method by heavy metal diffusion or radiation irradiation, for example, as shown in FIG. 8, by irradiating ionic species such as He ³⁺ and H ²⁺ , the N ⁻ type base layer is formed. Attempts have been made to locally shorten the lifetime in the depth direction within 102.

Ion species such as He ³⁺ and H ²⁺ can be changed in the N ⁻ type base layer 102 by changing the acceleration voltage at the time of irradiation or by irradiating an Al thin film as an absorber with a constant acceleration voltage. Defect 11 that becomes a recombination center at an arbitrary depth
0 can be generated locally.

[0021] When the life time control method according to the ion beam irradiation, N ^- since -type base layer 102 defects 110 optionally localized in the depth direction of the can forming, N ^- type base layer 102 in The hole distribution can be optimally controlled (that is, the degree of conductivity modulation can be optimized), and the speed can be increased without increasing the on-resistance as compared with the case of the lifetime control method by irradiation of radiation or the like.

However, the above-described lifetime control method by ion beam irradiation still has the following problems. The blocking voltage of the IGBT is
It is substantially determined by the base open breakdown voltage V _CBO of the PNP-Tr parasitic in the IGBT. Therefore, in the blocking state, for example, as shown in FIG. 9, the depletion layer 111 grows and the base layer (N ⁻ type base layer 102) of the parasitic PNP-Tr is depleted.

[0023] In this case, PNP-Tr is cause Early effect, the effective base width W _B is modulated (shortening). By effective base width W _B becomes shorter, common emitter current gain beta _o of the parasitic PNP-Tr is increased based on the two numbers of the following formula.

[0024]

(Equation 2)

[0025] However, L _P is diffusion length of the holes, W _B is the effective base width, N _E, N _B is the emitter concentration respectively, a base density. Meanwhile, related to the open-base breakdown voltage V _CBO and its leakage current I _{CB O} of PNP-Tr, the emitter opening breakdown voltage V _CEO and its leakage current I _CEO, number of the following formula 3, such as the number 4 .

[0026]

(Equation 3)

[0027]

(Equation 4)

[0028] Here, an increase in the common emitter current gain beta _o of the parasitic PNP-Tr due to modulation of the effective base width W _B, the increase of the reduction and the leakage current I _CEO emitter opening breakdown voltage V _CEO, i.e., This suggests that the IGBT causes a decrease in V _CES and an increase in I _CES , and is unstable in reliability.

[0029] As previously mentioned, such as by irradiation with an electron beam N ^- when the type base layer 102 in the entire region and the low lifetime reduction, depletion proceeds, even if the effective base width W _B becomes smaller, non-depleted Since the hole diffusion length L _P in the activated region is sufficiently low, the grounded emitter current gain β of the parasitic PNP-Tr
_o hardly increases.

On the other hand, a low lifetime layer (defect 1) localized in the N ⁻ -type base layer 102 by ion beam irradiation.
In the case of forming a 10), the low lifetime layer localized will be incorporated into the depletion layer 111, suddenly grounded emitter current gain beta _o of the parasitic PNP-Tr increases. This causes a decrease in V _CES and an increase in I _CES , causing thermal runaway and sometimes thermal destruction of the device. Next, problems during the switching operation will be described. The collector current I _{C of the} IGBT is represented by the following equation (5).

[0031]

(Equation 5)

[0032] However, Z is the channel perimeter, L is the channel length, .mu.n is the mobility, C _o is a gate insulating film capacitance, V _G is the gate voltage, V _T is the threshold voltage, V _C is the collector voltage .

[0033] Also during this switching operation, as in the case described above, when the low lifetime layer localized at the switching turn-off is taken into the depletion layer 111, the parasitic PNP-Tr grounded emitter current gain beta _o With the increase, the collector current I _{C of the} IGBT is bent, which is a current-voltage product at the time of switching off.
There is a problem that the switching turn-off loss increases (see FIG. 10).

Regarding these problems, for example, N ⁻
The problem can be solved to some extent by designing the thickness and concentration of the mold base layer 102 so as to satisfy the following equation (6).

[0035]

(Equation 6)

[0036] However, W _B is the effective base width, ε _S, ε _O
Is the dielectric constant and vacuum dielectric constant of silicon, Vbi is the internal voltage of the PN junction between the P-type base layer 103 and the N ⁻ -type base layer 102, and V is the collector voltage ((desired withstand voltage)). , N _B is the base concentration,
q is the amount of charge.

The first term of the above equation (6) indicates the width of the depletion layer 111 at a certain applied voltage.
The term is the distribution width of the defect 110 formed by ion beam irradiation.

The defect distribution width when silicon is irradiated with ion species such as He ³⁺ and H ²⁺ is, for example, about 40 μm according to the SR (Spreding Resistance) method as shown in FIG. It hardly depends on the dose of the ion species or the substrate concentration.

[0039] Therefore, to satisfy the equation above having 6, do it with the effective base width W _B to set to a desired withstand voltage, which is formed by irradiation of the ion beam, low lifetime localized layer since fall within the non-depleted region to break down, to maintain more than enough low common emitter current gain beta _o.

[0040] That is, by setting the effective base width W _B to the above 40 [mu] m, the parasitic PNP-Tr modulation grounded emitter current gain beta _o of (increase) can be suppressed, increase in the breakdown voltage deterioration and leakage current, and In addition, problems such as an increase in switching turn-off loss can be avoided.

However, even when the condition of the above equation (6) is satisfied, the following problem still remains. That is, as described above, the turn-off of the IGBT is mostly determined by the carrier lifetime, but like other bipolar elements such as BJT, the P-type base layer 103 and the N ⁻ -type base layer 102 are turned off at the time of turn-off.
The minority carriers (holes) in the N ⁻ -type base layer 102 are forcibly swept out by the depletion layer formed by reverse biasing the PN junction with the PN junction.

For this reason, when the power supply voltage is equal to or lower than the element breakdown voltage (usually, it is often used at about half of the standard), for example, as shown in FIG. The tail current increases due to the excessive area remaining and the excessive minority carrier remaining.

This problem can be solved by simply increasing the dose at the time of ion beam irradiation. However, as a matter of course, the on-state voltage rapidly deteriorates. Conventionally, for example, as shown in FIG. 13, a structure in which an N ⁺ type buffer layer 120 is provided between a P type collector layer 101 and an N ⁻ type base layer 102 (P ⁺ -N ⁺ -N ^- wafer) ) Is also in practical use, but in this IGBT as well,
There was the same problem as T.

[0044]

As described above [0008] In the prior art, increase of the breakdown voltage deterioration and leakage current, and the increase of the switching turn-off losses, the effective base width W _B
However, when the power supply voltage is low, the tail current is increased.

Therefore, the present invention is highly reliable, has a small tail current even when the power supply voltage is relatively low, does not cause deterioration of the breakdown voltage or increases the leakage current, and has a small on-voltage and turn-off time. It is an object of the present invention to provide a semiconductor device capable of improving the trade-off of the semiconductor device.

[0046]

In order to achieve the above object, in a semiconductor device according to the present invention, a first region composed of a semiconductor layer of a first conductivity type and one of the first region are formed. A second region formed of a second conductivity type semiconductor layer selectively formed on the main surface; and a second region formed of a first conductivity type semiconductor layer selectively formed on one main surface of the second region. The first region including a third region, a fourth region formed of a second conductivity type semiconductor layer formed on the other main surface of the first region, and at least a part of the second region. A control electrode formed on the second region via an insulating film, a first electrode formed on the second region including at least a part on the third region, and a fourth electrode formed on the second region. Consisting of a second electrode formed thereon and a plurality of recombination center lattice defects localized in the first region. It has been.

According to the semiconductor device of the present invention, almost the entire non-depleted region can be substantially reduced in lifetime. Thereby, even when the external power supply voltage is relatively low and the non-depleted region remains excessively, it is possible to reduce the excess minority carriers in the non-depleted region.

[0048]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a conductivity modulation type semiconductor device according to an embodiment of the present invention, so-called IGBT (Insulated Gate Bipolar Transistor).
FIG. Here, an N-channel type IGBT will be described as an example.

For example, a P-type base layer (second region) 12 is selectively formed on the surface of a high-resistance N ⁻ -type base layer (first region) 11 having a low impurity concentration. This P
On the surface of the mold base layer 12, an N ⁺ -type emitter layer (third region) 13 is selectively formed.

[0050] Then, the N ^- type base layer 11 and, the the N ^- adjacent to the mold base layer 11 above the P type base layer 12 surface through the thin insulating film 14, a polysilicon gate electrode (control An electrode 15 is provided.

The surface of the N ⁺ -type emitter layer 13 and the surface of the P-type base layer 12 sandwiched between the N ⁺ -type emitter layers 13 are short-circuited to each other.
A metal emitter electrode (first electrode) 16 is provided.

Further, the polysilicon gate electrode 15
A metal gate electrode 17 is provided above and connected thereto. On the other hand, a P-type collector layer (fourth region) 18 is formed on the back surface of the N ⁻ -type base layer 11, and a metal collector electrode (second electrode) 19 is provided so as to be connected thereto. ing.

Then, in the N ⁻ type base layer 11,
For example, 20 μm from the contact surface with the P-type collector layer 18.
m and a second low lifetime layer (recombination center lattice defect) 21 having a defect peak at about 60 m, and a second low lifetime layer having a defect peak at about 60 μm from the contact surface with the P-type collector layer 18. And a lifetime layer 22.

The first and second low lifetime layers 21,
The formation of 22 is performed, for example, by irradiating each of H ²⁺ ion species from the metal collector electrode 19 side using Al thin films having different thicknesses as absorbers.

Next, a method for manufacturing the above-described N-channel type IGBT will be described. First, for example, a 280-μm-thick substrate (N ⁻ -type base layer 11) is prepared by doping silicon with an impurity such as phosphorus and having a low impurity concentration and a specific resistance of 70 Ω · cm.

Then, a BSG film is formed on the back surface of the substrate by CV.
After being formed by the D (Chemical Vapor Deposition) method, a P-type collector layer 18 is formed by using this as a diffusion source to a thickness of 80 μm.
The diffusion is formed with a thickness of m.

After removing the BSG film, the N ⁻ type base layer 1 is removed.
1 is oxidized to form an insulating film 14 having a thickness of about 1000 angstroms, and polysilicon is formed thereon to a thickness of about 5000 angstroms.

Thereafter, the polysilicon is partially opened to form a polysilicon gate electrode 15, and boron is applied to the polysilicon gate electrode 15 as a mask to a thickness of 8 μm.
The P-type base layer 12 is formed by being diffused with a thickness of the order of magnitude.

Next, the insulating film 14 between the polysilicon gate electrodes 15 is partially opened, and this is used as a mask for forming an emitter, and under the condition of a dose amount of about 5 × 10 ¹⁵ cm ⁻² , ions of As Implantation and heat treatment are performed to form an N ⁺ -type emitter layer 13 in the P-type base layer 12.

After the insulating film 14 is formed on the surface again by the CVD method to a thickness of about 15,000 angstroms,
The insulating film 14 is selectively removed, and the P-type base layer 12 and the N ⁺
A hole is formed so that a part on the mold emitter layer 13 is exposed.

Then, a metal film such as Al is formed on the surface so as to fill the opening, and the metal film is patterned to form the metal emitter electrode 16 and the metal gate electrode 17, respectively.

On the other hand, V or Au is formed on the surface of the P-type collector layer 18 formed on the back surface of the N ⁻ -type base layer 11.
A metal film such as a metal collector electrode 19 is formed.
And

On the metal collector electrode 19, 75 μm
An Al thin film having a thickness of about m is formed as an absorber to protect the back surface of the device, and from this back surface, an acceleration voltage of 4.5 MeV and a dose amount of 1 × 10 ¹⁰ to 1 × 10 ¹² cm ^−2.
The first irradiation of H ²⁺ is performed under the conditions described above to form the first low lifetime layer 21 in the N ⁻ type base layer 11.
At this time, a defect peak is formed in the first low lifetime layer 21 at a position near 20 μm from the P-type collector layer 18, and has a distribution width of ± 20 μm with respect to the peak position.

Subsequently, the back surface of the device was protected by using an Al thin film having a thickness of about 35 μm as an absorber.
Accelerating voltage 4.5 MeV, dose 1 × 10 ⁹ -1 × 10
¹¹ under conditions of m ^-2, performs irradiation of the second H ^2+, N ^-
A second low lifetime layer 22 is formed in the mold base layer 11. At this time, a defect peak is formed in the second low lifetime layer 22 at a position near 60 μm from the P-type collector layer 18 and has a distribution width of ± 20 μm with respect to the peak position.

As described above, the structure shown in FIG.
An N-channel IGBT is completed. FIG. 2 shows a state of hole distribution in the N ⁻ -type base layer 11 due to the formation of the low lifetime layers 21 and 22 in the above-described N-channel type IGBT.

According to such a configuration, even if the power supply voltage is relatively low and the non-depleted region 11a remains excessively,
Since the entire region of the non-depleted region 11a is substantially reduced in lifetime by the first and second irradiations of H ²⁺ , the number of excess minority carriers in the non-depleted region 11a is small, and the tail current is reduced. It can be reduced efficiently.

[0067] That is, in this IGBT, as the effective base width W _B of about 190 .mu.m, N ^- 280 .mu.m thickness -type base layer 11 satisfies the equation of the above conditions 6
Is set to Thereby, for example, when the power supply voltage is
At 00 V, the extension width of the depletion layer 11b is about 110 μm, and the remaining width of the non-depletion region 11a is about 80 μm. However, the localized second low lifetime layer 22 exists near 60 μm. In addition, the entire area in the non-depleted region 11a is completely reduced in life time.

The second dose of H ²⁺ is one order of magnitude lower than the first dose, that is, the low lifetime layer 22 due to the second ion beam irradiation is a low lifetime layer 22 due to the first ion beam irradiation. Since it is shallower than the recombination order of No. 21, no extreme increase in on-voltage is caused.

In addition, the low lifetime layer 21 formed by localization by the first irradiation of H ²⁺ causes parasitic P
Since the emitter ground current gain β _o of the NP-Tr is rate-limiting, the power supply voltage rises, and the low lifetime layer 22 formed by localization by the second irradiation of H ²⁺ is taken into the depletion layer 11b. Even so, the modulation of the common emitter current gain β _o can be ignored, and there is no reduction in breakdown voltage and no increase in I _CES and switching turn-off loss.

FIG. 3 shows a trade-off curve of the IGBT (element of the present invention) having the above-described structure in comparison with a conventional element. Here, an IGBT formed by forming a localized low lifetime layer by one ion beam irradiation is shown as a conventional element.

As is clear from this figure, according to the element of the present invention, even when the power supply voltage is equal to or lower than the element withstand voltage (600 V), the fall time (switching characteristic) tf is obtained.
It can be seen that the collector-emitter saturation voltage V _CE (on-voltage characteristic) is smaller than that of the conventional device, and the trade-off is improved.

As described above, almost the entire non-depleted region in the N ⁻ -type base layer can be substantially reduced in life time. That is, the localized low lifetime layers are formed at a position near 20 μm and a position near 60 μm from the P-type collector layer in the N ⁻ -type base layer. Thereby, even when the external power supply voltage is relatively low and the non-depleted region remains excessively, the entire region in the non-depleted region can be completely reduced in lifetime. Therefore, excess minority carriers in the non-depleted region can be reduced, and the tail current can be reduced efficiently.

Further, since the low lifetime layer formed locally at about 60 μm is shallower than the recombination order of the low lifetime layer formed locally at about 20 μm, the on-state voltage is reduced. Does not cause an extreme increase in

Further, since the low lifetime layer formed locally at about 20 μm is designed so as not to be taken into the depletion layer, the breakdown voltage is reduced, the leakage current is increased, and There is no increase in switching turn-off loss.

In the above-described embodiment of the present invention, the case where H ²⁺ is irradiated to form the low lifetime layer has been described. However, the present invention is not limited to this. For example, He ³⁺ or heavy Irradiation with protons (Deuteron) or the like can be similarly performed.

Instead of two ion beam irradiations, a plurality of ion beam irradiations with different ranges may be performed as necessary. In addition, not only ion beam irradiation but also light electron beam irradiation can be combined.

Further, as shown in FIG. 4, a P-type collector layer 18 'having an uneven shape may be formed.
In this case, if the effective base width W _B to determine the projected portions of the P-type collector layer 18 'can be expected substantially the same effects as IGBT having the structure shown in FIG.

[0078] Moreover, for the concave portion, amount that is effective base width W _B becomes longer, the area common emitter current gain beta _o increases in, for withstand voltage deterioration and leakage current of the structure shown in FIG. 1 IGBT More advantageous than

As shown in FIG. 5, an N ⁺ type buffer layer 3 is provided between N ⁻ type base layer 11 and P type collector layer 18.
The present invention is also applicable to an IGBT having a configuration in which 0 is provided. Furthermore, it is not limited to the N-channel IGBT of the 1200 V system,
For example, it goes without saying that the present invention can be similarly applied to a P-channel type IGBT.
The same applies to BT. Of course, various modifications can be made without departing from the scope of the present invention.

[0080]

As described in detail above, according to the present invention, the tail current can be increased with high reliability without causing the deterioration of the breakdown voltage and the increase of the leakage current even when the power supply voltage is relatively low. A semiconductor device which is small and can improve a trade-off between on-voltage and turn-off time can be provided.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a schematic configuration of an N-channel IGBT according to an embodiment of the present invention.

FIG. 2 is a diagram showing an N-channel type IGBT,
^- schematic diagram showing the state of distribution of holes in the mold base layer.

FIG. 3 is a schematic diagram showing a trade-off curve of an N-channel IGBT in comparison with a conventional device.

FIG. 4 is a schematic cross-sectional view of an N-channel IGBT according to another embodiment of the present invention.

FIG. 5 shows N according to still another embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view of a channel type IGBT.

FIG. 6 is shown to explain the prior art and its problems;
FIG. 2 is a schematic cross-sectional view of an N-channel IGBT.

FIG. 7 is a schematic view similarly illustrating a low carrier lifetime method by irradiation with an electron beam.

FIG. 8 is a schematic view similarly illustrating a low carrier lifetime method by ion beam irradiation.

FIG. 9 is a schematic diagram showing the growth of a depletion layer in an IGBT blocking state and its equivalent circuit.

FIG. 10 is a schematic diagram showing a turn-off waveform of the IGBT.

FIG. 11 is a schematic view similarly illustrating the dependency of the dose distribution on the defect distribution profile due to ion beam irradiation.

FIG. 12 is a schematic diagram similarly illustrating the dependency of a tail current on a power supply voltage.

FIG. 13 is a schematic cross-sectional view showing another configuration of the N-channel IGBT.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... N ^- type base layer 11a ... Depletion region 11b ... Depletion layer 12 ... P type base layer 13 ... N ⁺ type emitter layer 14 ... Insulating film 15 ... Polysilicon gate electrode 16 ... Metal emitter electrode 17 ... Metal gate electrode 18 P-type collector layer 19 Metal collector electrode 21 First low-lifetime layer 22 Second low-lifetime layer

Claims (8)

[Claims] A first region formed of a semiconductor layer of a first conductivity type; and a second region formed of a semiconductor layer of a second conductivity type selectively formed on one main surface of the first region. A third region formed of a semiconductor layer of the first conductivity type selectively formed on one main surface of the second region, and a second region of the second conductivity type formed on the other main surface of the first region. A fourth region made of a semiconductor layer, and at least a part on the second region;
A control electrode formed on a region of the second region via an insulating film;
A first electrode formed on the region, a second electrode formed on the fourth region, and a plurality of recombination center lattice defects localized in the first region. A semiconductor device comprising: 2. The method according to claim 2, wherein each of the recombination center lattice defects is the fourth recombination center lattice defect.
2. The semiconductor device according to claim 1, wherein the closer to the region, the deeper the recombination order. 3. The recombination center lattice defect having the deepest recombination order among the recombination center lattice defects has a peak value of the recombination center whose width of the non-depleted region is at least 40 μm or more. 2 from the other main surface of the first area
The semiconductor device according to claim 1, wherein the semiconductor device is located near 0 μm. 4. Each of the recombination center lattice defects is He ³⁺ ,
2. The semiconductor device according to claim 1, wherein the semiconductor device is formed by irradiation of ion species such as H2 ⁺ and deuteron. 5. The semiconductor device according to claim 1, wherein the first region has a substantially reduced lifetime over substantially the entire non-depleted region. 6. The effective width (W _B ), its concentration (N _B ), and breakdown voltage (V) of the first region are expressed by the following equation (1). 2. The semiconductor device according to claim 1, wherein the following is substantially satisfied. 7. The semiconductor device according to claim 1, wherein the fourth region has a surface in contact with the first region having irregularities. 8. The semiconductor device according to claim 1, wherein a fifth region made of a semiconductor layer of a first conductivity type is further formed between the first region and the fourth region. 3. The semiconductor device according to claim 1.