JPH10340340A - Image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processor which improves versatility and the use efficiency of resource by changing image processing configuration corresponding to the bit width of image data to be handled. SOLUTION: This device is provided with a line memory 5 for storing image data, constitution control part 3 for controlling the input/output constitution of line memory 5, input data control circuit 200 and output data control circuit 300 or the arithmetic constitution of image processing part 90 based on an image processing function to be set together with the bit width of image data, line memory input data control circuit 200 for controlling the generation of data to be inputted to the line memory 5 according to input/output control from the constitution control part 3, and line memory output data control circuit 200 for controlling data outputted from the line memory 5 and distributing them to the image processing part 90.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a general-purpose image processing apparatus in which the bit width of image data to be handled is diversified, and more particularly to an image processing apparatus capable of changing a processing configuration according to the bit width of image data.

[0002]

2. Description of the Related Art There is a method of performing a filter process, which is one of image processes, at a high speed by performing a process while storing image data in a line memory (LM). The method using the LM can partially perform the processing required for the filter processing in parallel. Further, it is possible to perform the filtering process by simply scanning the screen.

FIG. 2 shows a schematic configuration of an image processing apparatus using LM. FIG. 3A shows that the bit width of the image data is 8 bits.
The configuration in the case of 3 × 3 filter processing when bits are set is shown. In the 3 × 3 filter processing, nine image data including neighboring pixels are required for processing a certain pixel. These nine image data are given by a combination of two line memories and image data read from the processing target memory. Then, by using nine image data and nine coefficients used in the filter processing and performing a product-sum operation in parallel by using nine multipliers, the filter processing is executed at high speed.

When the bit width of image data handled by the same 3 × 3 filter is 16 bits, two line memories having a width of 16 bits are used as shown in FIG. Further, when the bit width of the image data is 8 bits and 5 × 5 filter processing is realized, four line memories of 8 bit width are required as shown in FIG. 2C.

Conventionally, 16-bit image data has been used in medical image processing requiring high resolution, and 8-bit or 1-bit image data has been used in image processing in other fields. Recently, there has been an increasing need for image processing using 16-bit width image data even in the industrial field.

[0006]

A conventional image processing apparatus using a line memory is fixedly configured according to the specification of the maximum bit width of image data to be processed. That is, in consideration of 3 × 3 filter processing, an image processing apparatus that handles image data having a maximum width of 8 bits is shown in FIG.
The image processing apparatus having the configuration shown in FIG. 2A and handling image data having a maximum width of 16 bits has the configuration shown in FIG. 2B. Therefore, in an image processing apparatus that handles image data of 1-bit width, 8-bit width, and 16-bit width, it is necessary to adopt the processing configuration of FIG.

However, using the processing configuration of FIG.
When processing image data having a bit width or an 8-bit width, there is a problem that many unused memory areas are present in the line memory, and the use efficiency of the memory is low and it is not economical.

Further, FIG. 2 for realizing 5 × 5 filter processing
In the processing configuration (c), the same problem as described above occurs when image data with a small bit width is handled. further,
When the 3 × 3 filter processing is performed, there is a problem that many unused circuits exist not only in the line memory but also in the filter processing arithmetic unit.

The low use efficiency as described above is an important problem when speeding up processing. In general, pipeline processing is used for speeding up when a plurality of filter processes are continuously performed, and parallel processing for dividing a screen into small regions and performing processing for each small region is used for speeding up a single filter process. be able to. However, these pipeline processing and parallel processing require a large scale of a line memory and an arithmetic unit, and therefore, solving the above problems becomes an important issue.

An object of the present invention is to overcome the problems of the prior art, to flexibly change the processing configuration in accordance with the bit width of image data to be handled and the processing function, and to realize image processing with excellent versatility and high resource use efficiency. It is to provide a device. Another object of the present invention is to provide an image processing apparatus which can arbitrarily configure pipeline processing and parallel processing capable of high-speed processing according to the bit width of image data.

[0011]

An object of the present invention is to provide an image processing apparatus for inputting image data to be processed to an image processing circuit using a line memory having a line width of a plurality of bits. The line width of the line memory is cut in accordance with the width to theoretically constitute a plurality of divided line memories, and the number of divided lines to be used in accordance with the set image processing function information (hereinafter abbreviated as setting function) This is achieved by providing a configuration for controlling the input and output of the memory so as to correspond to the image processing circuit.

In the above configuration, according to the setting function,
The image processing circuit has a function of controlling a combination of a plurality of arithmetic circuits, and is capable of changing a processing size such as 3 × 3 or 5 × 5 and / or changing a processing mode such as pipeline or parallel processing. Features.

That is, the image processing apparatus according to the present invention has an image memory for storing image data to be processed, an image processing circuit for performing predetermined image processing, and image data read from the image memory adapted to the processing size. In an image processing apparatus including a line memory that outputs block data to the image processing circuit, a line width of the line memory is cut in accordance with a bit width of the image data, and theoretically, a plurality of divided line memories are configured, and Configuration control means for controlling the input / output of the number of divided line memories used in accordance with the setting function so as to correspond to the image processing circuit, and line memory input data for generating input data to be input to the line memory Control means, and a line manager for generating the block data from the data output from the line memory. Characterized in that it comprises a re-output data control means.

If the number L used is (i−1) × P in the P-stage pipeline processing by the i × i filter processing having a different setting function, the configuration control means performs the pipeline processing. The divided line memory used for each stage is an L / P line group, and a line group including a divided line memory for directly inputting image data read from the image memory is associated with the image processing circuit at the foremost stage. The input / output of the line memory is controlled so that the image processing circuits of the next and subsequent stages sequentially correspond to the line group including the divided line memory for inputting the processing data of the previous stage.

If the setting function is a parallel processing of Q sets by the same i × i filter processing, and the number L to be used is (i−1) × Q, the configuration control means performs each processing of the parallel processing. The divided line memory used in the set is an L / Q line group, and one screen of the image data stored in the image memory is vertically divided into Q, and the image data read out in parallel from each area is obtained. , Is controlled so as to be input to a corresponding line group.

Further, the configuration control means, when a processing mode such as a filter size (i × i) indicating the setting function, the number of processes (1 or P or Q), and a pipeline is set, the number of processes corresponding to the number of processes. Is controlled so as to be constituted by an arithmetic circuit corresponding to the filter size.

According to the present invention, by changing the bit width of the line memory for one line in accordance with the bit width of the image data to be handled, the theoretical number of line memories can be changed. For example, when a line memory having a 32-bit width realizing the same function as that of FIG. 2B is used, and when image data having a bit width of 16 bits is handled, the processing is the same as that of FIG. When handling image data having a width of 8 bits, the line memory can be controlled as shown in FIG. That is, since the processing configuration can be changed according to the bit width of the image data to be handled, the versatility and use efficiency of the image processing apparatus can be improved.

Further, according to the present invention, since the input / output of the line memory can be controlled according to the setting function of the image processing, a processing configuration capable of high-speed processing such as a plurality of stages of pipeline processing and a plurality of sets of parallel processing. Can be easily constructed.

Therefore, according to the present invention in which the configurations of the line memory and the image circuit are variably controlled as described above, an image processing apparatus including, for example, a line memory having a 32-bit width and a product-sum operation circuit capable of performing 5 × 5 filter processing. In the case of, the image data is 3 × 3 filter processing of 16 bit width, the image data is 5 × 5 or 3 × 3 filter processing of 1 to 8 bit width, or the image data is 3 × 3 filter of 1 to 8 bit width. A general-purpose image processing apparatus capable of arbitrarily configuring and controlling pipeline processing or parallel processing by filter processing can be provided.

[0020]

An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a functional block diagram illustrating an overall configuration of an image processing apparatus according to an embodiment. Arrows indicating the flow of signals in the drawing correspond to pipeline processing described later.

The configuration control unit 3 receives detailed information of image data to be processed from the control device 1 and interprets it. Further, interpreting the image processing function transmitted from the control device 1,
A control signal for performing a processing configuration necessary for the function is issued. Among the control signals issued by the configuration control unit 3, signals related to timing are transmitted to the memory control unit 10 via the signal transmission unit 4. The memory control unit 10 controls the processing target memory unit 100 that stores image data, the processing result memory unit 700, and the LM control unit 50 that controls the line memory (LM) 5.

Further, the configuration control section 3 sends the LM input data control circuit 200, the LM output control circuit 300, etc., based on the transmitted information on the image processing function and the bit width of the image data.
A control signal for controlling the input / output is transmitted through the transmission means 4. The LM input data control circuit 200 and the LM output data control circuit 300 control data input to and output from the LM 5 according to the control signal.

The image data output from the LM output data control circuit 300 is calculated by the processor unit (PU) 400 of the image processing unit 90 and input to the data integration circuit 500. Although the image processing unit 90 according to the present embodiment performs the filtering process, a circuit that performs a shape conversion process and a labeling process may be added to the data integration circuit 500.

The filtered processing result data is input to the data selection control circuit 600, the processing result data is selected by a control signal from the configuration control unit 3, and the data is output to the processing result memory unit 700. Further, in the data selection control circuit 600, when there is a feedback instruction from the control signal from the configuration control unit 3, the processing result data is fed back to the LM input data control circuit 200 via the feedback unit 800. In the pipeline processing configuration according to one embodiment of the present invention, the feedback processing result can be input to the LM 5 again to perform another filtering processing.

FIG. 3 shows a schematic configuration of an image processing apparatus for performing pipeline processing. In the present embodiment, the filter processing A
By returning the output result of 903 to LM5 again, different filter processing B904 is processed in a pipeline manner.
This pipeline processing configuration is shown in FIG.
Can be changed from That is, LM5 is shown in FIG.
It has the same 32-bit width as in (c). FIG.
Since the 5 × 5 filter processing 902 of (c) uses 25 multipliers and 24 adders, 9 × 2 multipliers and 8 × 2 adders are used from among them, and FIG. Filter processing 9
03,904. Alternatively, if the system shown in FIG. 2B has 18 multipliers and 16 adders, the processing configuration shown in FIG. 3 can be changed.

Next, each block in FIG. 1 will be described in detail. The configuration control unit 3 receives information related to image data and an instruction to execute an image processing function from the control device 1 via the bus 2.

FIG. 4 shows an example of a management table for image data information and image processing function information. These pieces of information are set from the control device 1 in a management table provided in a storage device (not shown) of the configuration control unit 3. FIG. 7A shows a screen management table, which includes an image memory channel number indicating a memory in which image data to be processed is stored, a physical address starting on an image screen to be processed, a screen size, and the like. Further, it stores image data information such as a bit width (w) of image data and a screen data type indicating an image type such as color or monochrome.

FIG. 3B shows an image processing function setting table, which stores processing contents such as filter processing, processing forms such as single processing, pipeline processing or parallel processing, the number of processings, processing size, and the like. FIG. 9C is a processing number management table for checking whether or not the processing function to be set is available. In the illustrated example, when the LM5 has a 32-bit width, the number of processing operations of the filter processing that can be configured by the image processing unit 90 is shown. Is shown. That is, the bit width (w) of the image data
And the processing size (kernel size of the filtering process) as a parameter, the number of filtering processes is set. For example, if the bit width of the image data is w = 8 and 3 ×
When performing three filterings, the number of possible processings is two, and two different filterings can be performed in a pipeline or two identical filterings can be performed in parallel.

FIG. 5 shows a processing flow of the configuration control unit 3.
The configuration control unit 3 generates signals for controlling each block, including input / output control of data to and from the LM 5, by setting image data information and setting image processing functions (s103). These control signals are issued based on the bit width (w) of the image data and the setting function, for example, as shown in FIG.

The table in FIG. 5B shows an example of control signals for each block of the 3 × 3 filter processing having a data width of 8 bits for the case of single processing, pipeline processing, and parallel processing.

A storage signal and a screen size of image data are set for the memory control unit 10 by a control signal from the configuration control unit 3. In the case of pipeline processing, as shown in FIG. 5B and FIGS. 6 and 7 described later, the LM input data control circuit 200 receives data from the processing target memory unit 100 and output data from the LM 5. And a control signal for generating input data of the LM 5 from the data of the image processing result. For the LM output data control circuit 300, the output (LM_out) 301 of the LM5 and the LM5 are set so that the PU 400 and the data integration circuit 500 realize the product-sum operation of the 3 × 3 filter processing according to the image processing function. Data (LM_t) directly input from the input data control circuit 200
(hr) 302, a control signal for generating block data to be distributed to each PU 400 is generated.

Next, for each PU 400, a control signal for setting a coefficient and selecting a function such as multiplication or addition is generated so that a product-sum operation or the like realizes a desired function. For the data integration circuit 500, for example, a control signal for performing the configuration of the circuit shown in FIG.
From the result of the calculation. These are performed basically in the same manner as in the prior art.

The data selection control circuit 600 selects a 3 × 3 filter processing result stored in the processing result memory unit 700 and generates a signal for selecting image data to be fed back to realize pipeline processing.

After all the control signals have been generated, the configuration control unit 3 sends a start signal for starting image processing to the memory control unit 1.
It occurs at 0 (s104). The memory control unit 10 generates an address for accessing each memory, which is a storage unit of image data, and a timing signal based on the start signal.

As described above, in the case of the pipeline processing configuration of FIG. 3, the configuration control unit 3 theoretically divides the 32-bit width LM5 into LM0 to LM3 every 8 bits, and inputs the LM5 corresponding to each divided LM. Enable data capture.
Also, two sets of 3 × 3 filter processing are performed according to the image processing function to be used. In the present embodiment, the 3 × 3 filter processing has been described, but a 5 × 5 filter processing configuration may be employed. That is, the configuration of the product-sum operation can be changed according to the filter size so that the filter size can be freely selected.

FIG. 8 shows a configuration for realizing two different 3 × 3 filter processes, and FIG. 9 shows a configuration for realizing 5 × 5 filter processes. In the product-sum operation in the filter processing, the multiplication is performed by the PU 400, and the addition is performed by the data integration circuit 500.
It is done in. The control of the filter size is realized by controlling the data flow in the data integration circuit 500. The data flow is controlled by selectors 510 to 550, and desired filter processing is realized by combining adders according to the filter size. Therefore, the change of the configuration of FIG. 8 and FIG.
550 makes this possible by controlling the flow of data.

In the present embodiment, the configuration control unit 3 performs all controls relating to the processing configuration and image processing. However, other alternatives to the present embodiment are possible, for example, the control device 1 performs the same function, or a part of the function performed by the configuration control unit 3 is replaced by another block.

Next, the input / output control of the LM 5 will be described with reference to FIG.
This will be described in detail with reference to FIG. 7 and FIGS. First, the LM input data control circuit 200, LM
5 and the relationship between the LM output data control circuit 300 will be described. In the figure, data 201 having a bit width of 8 bits input from the memory unit 100 to be processed is M [7: 0], and the data selection control circuit 600 sends feedback data 800
FB [7: 0], 32
The data 210 to be input to the bit width LM5 is represented by LM_in [3
1: 0], data 301 (202) output from LM5
Is described as LM_out [31: 0], and the data 302 input from the LM input data control circuit 200 to the LM output data control circuit 300 without passing through the LM5 is described as LM_thr [15: 0].
The code of each data may be replaced with the code of the corresponding signal line.

First, the LM input data control circuit 200 and L
An outline of the function of the M output data control circuit 300 will be described.
In the LM input data control circuit 200, M [7:
0], FB [7: 0], input data LM_in [31: 0] to LM5 from LM_out [31: 0], and input data LM_thr [15: 0] to the LM output data control circuit 300. At this time, LM_in [31: 0] and LM_thr [15: 0] are controlled according to the bit width of the image data, and the bit width is 8
In the case of bits, as shown in FIG. 9, a signal line is used by separating every eight bits.

FIG. 10 shows the relationship between the theoretical separation configuration of the LM5 and the bit width of the input data. If the bit width of the image data is 16 bits as shown in FIG. 2A, the processing configuration is as shown in FIG. 2B, so that LM_in [15:
0], LM_in [31:16] is input to LM1. As shown in FIG. 3B, the bit width of the image data is 8 bits,
When the processing configuration of FIG. 3 is adopted, M [7: 0] and LM
1 is input to LM_out [7: 0], FB2 is input to LM2, and LM_out [23:16] is input to LM3.

Next, in the LM output data control circuit 300, data necessary for the filtering process is selectively controlled from LM_out [31: 0] and LM_thr [15: 0], and output to the PU 400. Here, the data flow when the 3 × 3 filter processing A and B are pipelined will be described in detail.

FIG. 7 shows the configuration of the LM output data control circuit 300. The LM output data control circuit 300 receives the image data LM_out delayed by one or two lines in the vertical direction from the signal line 301 and the image data LM_thr without the vertical delay from the signal line 302, respectively. In the figure, the numbers attached to the oblique lines on the signal lines represent the number of each signal line, and correspond to the number of transmitted bits.

Inside the LM output data control circuit 300, a horizontal delay circuit (flip-flop) 311,
Using 312, data delayed by two stages in the horizontal direction is generated, and block data necessary for 3 × 3 filter processing, that is, a combination of nine image data corresponding to a 3 × 3 area on the screen is created, Filter processing A is distributed to each of the PUs 400. Similarly, the delay circuit 313 and the delay circuit 313 for the filter processing B using the processing result of the filter processing A
314 is used to create block data. The output data is divided into the processing A and the processing B by the output data bit separation circuit 315.

FIG. 20 shows a configuration of an LM output data control circuit 300 according to another embodiment. Horizontal delay circuit 3
By setting each of 11 to 314 and 321 to 324 to four stages, it is possible to apply to both 3 × 3 and 5 × 5 filter processing. Specifically, output data is generated according to the processing size (kernel size) specified in the output data bit circuit.

FIG. 11 shows the relationship between the data arrays of the filtering processes A and B. This example shows the relationship when there is no delay in the product-sum operation, and the filter A in the figure shows the operation of the filter processing at the position of Am, n. Here, the subscript m indicates the x coordinate of the image, and n indicates the y coordinate. Nine pieces of data used for the processing are put together into one set by the LM output data control circuit 300, and are input to the PU 400 and the data integration circuit 500, which are circuits that perform a product-sum operation at the same time.

Next, a description will be given of a mechanism for performing pipeline processing of a different filter processing B on the processing result of the filter processing A. The processing result of Am, n in the filter processing A is transmitted to the LM input data control circuit 200 via the feedback means 800 and used for the filter processing B. At this time, the processing result of Am, n is Bm, n.
At this time, the output result of the filter processing B is a position delayed by one line and one pixel from the processing result of the filter processing A because the processing result of the filter processing A is processed. That is, the filter processing A outputs the result at the pixel of (m, n) in absolute coordinates, and at this time, the filter processing B outputs (m
-1, n-1) is output.

To summarize the above, in the filtering process A,
While the filter processing is performed on the data from the processing target memory unit 100, the filter processing B performs the filter processing on the processing result of the filter processing A in a pipeline manner. At this time, the difference between the configuration of the filter processing A and the configuration of the filter processing B is as follows.
0 or filter processing A
Is performed on the data resulting from the above processing, and is not different from the processing configuration in the case of individual filter processing.

The data control for realizing the pipeline processing of the filter processings A and B shown in FIG. 11 will be described in further detail. The purpose of the data control here is to simultaneously execute the three data indicated by hatching in FIG.
And LM_thr to control the timing of the data flow so that the data can be generated from the two data. Simultaneous generation of the above-mentioned hatched portions means that L
This means that data of the above-mentioned hatched portions is generated in M_out and LM_thr.

FIG. 12 shows the bit configuration of the data in the hatched portion in FIG. In the drawing, LM_in, LM_thr, LM_out
The data to be separated from is shown in the upper row for each bit width,
The data array in the filtering processes A and B corresponding to the data is shown in the lower part.

The bit separation control is performed by LM_i
For n, the LM input data generation circuit 25 in FIG.
0, the LM pass data generation circuit 25 for LM_thr
1 is performed. Regarding LM_out, the data read from LM5 already has the bit configuration shown in FIG.

FIG. 13 shows a timing chart of the filtering processes A and B. (A) shows the case where there is no delay in the operation in the filter processing. RA indicates the read address of the LM5 and WA indicates the write address. L in this example
M5 uses a synchronous memory having a bit width of 32 bits and a processing target bit width of 8 bits and outputting data of an address designated by RA after one clock.

At this time, control is performed so that the lower 16 bits of LM5 are used for filter processing A and the upper 16 bits are used for filter processing B. That is, LM5 and signal line 2
The filters 10 and 302 are controlled by the filtering processes A and B so that they can be used after being divided into two according to the bit width of the image data.

Next, the relationship between the operation of the LM 5 and the filter processing A and the filter processing B will be described more specifically with reference to FIGS. FIG. 14 is a conceptual diagram for explaining the data array on the image screen to be processed and the data array of LM5. The LM5 uses a synchronous memory that outputs the data at the address specified by RA one clock after. The image data used in the filter A is indicated by a circle, and the image data used in the filter B is indicated by a double circle. As shown, RA (=
8), when WA (= 7) is instructed, filter processing A performs processing of data 68 using nine image data in a rectangle, and filter processing B similarly results data 57 of processing A (image data 57 Corresponding). The following description focuses on the filter processing indicated by a rectangle.

FIG. 15 shows the LM as shown in (a) to (c).
5 is an explanatory diagram in which the operation of FIG. 5 is monitored for three clock periods. Hereinafter, the data used in the filter A is distinguished by adding a suffix a, and the data used in the filter B is distinguished by adding a suffix b.

In the state shown in FIG. 7A, WA = 5 and RA =
6 is shown. Image data 59 from image memory 100
When a is input, the LM 5 is controlled to output image data 57a and 58a in synchronization with the input. At this time, filter processing A is performed at 37a, 38a, 39a, 47
Filter processing is performed using the image data of a, 48a, 49a, 57a, 58a, and 59a, and the processing result is data 48b. The data 48b is used as an input to the LM5 and at the same time as the filter processing B. The filter processing B includes the result data 26b, 27b,
28b, 36b, 37b, 38b, 46b, 47b, 4
Using 8b, the processing result at the 37 positions is output.

Next, in the state shown in FIG. 7B after one clock, WA = 6 and RA = 7, and the output from LM5 becomes 1
Data 56b, 57 of the address specified before the clock
b, 67a and 68a. At this time, the image memory 10
Image data input from 0 is 69a, filter processing A
Is 58b. The processing result data of the filter processing B is data at the position of 47. Further, in the state of FIG.
7, RA = 8, and the output from LM5 is data 66
b, 67b, 77a, 78a. The processing result data of the filtering process A is 68b, and the processing result data of the filtering process B is data at the position 57.

As described above, each clock WA is adjusted according to the bit width of the image data input from the image memory 100.
And RA are counted up. Then, in synchronization with the image data read from the image memory 100, 3 × 3
The LM 5 is controlled so that the filter processing can be executed.

The above-described operation of the LM5 is for the two-stage pipeline processing. However, for the individual filter processing A or filter processing B, ordinary 3 × 3 filter processing or 5 × 5 filter processing is performed. Operation is the same as

Although the present embodiment does not consider the number of delay stages of the operation in the filter processing, the number of delay stages may be considered. When the number of delay stages is considered, FIG.
As shown in (1), the control method is exactly the same as in the case where there is no delay, except that the difference between the data combination of the filter processing A and the data of the filter processing B in LM_in and LM_thr is only one clock.

As described above, according to the present embodiment, the input / output of the line memory can be easily controlled by a combination of data, so that filter processing with different filter sizes, and further, pipeline processing and parallel processing can be performed in common. The processing can be efficiently realized by changing the processing configuration using hardware (resources). Hereinafter, another embodiment having a different processing mode will be described.

FIG. 16 shows the bit configuration of the data input to the 3 × 3 filter processing 901 in the processing configuration of FIG. 2B in which the bit width of the image data is 16 bits. As in the case of FIG. 12, LM_in, LM_thr, and LM_out show the data to be controlled in the upper row and the target data in the filter processing A901 corresponding to the data are shown in the lower row.
As in the previous example, these bits are separated by LM
_in, the LM input data generation circuit 250
The LM pass data generation circuit 251 performs thr. Regarding LM_out, the data read from LM5 has the bit configuration already shown in FIG.

FIG. 17 shows a processing configuration in which the bit width of image data is 1 bit and 16 stages of A to P pipeline processing are performed. Also in this case, LM5 is set to LM with 1-bit width.
L divided into 0 to LM31 and input to each 3 × 3 filter
This can be similarly realized by controlling the data of M_in, LM_thr, and LM_out to be separated by 1 bit width from the 8 bit width in FIG.

As described above, the input / output of the LM is controlled in accordance with the bit width of the image data, and the number of LMs to be used is substantially optimized, whereby a plurality of stages of pipeline processing can be performed. Has been realized.

FIG. 18 shows the configuration of an image processing apparatus using parallel processing according to the present invention. As shown in the figure, the configuration is the same as that of the embodiment of FIG. 1 except that n processing target memory units 100 and n processing result memory units 700 are used.

FIG. 19 shows a processing configuration of two parallel processes. The processing configuration when parallel processing is performed on two 3 × 3 filter processes A using an LM having a 32-bit width and a bit width of image data of 8 bits is shown. When one screen is divided into two and processed in parallel as shown in FIG.
The processing time for performing the filter processing A can be reduced by half.

This processing configuration can be easily changed from the processing configuration of the pipeline in FIG. For example, in the LM input data control circuit 200, the feedback unit 800
It is only necessary to change the processing result data transmitted from the processing target data to image data from the processing target memory unit 100. Therefore, an arbitrary configuration is possible such that the processing configuration of FIG. 3 is employed when pipeline processing is required, and the processing configuration of FIG. 14 is employed when parallel processing is required. Of course, a change from the processing configuration of FIG. 2C is also possible.

[0067]

According to the present invention, the bit width of the line memory for one line is changed in accordance with the bit width of the image data to be handled, thereby changing the theoretical number of line memories.
The processing configuration corresponding to the bit width of the image data and the setting function of the image processing can be flexibly changed within the range of the scale of the line memory or the arithmetic unit.

Further, according to the present invention, by controlling the input / output of the line memory in accordance with the bit width of the image data to be handled and the image processing size, it is possible to freely perform a plurality of stages of pipeline processing and a plurality of sets of parallel processing. This makes it possible to increase the speed of image processing.

That is, according to the present invention, various processing configurations can be adopted in accordance with the bit width of the image data to be handled and the image processing setting function. Equipment can be provided.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of an image processing apparatus according to an embodiment of the present invention.

FIG. 2 is a conceptual diagram showing various processing configurations of an image processing apparatus using a line memory.

FIG. 3 is a conceptual diagram showing a processing configuration of an image processing apparatus for pipeline processing according to the present invention.

FIG. 4 is a table showing setting contents of image information and image processing function information.

FIG. 5 is an explanatory diagram showing a flow of processing by a configuration control unit and an example of a control signal to be issued;

FIG. 6 is a functional block diagram showing a configuration of an LM input data control circuit for controlling input data of a line memory and its peripheral circuits.

FIG. 7 is a functional block diagram showing a configuration of an LM output data control circuit.

FIG. 8 is a functional block diagram illustrating a circuit configuration of an image processing unit that implements 3 × 3 filter processing.

FIG. 9 is a functional block diagram illustrating a circuit configuration of an image processing unit that implements 5 × 5 filter processing.

FIG. 10 is a conceptual diagram showing a theoretical division configuration of a line memory.

FIG. 11 is an explanatory diagram showing transition of block data for realizing pipeline processing of 3 × 3 filter processing.

FIG. 12 corresponds to a shaded portion in FIG.
FIG. 4 is a data configuration diagram showing LM passing data and LM output data for each bit width.

FIG. 13 is a timing chart of the block data of FIG. 11;

FIG. 14 is an explanatory diagram showing block data and the positions of line memories in the pipeline processing of the 3 × 3 filter processing.

FIG. 15 is an explanatory diagram showing data movement of a line memory in detail.

FIG. 16 shows another embodiment of the present invention, wherein the image data is 15
FIG. 4 is a data configuration diagram showing LM input data, LM passing data, and LM output data for each bit width in the case of a bit width.

FIG. 17 is a conceptual diagram of a processing configuration for performing a 3 × 3 filter process in a 16-stage pipeline process when image data has a 1-bit width in another embodiment of the present invention.

FIG. 18 is an overall configuration diagram of an image processing apparatus that performs n sets of parallel processing according to another embodiment of the present invention.

FIG. 19 is an explanatory diagram of a processing configuration for performing two parallel processing of 3 × 3 filter processing and a target memory.

FIG. 20 is a functional block diagram showing a configuration of an LM output data control circuit according to another embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Control device, 2 ... Bus interface between a control device and an image processing device, 3 ... Configuration control part, 5 ... Line memory (L
M), 90: image processing unit, 100: memory unit to be processed,
200 LM input data control circuit, 250 LM input data generation circuit, 300 LM output data control circuit, 31
1 to 314: delay circuit, 321 to 324: delay circuit, 3
30 ... output data bit separation circuit, 400 ... PU,
500: Data integration circuit, 600: Data selection control circuit, 700: Processing result memory unit.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H04N 1/40 G06F 15/66 J 5/14 H04N 1/40 Z (72) Inventor Shigeru Naoi 5-chome Omikacho, Hitachi City, Ibaraki Prefecture No. 2 in Hitachi, Ltd. Omika Plant (72) Inventor Takahito Kanada 5-2-1, Omika-cho, Hitachi City, Ibaraki Prefecture In Hitachi Omika Plant

Claims (10)

[Claims] An image processing apparatus for inputting image data to be processed to an image processing circuit using a line memory having a line width of a plurality of bits, wherein the line width of the line memory is adjusted in accordance with the bit width of the image data. In theory, a plurality of divided line memories are configured in accordance with the set image processing function information (hereinafter referred to as a setting function). An image processing device comprising a configuration for controlling input and output. 2. The image processing circuit according to claim 1, further comprising a configuration for controlling a combination of a plurality of arithmetic circuits in the image processing circuit according to the setting function, wherein a processing size such as 3 × 3 or 5 × 5 is changed and / or Alternatively, an image processing apparatus capable of changing a processing mode such as a pipeline or parallel processing. 3. An image memory for storing image data to be processed, an image processing circuit for performing predetermined image processing, and the image processing circuit for converting image data read from the image memory into block data corresponding to a processing size. In the image processing apparatus having a line memory for outputting the line width of the line memory according to the bit width of the image data, theoretically, a plurality of divided line memories are configured, and the number of lines used according to the setting function Configuration control means for controlling the input / output of the divided line memory so as to correspond to the image processing circuit; line memory input data control means for generating input data to be input to the line memory; A line memory output data control means for generating the block data from the data to be output; An image processing apparatus wherein a processing configuration can be arbitrarily changed within a range of an in-memory line width. 4. The apparatus according to claim 3, wherein, in the P-stage pipeline processing by i × i filter processing having different setting functions, the number L used is (i−i).
1) In the case of xP, the configuration control means sets the divided line memory used for each stage of the pipeline processing to an L / P line group, and reads the divided line memory from the image memory to the first stage image processing circuit. A line group including a divided line memory for directly inputting image data, and a line group including a divided line memory for inputting processing data of a previous stage are sequentially associated with the image processing circuits of the next and subsequent stages. An image processing apparatus for controlling input / output of a line memory. 5. The image processing circuit according to claim 4, wherein said line memory input data control means includes: image data read from said image memory; a part of output data of said line memory; An image processing apparatus for generating, from data, input data to be input to all of the divided line memories. 6. The configuration control unit according to claim 3, wherein the setting function is a parallel processing of Q sets by the same i × i filter processing, and the number L used is (i−1) × Q. The divided line memory used for each set of parallel processing is an L / Q line group, and one screen of the image data stored in the image memory is divided into Q in the vertical direction, and the image data is divided in parallel from each area. An image processing apparatus that controls reading image data to be input to a corresponding line group. 7. The configuration control unit according to claim 4, wherein the configuration control unit includes a filter size (i × i) indicating the setting function, a processing number (1 or P or Q), a pipeline, and the like. When the processing mode is set, control is performed so that the image processing circuits for the number of processes are configured by arithmetic circuits corresponding to the filter size.When the processing mode is a pipeline, the image processing circuits of the image processing circuits are controlled. An image processing apparatus, wherein each processing result data is controlled so as to be fed back to the line memory input data control means. 8. An image memory for storing image data to be processed, an image processing circuit for performing predetermined image processing, and the image processing circuit for converting image data read from the image memory into block data corresponding to a processing size. An image processing apparatus having a line memory for outputting to a P memory, a P set of image processing circuits for performing P-stage pipeline processing by different i × i filter processing, and a line memory of the line memory according to a bit width of the image data. L (= (i-1) × P)
Configuration control for configuring input / output of the line memory by configuring the divided line memories and making the divided line memories used according to the setting function correspond to each image processing circuit for each of the L / P line groups Means, image data read from the image memory, part of output data of the line memory, and processing result data of each stage of the image processing circuit, all lines obtained by theoretically dividing the line memory A line memory input data control means for generating input data for input to the line memory; and a line memory output data control means for generating the block data from data output from the line memory, within a line width of the line memory. An image processing apparatus wherein a pipeline processing configuration can be arbitrarily changed. 9. The image processing device according to claim 8, wherein when i = 3 and P = 2, the line memory input data control means reads the M bits of the width of the image data read from the image memory and reads the data one clock before. M bits obtained from the output data in the output image data correspond to 2 bits corresponding to the preceding image processing circuit.
At this time, the M bits of the processing result data of the preceding image processing circuit and the M bits of the processing result data one clock before the two lines corresponding to the subsequent image processing circuit are added to the line group including the divided memories. The line memory output data control means controls the image data read from the image memory and the two image data output from the preceding line group on three lines on the screen. A data set and a data set one clock before and two clocks before the data set are combined to generate nine data blocks, which are sent to the preceding image processing circuit from the processing result data of the preceding stage and the line group of the following stage at this time. Output the processing result data of 2,
An image processing apparatus, wherein control is performed in the same manner as in the previous stage to generate a data block and output to a subsequent image processing circuit. 10. An image processing apparatus comprising: an image memory for storing image data to be processed; a line memory having a line width of 32 bits; and an image processing circuit having a plurality of product-sum operation circuits capable of executing at least 5 × 5 filter processing. In the image processing apparatus, the line width of the line memory is cut in accordance with the bit width of image data.Theoretically, a plurality of divided line memories are configured, and the number of divided line memories used according to a setting function is determined by the image processing apparatus. To correspond to the processing circuit,
A configuration for controlling the input / output is provided. When the image data has a 16-bit width, the line memory is divided into 16-bit widths to construct a processing configuration of a 3 × 3 filter. In any case of an 8-bit width, the line memory is divided into corresponding widths of 1 to 8 bits to construct a processing configuration of a 5 × 5 filter or a 3 × 3 filter. In the case of any of 8-bit widths and the processing mode is a multi-stage pipeline processing, the line memory is divided into corresponding widths of 1 to 8 bits,
A processing configuration in which each stage of the pipeline processing by the 3 × 3 filter processing is input / output by a divided line memory is constructed, or the image data is any one of 1 to 8 bits wide and the processing form is a plurality of sets. In the case of parallel processing, a process in which the line memory is divided into corresponding widths of 1 to 8 bits, and each set of parallel processing by 3 × 3 filter processing is associated with a divided line memory of the parallel readout area of the image memory. An image processing apparatus having a configuration.