JPH10335615A - Improvement of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which is lessened in substrate loss in a high frequency band which contains multi-gigahertz frequencies and in cross talk. SOLUTION: A semiconductor device is formed of a bonded wafer 10 equipped with a silicon device layer bonded to a semi-insulating layer 14 made of mobility-deteriorated crystalline silicon, for instance, polycrystalline silicon. When a device located inside a layer 20 operates at frequencies above 0.1 GHz, the semi-insulating layer 14 is made thick enough to be lessened in resistance loss, and a substrate 18 is made high enough in conductivity. The substrate 18 is high enough in conductivity to protect devices located in the layer 20 against cross talk between them, and the semi-insulating layer 14 is high enough in resistivity.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, it relates to a semi-insulating wafer.

[0002]

2. Description of the Related Art Integrated circuits operating at microwave frequencies comprise monocrystalline gallium arsenide or are mounted on substrates utilizing hybrid circuit techniques. Attempts to implement microwave frequency integrated circuits with conventional silicon technology have been limited due to the high losses that occur in silicon substrates at gigahertz frequencies. Although gallium arsenide and hybrid circuit technology are effective in producing integrated circuits operating at microwave frequencies, they still have several disadvantages. Both of these technologies are expensive and generally result in circuits of lower device density compared to the cost and device density in planar silicon integrated circuits. Although highly resistive float zone method substrates are now being applied in this multi-gigahertz range, these types of substrates are very expensive and the wafer diameter is limited to 100 mm. . Silicon dioxide is an excellent insulator, but has a relatively low thermal conductivity.

[0003]

SUMMARY OF THE INVENTION The present invention relates to semiconductor devices, particularly semi-insulating wafers, and comprises a substrate structure that enables all of the following desirable characteristics, the characteristics being (1): Bonded wafer SOI
High quality device silicon by the technique, (2) good thermal conductivity by silicon-based substrate, (3) good electrical insulation by the bonded wafer SOI technique, (4) low RF loss by using a semi-insulating layer under the device Characteristics, (5)
Low crosstalk due to the use of a conductive region below the semi-insulating region, and (6) unrestricted wafer diameter because a standard silicon wafer forms the starting substrate.

The present invention further provides a bonded wafer and conductive substructure with a semi-insulating layer that reduces substrate loss and crosstalk at high frequencies, including multi-gigahertz frequencies. The bonded wafer has a handle substrate, preferably made of single crystal silicon. The semi-insulating layer is disposed above the handle substrate. The semi-insulating layer is preferably polycrystalline silicon, amorphous silicon, or other forms of silicon, including oxygen-doped silicon and porous silicon, having relatively high thermal conductivity.

[0005] Combining this semi-insulating layer with a base conductive layer results in both reduced substrate loss and reduced crosstalk between circuit elements. In one embodiment of the invention, the semi-insulating layer is as thick as the device width in the device layer, or less than the device width in the device layer. In addition, the semi-insulating layer should be practical and somewhat resistive, and the substrate should be practical and somewhat conductive. A semi-insulating layer and a barrier layer between the substrates may be required. The barrier layer may be a single layer of epitaxial undoped silicon or metal or silicide, or a multilayer of these materials, which may further enhance the RF performance of the resulting structure. . This barrier layer prevents the dopant in the handle substrate from diffusing into the semi-insulating layer of silicon and thus retains its semi-insulating properties.

The present invention includes a semiconductor device comprising a semi-insulating layer with a bonded wafer for reducing loss and crosstalk at high frequencies, the device comprising a handle substrate, a semi-insulating layer over the handle wafer, an insulating layer. And a device layer of single crystal silicon covering the insulating layer, wherein the semi-insulating layer has a predetermined thickness.

The present invention will be described by way of specific examples with reference to the accompanying drawings. FIG. 1 shows a bonded wafer 10 that includes active devices 22, 2 in a device layer 20.
4 to dramatically reduce substrate losses while maintaining good heat transfer. This bonded wafer 10
It has a handle substrate 16 preferably made of single crystal silicon. Deposited on handle wafer 16 is a layer 14 of semi-insulating material. This semi-insulating material is polycrystalline silicon, amorphous silicon, semi-insulating polysilicon
(SIPOS) or completely insulated silicon using FIPOS. The semi-insulating material of layer 14 is any mobility degraded crystalline silicon
Or any other suitable electrical insulator with high thermal conductivity, such as diamond. Semi-insulating layer 14
Are bonded to an insulating layer 18 deposited on a device layer 20. Insulating layer 18 is typically an oxide. The bond can be formed by known methods, for example, those shown in U.S. Patent Nos. 5,266,135 and 5,334,273, assigned to Harris Corporation. The device layer 20 includes a plurality of semiconductor devices, including diodes and transistors, which are integrated in a circuit. Representative field effect transistors 22 and bipolar transistors 24 are shown in FIG.

FIG. 1 is about 600 microns thick and has a resistivity of 1
Shown is a handle wafer 16 having 0-20 ohm-cm. Polysilicon semi-insulating layer 14 is approximately 50 microns thick. Isolation oxide layer 18 is about 2 microns thick and device silicon layer 20 is about 10 microns thick. The silicon layer 20 including the insulating layer 18 is bonded to the handle wafer 12, and the silicon layer 20 may be significantly thicker than 10 microns, for example, 500-7.
00 microns. After bonding, the device wafer 20 is thinned using various techniques including etching, lapping or polishing.

At multiple gigahertz high frequency operation, bonded wafer 10 experiences substantially less loss than any standard silicon device or standard bonded wafer would experience. Semi-insulating layer 14 is more thermally conductive than silicon dioxide. Substrate layer 16 is sufficiently conductive to reduce crosstalk between devices 22,24.

FIG. 2 illustrates a second embodiment of the present invention, wherein like reference numerals identify like elements. Bonded wafer 30 includes barrier layer 1 disposed between substrate 16 and semi-insulating layer 14.
Five. Barrier layer 30 is about 1.5 microns thick and comprises an epitaxial layer of undoped silicon. The barrier layer 15 is formed on a single crystal substrate 16 in an epitaxial reactor well known in the art.
Grow on. The handle wafer 16 contains the devices 22, 2
Very heavily doped to reduce cross talk between the four. Handle wafer 16 has a thickness of about 600 microns. Semi-insulating layer 30 has a thickness of about 30 microns. Insulating layer 18 and device layer 20
Have the same thickness as shown in FIG. The semi-insulating layer 14 of FIG. 2 has been reduced in thickness to provide a highly conductive handle substrate layer 16 that more closely resembles the devices 22,24. By effectively moving the highly conductive substrate layer 16 closer to the devices 22, 24, crosstalk between the devices 22, 24 is reduced. However, substrate losses may increase slightly.

The present invention provides a mechanism for optimizing substrate losses and device crosstalk not possible with prior art devices. One of the features of the present invention is that the thickness of the semi-insulating layer 14 has a predetermined thickness and can be used to balance the gain in reduced ohmic loss with the gain in reduced crosstalk. It is our discovery. Thus, as layer 14 is reduced in thickness, resistive losses will increase, while crosstalk will decrease due to the shielding effect of highly conductive layer 16. As this highly conductive layer 16 moves closer to the devices 22,24, crosstalk decreases. An overly thick layer 14 results in increased crosstalk, whereas an overly thin layer 14 results in high ohmic losses. Layer 14 should be sufficiently thick and layer 16 be sufficiently conductive to balance between reduced ohmic losses and reduced crosstalk. This balance generally results in a particular operating frequency of the device 22,24.

FIGS. 3-12 disclose a very complex problem that allows minimization of substrate parasitics, including crosstalk and resistive substrate losses. The amount of current induced in the substrate depends, for example, on the metal line layout (metal line plac
ement). In order to establish a probable estimate of their magnitude, the following analysis will focus on the key factors affecting loss. This provides a set of guidelines for optimizing the substrate doping profile and substrate depth. The following description also provides worst-case estimates for substrate ohmic losses in the simple case of very long, straight metal lines. To determine the estimation and understanding of crosstalk, the capacitance was determined using a two-dimensional finite difference device simulator.
It is calculated for a representative case of a number of neighboring devices (D1, D2, D3).

FIG. 3 shows a very long straight metal conductor 6.
2, which extends across the various layers of the bonded wafer 50. Bonded wafer 50 has a handle substrate 52 typically made of single crystal silicon. Bond oxide layer 54 connects substrate 52 to device wafer 56. The device wafer 56 includes a number of devices (not shown), which are connected by metal lines. Line 62 represents a cross-sectional view of one metal line passing between two or more devices. Metal line 62 is electrically isolated from devices in layer 56 by oxide layer 58. Metal line 62
Is also covered by another insulating layer 60 which can be an oxide or nitride layer.

In almost all practical cases, the conductivity in device layer 56 for these long distances can be neglected. That is because it is thin when compared to its skin depth for the most typical doping levels, and because the highly doped regions are limited to isolated regions that are too small to allow significant conductivity. .
This allows simplification of the geometry of the wafer 50 to the extent shown in FIG. Thus, the wafer 50 'is
And a semi-insulating layer 64. Layer 64 includes a device layer 56 that is silicon, but is sufficiently “semi-insulating”.

Assuming that the resistivity in layer 52 is sufficiently low, the skin depth will be much smaller than the substrate thickness. It is known that for distances above a few skin depths below the substrate-insulator interface, both electric and magnetic fields due to AC current are essentially zero. Thus, the overall effect of the induced electric field is that it is equal in direction and magnitude, and that the conductor 62
Generate a current that is opposite to the phase of the AC current at. This is simply the return current at the ground plane. As shown, at microwave frequencies, these induced resistive losses can be greater than those in metal conductor 62.

A rough and quick estimate of the dielectric substrate resistance can be derived. For the wafer 52 'of FIG. 4, assume that the entire structure is cylindrically symmetrical about an axis centered on the metal conductor 62. Attempts to validate this approximation will be made later. The solution of Maxwell's equation for this electric field is

[0017]

(Equation 1)

Or

[0019]

(Equation 2) Where δ is the skin depth and j = -1-1.

[0020]

(Equation 3)

EZ is the component of the electric field E in the axial direction, ω is the angular frequency, μ is the magnetic permeability, ρ is the resistivity of the substrate, and γ is the distance to the center of the metal line. is there. The solution to Equation 2 is the Bessel function of the complex argument. The exact combination of these Bessel functions was determined by applying the boundary condition that the electric and transient fields are zero at large r. The latter was done by forcing the concentrated electric field (or current density) to be equal in magnitude and opposite in phase to the current of the metal line. From this solution,
Integration of EE * / ρ to perform resistance power loss on the substrate
(resistive power loss). Since the current is fixed at a low resistivity, this power loss is proportional to the substrate resistance. In fact, the substrate resistance R can be defined by this relationship. Some results showing substrate resistance versus substrate resistivity are shown in FIG. 5 (frequency = 109 Hz) and FIG.
10 Hz). More enlightening, however, is to compare these numerical results with simple analytical formulas. This equation simply uses the resistivity,
Then, it is divided as follows by the area determined by the skin depth.

[0022]

(Equation 4) Where l is the length of the metal line and d is the distance from the metal line to the top interface of the substrate. The denominator in (4) is the region of the δ-wide strip at the top of the substrate. The result of this equation compared to the exact result of FIG. 7 tends to be overestimated R, but does not exceed a factor of 1.27. As expected, this formula approaches numerical results if the substrate distance is large compared to the skin depth and the physical properties become more locally planar. From Equation 4, for d≪δ, it shows that R is proportional to frequency and independent of resistivity. For d≫δ, a better known relationship is obtained, ie, R is proportional to the square root of both frequency and resistivity.

Qualitatively, all these results will still exist with respect to actual plane geometry. The main difference is that the available area for conduction is reduced. According to rough guesswork, this increases R by a factor of three. One skilled in the art will appreciate that the complete numerical solution of Maxwell's equations can yield a more accurate equation similar to Equation 4 to model planar geometry.

When minimizing R using Equation 4, it is desirable to increase d relative to δ and to reduce the resistivity of substrate 52 as much as possible. Typically, this has never been done. This is because the substrate distance is about 10 μm or less. At very high frequencies where this particular parasitic is a predominant requirement, the skin depth is too large compared to the substrate thickness, often making the substrate highly resistive, so that essentially no current flows through the substrate. Absent. In this case, silicon 56 can be considered as an insulator,
The distance to the substrate d can be replaced by the distance to the metal on which silicon is present. However, often there are other important parasites to consider.

The substrate also acts as a parasitic capacitor that couples to the immediate device. Referring to FIG. 8, a structure 80 is shown that includes three devices D1, D2, D3, each having a total length of 46 microns, 46 microns, and 280 microns. This structure 80 has a handle substrate 85. Above the handle substrate 85 is a semi-insulating layer 84. Semi-insulating layer 84 is typically polysilicon. Bond layer 83
Bonds the semi-insulating layer 84 to the device wafer 88. An idealized single metal contact 89 separated by an oxide is added to contact each device. These devices are laterally isolated from one another by trenches having oxidized sidewalls 86 filled with a suitable material 87, for example polysilicon. The oxide layer 81 covers the metal layer 82.

The result from the numerical device simulation is:
Capacitance matrix for frequency に 対 す る CD
This is shown in FIG. 9 by plotting the elements from 1, D2 + CD1, D3 + CD1, Sub}.
The substrate doping in this case is 1015 cm-3.
Most of the field lines starting at D1 will converge below the top of the substrate while most of the rest will move directly to D2. At low frequencies, all of this substrate charge can be provided by the substrate contacts. This is because the RC constant is smaller than the charging time. However, as the frequency increases, this path is locked out. This is because the charging time becomes smaller than RC. When this occurs, the lower resistive coupling from the immediate device is now complete to provide this charge. 10
At an intermediate frequency of 9 Hz, the capacitive coupling CD1, D3 is actually larger than CD1, D2. This is because D3 (meaning indicating the immediate collection of devices) has a much larger surface exposed to the substrate than D2. However, as the frequency is further increased, CD1 and D3 drop to almost zero, while CD1 and D2 dominate. This is because it has a much lower path resistance.

FIGS. 9 and 10 show CD1, D2 and C
D1 and D3, respectively, each showing uniform substrate doping {1011, 1013, 1015, 1017,
The range is 1019 cm-3. In general, the trend is the same but shifts towards higher frequencies for more highly doped substrates. At low frequencies, CD1, D2 are dominated by direct dielectric capacitance from the field above the substrate. At higher frequencies-at the peak of Fig. 9 (when the substrate coupling is locked out)-an additional conductive path below the oxide allows additional coupling between D1 and D2. Even at higher frequencies, this conductive path is also locked out-leaving the dielectric coupling in place, including fringing through the shielded substrate at lower frequencies. From FIG.
It is clear that these same effects are present in the second closest neighbor, but differ greatly in magnitude. At frequencies above and below the peak, CD1 and D3 drop to approximately zero.

The above analysis is repeated for the same device, but for a substrate divided into two compartments. The upper section SU of the substrate has a higher resistivity than the lower section SL. In this example, SU is 30 μm thick;
And that is $ 1011, 1013, 1015, 101
SL is usually as high as possible while doped at 7 cm-3, which is 1020 cm-3 in the present example.
Is doped.

The importance of attention is in the order described here. Because the device simulator does not simulate all Maxwell's equations, skin effects on substrate resistance are not automatically addressed. If the skin depth is much smaller than the thickness of the substrate, the skin effect will be very large. To illustrate this, the SL doping was scaled so that its total resistance for each frequency was approximately the same so as to include the skin effect.
At 10 GHz, the doping used to simulate 1020 cm-3 is actually 1018 cm-3.
-3. With elimination, this change resulted in a significant difference in these curves only for the upper substrate doping case of 1017 cm-3 (and above) and only at frequencies above 1010 Hz.

FIG. 12 shows CD1, D2 and CD1, D3 for these dual substrate devices. C
The peaks at D1 and D3 are reduced by a factor better than 10. For a physical understanding of this, consider the path of the AC current from D1 to D2 to be split into two parts. That is, pass 1 is defined as a whole via the higher resistive portion at the top of the substrate SU, whereas pass 2 is laterally down from D1 via SU down to SL via SL, and finally Upward via SU to D2
Leads to. As before, at low frequencies, CD1, S
ubs dominates and shields any substrate coupling between devices. However, as the frequency increases, the resistive substrate current drops off (leaving only displacement current in this region) due to the resistance at the top of the substrate. However, during this transition, the resistance current via path 2 has already begun to drop. Because it has about twice the resistance of the current from the substrate (passing the SU only once).
Similarly, since the thickness of the SU is selected to be substantially the same as or less than the device width, the resistance through path 1 will also be at least as large as the resistance to the substrate. At frequencies higher than this transition, the AC current passing through the upper substrate between adjacent devices is primarily a displacement current. However, it should be noted that crosstalk from the displacement current is also reduced by the binary substrate. The displacement current via path 1 must still counter the charge provided by the substrate. More importantly, any displacement current to or from SL (as in pass 2) will be intercepted by highly doped region SL, still controlled by the substrate electrode. .

Assume that the circuit operates at 10 GHz.
The substrate resistance was chosen to be less than half that of the widest metal line used in the layout (in this example, 10 μm wide and 1.5 μm thick, or about 30 Ω / cm). Assuming that the resistivity of the SU is high enough that its skin depth is very large relative to its thickness, d in Equation 4 is the distance between the metal line and the SU / SL interface. Fudge factor (fud
ge factor) 3 and d = 40 μm (S in the above embodiment)
Assuming a thickness of 30 for U) and assuming a resistivity of 2E-4 ohm-cm (doping of 5E20 cm-3) for SL, the total substrate resistance is about 9 ohms. This is within a secure goal, even considering that the approximation is involved. In addition to an acceptable low substrate loss, the advantages of dual resistivity substrate crosstalk are as described in the previous section. SU doping can now be selected for optimal capacitance profile. From FIG.
Any value below 1015 cm-3 should be acceptable.

In order to reach higher frequencies, the thickness of the SU must be increased to lower the substrate resistance sufficiently, which at the expense of some of the substrate's shielding effectiveness. A more interesting solution may be to embed a highly conductive layer, such as silicide, on top of the SL or simply replace the SL with a metal.

Evaluation of the substrate resistance and crosstalk by physical criteria can be used as a guideline for optimizing the substrate properties to minimize and for compromising these parasitics. Binary-resistivity substrates are used as an example, and show that they have certain advantages over highly resistive substrates. FIG. 9 shows that even the most highly resistive substrates still allow significant crosstalk at 1 MHz, and for most circuits with components at 10 GHz, crosstalk can be important there. It shows that there are often other parts of the circuit that operate at lower frequencies. The actual resistivity of a highly resistive substrate can also be very sensitive to applied DC bias. Without insulating layer separation, carrier injection would destroy any high resistivity, and with separation, an accumulation or inversion layer could be created at the insulator / substrate interface. In the above example, a DC bias of 2V applied to the device creates a storage layer, which raises the peak of CD1, D3 by 50% and widens the peak width from 22db to 47db. The same bias applied to the binary-resistive substrate of the last example had no effect. This is because the additional conduction allowed by the storage layer has been reduced by the more highly doped substrate layer.

The binary-resistive substrate of the last embodiment has 10
It provided a good compromise between substrate resistance and crosstalk at GHz. At lower frequencies, the compromise is easier. A lower value of R results in a thinner SU, so that greater shielding from SL is obtained. 10
At frequencies much higher than GHz, interesting devices, such as buried ground planes or very thin substrates on metal, would be required to provide some significant shielding from crosstalk.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a bonded wafer including the present invention.

FIG. 2 is a cross-sectional view illustrating an alternative embodiment of the present invention.

FIG. 3 is a cross-sectional view showing an analytical model used to simulate the present invention.

FIG. 4 is another cross-sectional view showing a simplified analytical model.

FIG. 5 is a graph showing resistance vs. Log10 (resistivity) at a frequency of 109 Hertz for different substrate dopant levels.

FIG. 6 is a graph similar to FIG. 5 for frequency at 1010 Hertz.

FIG. 7 is a graph showing the accuracy of analytical simplification.

FIG. 8 is a cross-sectional view showing a bonded wafer having three devices.

FIG. 9 is a graph showing the capacitance between different elements of the bonded wafer of FIG. 8 as a function of frequency.

FIG. 10 is a graph showing the capacitance between devices D1 and D2 as a function of frequency for different levels of substrate doping in a conventional silicon substrate according to the prior art.

FIG. 11 is a graph showing the capacitance between devices D1 and D3 as a function of frequency for different levels of substrate doping in a conventional silicon substrate according to the prior art.

FIG. 12 shows devices D1 and D2 and devices D1 and D for a multilayer substrate prepared according to the present invention.
3 shows another capacitance between the three.

[Explanation of symbols]

 REFERENCE SIGNS LIST 10 bonded wafer 12 handle wafer 14 semi-insulating layer 15 barrier layer 16 handle wafer 18 insulating layer 20 device layer 22, 24 active device 30 bonded wafer 50 bonded wafer 52 handle substrate 54 bond oxide layer 56 device wafer 58 oxidation Material layer 60 insulating layer 62 metal line 64 semi-insulating layer

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Anthony Rivoli 32905, Florida, USA, Daytona Drive 1198 (72) Inventor Jorgie Bayor United States 32901, Florida, Malvern, Martwood Road 231 (72) Inventor Rex E. Lowther United States Florida 32907, North East Palm Bay, Pre-Mountain Court 980

Claims (8)

[Claims] 1. A device layer comprising a handle substrate, a semi-insulating layer on a handle wafer, an insulating layer, and single crystal silicon on the insulating layer, wherein the semi-insulating layer has a predetermined thickness. A semiconductor device comprising a wafer bonded by a semi-insulating layer to reduce loss and crosstalk at high frequencies. 2. The method according to claim 1, wherein the handle wafer is doped.
The device of claim 1, having a resistivity in the range of -10,000 ohm-cm, wherein the handle wafer preferably has a resistivity of less than 1 ohm-cm. 3. The semi-insulating layer comprises one selected from the group comprising diamond, silicon carbide and gallium arsenide, and the semi-insulating layer comprises polycrystalline silicon, amorphous silicon, SIPOS, FIPOS. 3. A device according to claim 1 comprising one of the group consisting of: and wherein the insulating layer is silicon dioxide. 4. The semi-insulating layer is thick enough to reduce substrate losses, the semi-insulating layer is thin enough to reduce crosstalk between circuit elements, and a barrier layer is provided between the handle wafer and the semi-insulating layer. A device according to any of the preceding claims, wherein 5. The barrier layer comprises an epitaxial layer of undoped silicon, wherein the semi-insulating layer is thicker than the thickness of the insulating layer, and preferably the semi-insulating layer is six times the minimum device width. 5. The device of claim 4, wherein the semi-insulating layer is narrower or thicker than the thickness of the insulating layer, but six times narrower than the smallest device width. 6. The barrier layer includes a metal layer or a silicide layer to increase the conductivity of the handle wafer, wherein the semi-insulating layer is thick enough to reduce resistivity loss, but does not increase shielding. A device according to any of claims 4 to 5, which is not too thick so that reducing it does not adversely affect crosstalk. 7. A handle substrate made of single-crystal silicon, a semi-insulating layer made of polysilicon on a handle wafer, an insulating layer made of silicon dioxide on the semi-insulating layer, and a device layer made of single-crystal silicon. A bonded wafer structure having a semi-insulating layer to reduce loss and crosstalk at high frequencies, comprising a silicon epitaxial layer disposed on a handle substrate. Semiconductor device composed. 8. A device layer comprising a single crystal semiconductor material including an integrated device forming an integrated circuit, wherein the device layers are separated by a first distance from each other, and a device layer for supporting the device layer. An upper substrate having a first resistivity and a controlled upper substrate thickness for controlling resistive losses due to high frequency signals; and a distance between the device layer and the lower substrate for supporting the upper substrate and for the upper substrate. A lower substrate having a second resistivity to suppress crosstalk between devices in the device layer, which is inversely proportional to the first resistivity, and wherein the first resistivity is greater than the second resistivity, and A semiconductor constituted by a substrate for carrying high-frequency signals, characterized in that the thickness of the substrate is approximately equal to or less than the width of the smallest active circuit device Body device.