JPH10322182A - Clock-disconnection detecting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock-disconnection detecting circuit in which the degree of freedom of arrangement can be obtained, the number of parts can be reduced, and the frequencies of a monitoring clock can be easily changed by monitoring a clock signal with only a digital circuit. SOLUTION: A clock-disconnection detecting circuit 10 is provided with a 1/n frequency-divider 11 which frequency-divides a monitoring clock input, a NAND gate 12 which inverts the frequency-divided output of the 1/n frequency-divider 11, a DFF 13 which receives a clock input to be monitored at a clock input, and clears it by the inverted output of the frequency dividing means, and DFF 14 which receives the output of the DFF 13 at a data input, receives the output of the 1/n frequency-divider 11 at a clock input, and outputs a Q output as a clock-disconnection detection signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock loss detection circuit, and more particularly, to a clock loss detection circuit for monitoring a clock signal in a digital device.

[0002]

2. Description of the Related Art The operation of a semiconductor integrated circuit such as a microcomputer is controlled by a clock signal, and the operating speed of the system is basically determined by the clock frequency (clock rate). Generally, a clock signal monitoring circuit in a conventional digital device is a general-purpose IC.
74LS123 of the 74 series and an analog circuit using a CR delay circuit composed of a resistor and a capacitor.

[0003]

However, in such a conventional clock signal monitoring circuit using a general-purpose IC and a CR delay circuit, a resistor value and a capacitor are used to determine the clock signal monitoring time. Had to be calculated and selected according to a calculation formula. Therefore, the frequency of the monitoring clock cannot be easily changed.

Further, since the connection between the resistor and the capacitor is an analog circuit, there is a problem that the monitoring time has to be confirmed by a waveform and that it has to be arranged apart from other digital signals.

According to the present invention, there is provided a clock disconnection detection circuit capable of monitoring a clock signal only by a digital circuit, improving the degree of freedom of arrangement and reducing the number of components, and easily changing the frequency of a monitoring clock. The purpose is to provide.

[0006]

A clock disconnection detection circuit according to the present invention comprises: a frequency dividing means for dividing a monitoring clock input;
A first flip-flop, which receives a monitored clock input at a clock input and is cleared by an inverted output of the frequency divider, receives an output of the first flip-flop at a data input, and receives an output of the frequency divider as a clock input Receiving, Q
A second flip-flop for outputting an output as a clock loss detection signal.

In the clock loss detection circuit, the data input of the first flip-flop and the clear input of the second flip-flop are connected to a power supply voltage, and the first flip-flop and the second flip-flop are It operates at the rising edge of the signal, and when the inverted output of the dividing means is at the H level, if the monitored clock rises at least once, the output of the first flip-flop remains high until the inverted output of the dividing means falls. The second flip-flop outputs the H level to the Q output when the output of the first flip-flop is at the H level when the output of the frequency dividing means rises, and the monitored clock is normal. May be detected.

[0008] The output waveform divided by the frequency dividing means may be slower than half the frequency of the monitored clock.

The first flip-flop and the second flip-flop may be synchronous flip-flops including a D flip-flop.

[0010] The frequency dividing means is configured to output one to the monitoring clock.
/ N (n is a natural number) to output an output waveform divided by 1 /
An n frequency divider may be used.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The clock cutoff detection circuit according to the present invention can be applied to a clock circuit for supplying a clock to an integrated circuit such as a microcomputer.

FIG. 1 is a circuit diagram showing a configuration of a clock disconnection detection circuit according to an embodiment of the present invention.

In FIG. 1, a clock disconnection detection circuit 10
Is a 1 / n (where n is a natural number) frequency divider 11 (frequency dividing means), a NAND gate 12, a D flip-flop (hereinafter, referred to as DFF) 13 (first flip-flop),
DFF14 (second flip-flop).

The reset input A is connected to the preset input pins PRN of the DFFs 13 and 14, and the monitored clock input B is connected to the DFF 13. Monitoring clock input C
Is connected to a 1 / n frequency divider 11, and the output after frequency division is input to a clear input C of a DFF 13 via a NAND gate 12.
It is connected to LRN and to the clock input of DFF14.

The data inputs D and DF of the DFF 13 are
The clear input CLRN of F14 is connected to the power supply voltage VCC, and the output Q of DFF13 is the data input D of DFF14.
It is connected to the. Then, the output Q of the DFF 14 becomes the clock cut detection output.

Hereinafter, the operation of the clock disconnection detection circuit 10 configured as described above will be described.

FIG. 2 is a timing chart for explaining the operation of the clock loss detection circuit 10. In the drawing, A to G correspond to signals A to G of the respective parts in FIG.

Waveform D divided by 1 / n frequency divider 11
Is set to be lower than 1/2 of the frequency of the monitored clock. Hereinafter, description will be made with reference to FIGS.

First, the reset input A becomes "H",
The preset of DFF13 and DFF14 is released.

The inverted signal E of the output D of the 1 / n frequency divider 11 becomes "L", whereby the DFF 13 is cleared and D
The Q output F of the FF 13 becomes “L”.

When the monitored clock B rises,
Since the clear input E of the DFF 13 is “H”, the DFF 13
The 13 Q output F becomes "H".

When the clock signal D of the DFF 14 rises, the data D input F is "H", so that the Q output, that is, the clock cutoff output G remains "H".

Thereafter, the inverted signal E of the output D of the 1 / n frequency divider 11 becomes "L", whereby the DFF 13 is cleared and the Q output F of the DFF 13 becomes "L".

When the monitored clock is operating normally, the above operations (1) to (4) are repeated, and the DFF 14
Is always "H" when the clock signal D of the DFF 14 rises. Thereby DFF1
The Q output of 4, ie, the clock cutoff output G, is always at "H".

This is because the clear input E of the DFF 13 is "H".
If the monitored clock B rises one or more times during this period, the Q output of the DFF 13 becomes “H”, and the condition is when the relationship of the expression (1) is established in units of frequency Hz.

B> E × 2 (1) where B is the monitored clock, and E is the inverted output of the 1 / n frequency divider 11 The monitored clock B is turned off.

When the clock signal D of the DFF 14 rises, the data D input F is "L", so that the Q output, that is, the clock cutoff output G becomes "L", and the clock cutoff of the monitored clock B is detected.

As described above, the clock loss detection circuit 10 according to the embodiment divides the monitoring clock input by one.
A / n frequency divider 11, a NAND gate 12 for inverting a frequency divided output of the 1 / n frequency divider 11, a DFF 13 receiving a monitored clock input at a clock input, and being cleared by an inverted output of the frequency dividing means; A DF that receives the output of DFF 13 at the data input, receives the output of 1 / n divider 11 at the clock input, and outputs the Q output as a clock loss detection signal
F14, when the inverted output of the 1 / n frequency divider 11 is at the H level and the monitored clock rises at least once, the output of the DFF 13 falls from the inverted output of the 1 / n frequency divider 11. Until the DF is output.
F14 is at the time of rising of the output of the 1 / n frequency divider 11,
Since the output of the FF 13 is at the H level, the Q output becomes H level.
Since the level is output to detect that the monitored clock is operating normally, the clock signal can be monitored only by the digital circuit.
A circuit can be provided inside the GA / PLD or the like, and the number of components can be reduced.

Further, since the frequency of the monitoring clock can be changed by the 1 / n frequency divider, it is possible to cope with various frequencies of the monitored clock without changing the design of parts.

Therefore, in a digital device, a synchronous clock signal input from the outside of the device is connected to the monitored clock input, and an asynchronous oscillator mounted inside the device is connected to the monitoring clock input, so that the clock disconnection can be detected. Become.

As described above, the clock disconnection detecting circuit 10 according to the present embodiment can detect the clock disconnection of only the digital circuit, which has been impossible in the past, and has a simple circuit configuration. It has the excellent feature that it can be done.

In the above embodiment, D flip-flops are used as the first flip-flop and the second flip-flop. However, the present invention is not limited to this, and other flip-flops performing the same operation may be used. . In addition, although the operation is performed at the rising edge of the signal, it is needless to say that the operation may be performed at the falling edge.

In the above embodiment, the frequency divider is applied to a frequency lower than half the frequency of the monitored clock. However, any frequency division may be used.

The above-described clock-break detection circuit can be applied to a clock-break detection circuit that supplies a clock signal to an integrated circuit such as a microcomputer, but any clock circuit that detects a clock can be used. Needless to say, this can also be applied. In addition, the clock loss detection circuit according to the present embodiment may be incorporated and installed inside an integrated circuit, or may be applied to an independent device.

Further, the type, number, connection state, and the like of the flip-flops and gate circuits constituting the clock cutoff detection circuit are not limited to the above embodiments.

[0036]

In the clock disconnection detection circuit according to the present invention,
Frequency dividing means for dividing the monitor clock input, a first flip-flop which receives the monitored clock input at the clock input and is cleared by the inverted output of the frequency dividing means, and an output of the first flip-flop as a data input And a second flip-flop that receives the output of the frequency dividing means at the clock input and outputs the Q output as a clock cutoff detection signal, so that the clock signal can be monitored only by the digital circuit, and the arrangement is free. The degree of improvement and the number of parts can be reduced, and the frequency of the monitoring clock can be easily changed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a clock cutoff detection circuit according to an embodiment to which the present invention is applied.

FIG. 2 is a timing chart for explaining the operation of the clock loss detection circuit.

[Explanation of symbols]

10 clock cutoff detection circuit, 11 1 / n frequency divider (frequency dividing means), 12 NAND gate, 13 DFF (first flip-flop), 14 DFF (second flip-flop)

Claims (5)

[Claims] 1. A frequency dividing means for dividing a monitored clock input, a first flip-flop which receives a monitored clock input at a clock input and is cleared by an inverted output of the frequency dividing means, and a first flip-flop A second flip-flop receiving an output of the frequency-dividing means at a data input, receiving an output of the frequency dividing means at a clock input, and outputting a Q output as a clock-loss detection signal. . 2. The clock disconnection detection circuit according to claim 1, wherein a data input of said first flip-flop and said second flip-flop are inputted.
Is connected to a power supply voltage, the first flip-flop and the second flip-flop operate at the rising edge of a signal, and the inverted output of the frequency dividing means is at the H level. When the monitored clock rises one or more times, the output of the first flip-flop outputs an H level until the inverted output of the frequency dividing means falls, and the second flip-flop outputs When the output of the frequency dividing means rises, the output of the first flip-flop is at the H level, so that the H output is output to the Q output to detect that the monitored clock is operating normally. Characteristic clock disconnection detection circuit. 3. The clock loss detection according to claim 1, wherein an output waveform divided by said frequency dividing means is made slower than 1/2 of a frequency of said monitored clock. circuit. 4. The flip-flop according to claim 1, wherein the first flip-flop and the second flip-flop are synchronous flip-flops including a D flip-flop.
Or the clock disconnection detection circuit according to any one of 2. 5. The frequency divider according to claim 1, wherein the frequency divider is a 1 / n frequency divider that outputs an output waveform obtained by dividing the monitor clock by 1 / n (n is a natural number). 4. The clock disconnection detection circuit according to any one of items 2 and 3.