JPH10321875A - Method for processing silicon wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable improvements in alignment accuracy between a circuit element and a recess formed on both sides of a silicon wafer by opening a throughhole in the silicon wafer by anisotropic etching and using this through- hole as a reference. SOLUTION: In a through-hole forming process, each through-hole 22 is formed on a back side 21B of a silicon wafer 21 by anisotropic etching. In an element-forming process, each piezoresistive element 25 is formed on a surface side 21A of the silicon wafer 21 with reference to each alignment mark 38 based on each through-hole 22. In a recess-forming process, a recess 26 is formed on the back side 21B of the silicon wafer 21 by anisotropic etching with reference to each through-hole 22. Thus, even in the case where there is a processing error on the surface 21A to be a cut surface of the silicon wafer 21, each piezoresistive element 25 and the recess 26 can be easily aligned with each other on the both sides of the silicon wafer 21.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of processing a silicon wafer suitable for forming a microstructure on the silicon wafer by, for example, a micromachining technique, and more particularly to a method of processing a silicon wafer on both sides. The present invention relates to a method for processing a silicon wafer used for a semiconductor device.

[0002]

2. Description of the Related Art In general, a silicon wafer processing method for forming a microstructure such as various sensors and semiconductor elements on a silicon wafer by, for example, a micromachining technique is used for forming a diaphragm-type pressure sensor. Used.

A case in which a conventional pressure sensor is formed on a silicon wafer will be described with reference to FIGS.

[0004] Reference numeral 1 denotes a silicon wafer serving as a substrate for processing and forming a pressure sensor 3 to be described later. The silicon wafer 1 is formed in a substantially disk shape having an outer diameter of, for example, about 10 cm, and has upper and lower surfaces. The front surface 1A and the rear surface 1B are formed so as to substantially coincide with the (1,0,0) plane of the silicon crystal. The silicon wafer 1 is divided into a plurality of areas 1C, 1C,... To form each pressure sensor 3, and each area 1C is formed as a silicon substrate 4 of the pressure sensor 3. A pair of alignment marks 2 and 2 are provided at predetermined positions as small-diameter convex portions on the front surface 1A side of the silicon wafer 1.

Reference numeral 3 denotes a diaphragm type pressure sensor formed in each area 1C of the silicon wafer 1. The pressure sensor 3 separates the silicon wafer 1 into each area 1C as shown in FIGS. 26 and 27. And a piezoresistive element 5 formed on the front surface 4A side of the silicon substrate 4 and having a resistance value that changes according to the applied strain, and a silicon substrate 4 formed on the back surface 4B side of the silicon substrate 4. A concave portion 6 and a flexible diaphragm portion 7 formed as a thin portion on the surface 4A side of the silicon substrate 4 by the concave portion 6
And lead terminals 8 connected to the piezoresistive element 5.

Here, the concave portion 6 is formed in a rectangular cross section by performing anisotropic etching on the silicon wafer 1 and formed along the (1,1,1) plane of the silicon crystal. , Four side walls 6A, 6A,.

When the fluid pressure or the like acts on the diaphragm 7, the pressure sensor 3 bends the diaphragm 7 in accordance with the pressure, causing distortion in the piezoresistive element 5. When the resistance value of the resistance element 5 changes, the change in the resistance value is detected from each lead terminal 8 as a change in pressure.

Reference numeral 9 denotes an exposure mask for forming the piezoresistive element 5 on the front surface 1A side of the silicon wafer 1. The exposure mask 9 has, as shown in FIG. A pair of alignment marks 9A, 9A are formed at the positions where they are to be performed. The exposure mask 9 has a plurality of areas 9B, 9 corresponding to the respective pressure sensors 3.
, And an exposure pattern (not shown) corresponding to the piezoresistive element 5 is formed at a predetermined position in each area 9B.

Reference numeral 10 denotes another exposure mask for forming the concave portion 6 on the back surface 1B side of the silicon wafer 1. The exposure mask 10 has substantially the same configuration as the exposure mask 9, and includes a pair of alignment marks 10A, 10A. , A plurality of areas 10B,
10B,..., And each area 10B has a recess 6
Is formed at a predetermined position.

The prior art has the above-described configuration. Next, a method of processing the silicon wafer 1 will be described with reference to FIGS.

First, with respect to the silicon wafer 1, FIG.
As shown in FIG. 1, a thin film 11 of a resistor material to be the piezoresistive element 5 is formed on the front surface 1A side, and an oxide film 12 is formed on the back surface 1B side. Subsequently, a photosensitive resist (not shown) or the like is applied to both sides of the silicon wafer 1 and the resist is exposed through the patterns of the exposure masks 9 and 10 to apply these patterns to the resist. Transcribe.

In this case, the piezoresistive element 5
The exposure masks 9 and 10 are accurately aligned with each other using, for example, a double-sided exposure equipment (not shown) in order to align the formation positions of the diaphragm and the diaphragm portion 7 (recess 6) on both sides of the silicon wafer 1. At the same time, the patterns of the exposure masks 9 and 10 are transferred to both sides of the silicon wafer 1 in this state.

Here, this double-sided exposure equipment is composed of a pair of exposure devices interlocked with each other, and each of these exposure devices is disposed at a position sandwiching both sides of the silicon wafer 1 upward and downward. Then, at the time of transferring the exposure masks 9 and 10, as shown in FIG. 25, the position of the exposure mask 9 is adjusted using an exposure apparatus on the front surface (upper surface), and each alignment mark 9A is aligned with each alignment of the silicon wafer 1. When the mark 2 coincides with the direction of the arrow A, the exposure device on the back side adjusts the position of the exposure mask 10 in conjunction with this, and the respective alignment marks 10A are aligned with the respective alignment marks 2 of the silicon wafer 1. The state is the same in the direction of arrow B. As a result, the patterns of the exposure masks 9 and 10 are simultaneously transferred to both surfaces of the silicon wafer 1 by the respective exposure devices as shown by arrows C in a state where they are aligned with each other.

After the patterns of the exposure masks 9 and 10 have been transferred, the thin film 11 is subjected to an etching treatment as shown in FIG. 27 to form the piezoresistive elements 5 on the surface 1A of the silicon wafer 1. . By performing an etching process on the oxide film 12, the concave portions 6 are formed.
Opening 12A of oxide film 12 corresponding to silicon wafer 1
Is formed on the back surface 1B side.

Next, by using an etching solution such as KOH, hydrazine or the like, anisotropic etching is performed for a predetermined time on the back surface 1B side of the silicon wafer 1 using the oxide film 12 as a mask to form the concave portion 6. Then, a diaphragm portion 7 is provided. Then, each pressure sensor 3 is separated from the silicon wafer 1 for each silicon substrate 4.

[0016]

In the above-mentioned prior art, the front surface 1A and the back surface 1A of the silicon wafer 1 are not provided.
The B side is cut so as to coincide with the (1,0,0) plane of the silicon crystal, and an anisotropic pattern using, for example, KOH, hydrazine or the like is applied from the back surface 1B side to the front surface 1A side of the silicon wafer 1. As shown in FIG. 27, a concave portion 6 is formed in the silicon wafer 1 by performing an etching process, and each side wall 6A of the concave portion 6 is fixed to the (1,0,0) plane as shown in FIG. The silicon crystal is formed along the (1,1,1) plane of the silicon crystal inclined at an angle α (for example, about 53.7 °).

In this case, each side wall 6A of the concave portion 6 is formed so as to be inclined at an angle α with respect to the surface 1A from the opening 12A of the oxide film 12 toward the surface 1A which is a cut surface of the silicon wafer 1. . As a result, the diaphragm portion 7 is formed on the surface 1A side of the silicon wafer 1 at a predetermined position corresponding to the opening 12A of the oxide film 12, and the formation position is aligned with the piezoresistive element 5.

However, the surface 1A serving as the cut surface of the silicon wafer 1 has an error in slicing and polishing when the wafer is cut (cut), as shown in FIG.
For example, the angle may vary from the (1,0,0) plane S by about 1 to 3 °. Then, when the recess 6 is formed by anisotropic etching on the silicon wafer 1 in this state, the recess 6 is formed with respect to each side wall 6A 'of the original recess 6' shown by a two-dot chain line in FIG. Each side wall 6A is in an inclined state.

For this reason, in the prior art, as shown in FIG. 28, the diaphragm 7 may be displaced from the piezoresistive element 5 by a dimension d0, and the deflection of the diaphragm 7 by the piezoresistive element 5 can be performed with high precision. There is a problem that it becomes difficult to detect.

The present invention has been made in view of the above-described problems of the prior art, and the present invention makes it possible to easily perform double-sided processing on a silicon wafer by using anisotropic etching even when the cut surface of the silicon wafer varies. Can be applied to
It is an object of the present invention to provide a method of processing a silicon wafer in which circuit elements and recesses formed on the front and back sides of the silicon wafer can be easily aligned on both sides of the silicon wafer.

[0021]

According to a first aspect of the present invention, a silicon wafer serving as a substrate is anisotropically etched from one side toward the other side of the silicon wafer. A transmission hole forming step of forming a transmission hole at a predetermined position of the silicon wafer; an element forming step of forming a circuit element on one surface side of the silicon wafer with the transmission hole as a reference; A recess forming step of forming a recess at a position corresponding to the circuit element by performing anisotropic etching from the other surface of the silicon wafer toward the one surface, and employing a method of processing a silicon wafer. ing.

According to the method described above, in the through hole forming step, through holes are formed along the crystal plane of the silicon wafer using anisotropic etching, and in the recess forming step, a recess is formed by the same anisotropic etching. Therefore, even when the cut surface of the silicon wafer has a variation, it is possible to easily align the circuit element formed on the one surface side of the silicon wafer with reference to the transmission hole and the concave portion formed on the other surface side of the silicon wafer. Thus, it is possible to prevent the circuit elements and the concave portions from being displaced from each other on both sides of the silicon wafer.

According to the second aspect of the present invention, a silicon wafer serving as a substrate is subjected to anisotropic etching from one side toward the one side, thereby forming a transmission hole at a predetermined position on the silicon wafer. Forming a positioning mark on one surface of the silicon wafer with reference to the transmission hole; and forming a circuit on the one surface of the silicon wafer with the positioning mark as a reference. A recess for forming a recess at a position corresponding to the circuit element by performing an element forming step of forming a device and performing anisotropic etching from the other surface of the silicon wafer toward the one surface with reference to the transmission hole; And a silicon wafer processing method including a forming step.

Thus, in the alignment mark forming step, an alignment mark can be formed on one surface side of the silicon wafer with reference to the transmission hole. The recess formed on the basis of the transmission hole in the forming step can be easily aligned on both sides of the silicon wafer. Further, even when the transmission hole is closed by, for example, an etching material during the element forming step, the circuit element can be positioned with respect to one surface side of the silicon wafer by the alignment mark.

According to a third aspect of the present invention, in the element forming step, the alignment mark of the first exposure mask prepared in advance matches the alignment mark of the silicon wafer. Transferring the pattern of the first exposure mask to the side to form the circuit element,
In the recess forming step, the alignment mark of the second exposure mask prepared in advance is made to coincide with the transmission hole of the silicon wafer, and in this state, the pattern of the second exposure mask is transferred to the other surface of the silicon wafer. To form the recess.

Thus, in the element forming step, the alignment mark of the first exposure mask is made to coincide with the alignment mark of the silicon wafer, and in the concave part forming step, the alignment mark of the second exposure mask is made to coincide with the transmission hole. The patterns of the respective exposure masks can be transferred to both sides of the silicon wafer in a state where they are aligned with each other with reference to the transmission holes, so that the circuit elements and the concave portions can be aligned with each other.

[0027]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

FIGS. 1 to 24 show an embodiment of the present invention. In this embodiment, a case where a diaphragm type pressure sensor is formed on a silicon wafer by way of example will be described.

Reference numeral 21 denotes a silicon wafer serving as a substrate for processing and forming a pressure sensor 23 to be described later. The silicon wafer 21 has substantially the same structure as the conventional silicon wafer 1, and has a surface 21A serving as upper and lower surfaces. , Back 21B
Are formed so as to substantially coincide with the (1, 0, 0) plane of the silicon crystal. The silicon wafer 21 has a plurality of areas 21C corresponding to each pressure sensor 23,
, And a chamfered portion 21D (so-called orientation flat) located on the outer peripheral side.

Reference numerals 22 and 22 denote a pair of transmission holes formed in the silicon wafer 21. The transmission holes 22 are formed at predetermined positions on the outer peripheral side of the silicon wafer 21 so as to face each other in the radial direction. The direction in which the transmission holes 22 are separated from each other matches the direction in which the chamfered portion 21D extends.

As shown in FIGS. 2 and 3, each transmission hole 22 is formed in a substantially quadrangular pyramid shape by performing anisotropic etching on the back surface 21B of the silicon wafer 21. Each of the transmission holes 22 has a square-shaped opening 22 on the surface 21A of the silicon wafer 21.
A, a square-shaped other-side opening 22B opening on the back surface 21B of the silicon wafer 21, and (1, 1,
1) Four side walls 22C, 22C, formed along the plane
.., For example, the one side opening 22A is formed as a square hole of about several tens of μm, and the other side opening 22B is formed as a square hole of about several hundred μm.

Reference numeral 23 denotes a diaphragm-type pressure sensor which is formed on the silicon wafer 21. The pressure sensor 23 includes a silicon substrate 24, which will be described later, as shown in FIGS.
It is composed of piezoresistive elements 25, 25, recess 26, diaphragm 27, wiring 28, and the like. Then, similarly to the pressure sensor 3 of the related art, the pressure sensor 23 converts the strain generated in each piezoresistive element 25 into a change in the resistance value of the wiring section 28 by bending the diaphragm section 27 by the action of the fluid pressure or the like. Is to be detected from

Numeral 24 designates the silicon wafer 21 in each area 21
The silicon substrate 24 is formed as a p-type silicon plate by adding an impurity such as boron, for example, and is formed on the back surface 21B side of the silicon wafer 21. Part 24A
And a surface layer portion 24B integrally formed as an n-type silicon layer on the surface side of the base portion 24A and having a thickness of, for example, about 5 to 10 μm.

Reference numerals 25, 25 denote piezoresistive elements as circuit elements provided on the silicon substrate 24. Each of the piezoresistive elements 25 is formed by ion-implanting impurities such as boron into the surface layer 24B of the silicon substrate 24. , And is disposed at a predetermined position on the outer edge side of the diaphragm 27. Each piezoresistive element 25 detects a fluid pressure or the like applied to the diaphragm 27 as a change in resistance value.

Reference numeral 26 denotes a concave portion provided on the back surface side of the silicon substrate 24. The concave portion 26 is formed by performing anisotropic etching from the back surface side of the silicon substrate 24 to form a base portion 24A.
And is formed with a certain depth to a position reaching the surface portion 24B. The concave portion 26 has a substantially quadrangular pyramid shape, and has four side walls 26A, 26A,... Formed along the (1,1,1) plane of the silicon crystal.

Reference numeral 27 denotes a thin diaphragm portion formed on the surface layer portion 24B of the silicon substrate 24 by the concave portion 26. The diaphragm portion 27 has a substantially square shape, and each piezoresistive element 25 is formed in accordance with an applied fluid pressure or the like. And bends with it.

Reference numeral 28 denotes a wiring portion for leading a detection signal from each piezoresistive element 25 to the outside.
For example, it is formed in a substantially U-shape by a metal material such as aluminum, and is disposed on the silicon substrate 24 via an insulating portion 29 made of a silicon oxide film (SiO ₂ ).

The wiring part 28 is connected to the longitudinal ends of each of the piezoresistive elements 25 via contact holes 29A, 29A,.
As a result, the piezoresistive elements 25 are connected in series between the pair of electrode parts 28A, 28A formed on both ends of the wiring part 28.

Reference numeral 30 denotes each transmission hole 22 in the silicon wafer 21.
The exposure mask 30 has a plurality of transmission holes 2 at predetermined positions as shown in FIG.
2 are formed.

Reference numeral 31 denotes an exposure mask for forming alignment marks 38, 38, which will be described later, on the surface 21A side of the silicon wafer 21. The exposure mask 31 has an alignment corresponding to each transmission hole 22 of the silicon wafer 21. Mark 31
A and 31A, and patterns 31B and 31B for forming each alignment mark 38 are provided.

Reference numeral 32 denotes a first exposure mask for forming each piezoresistive element 25 on the surface 21A side of the silicon wafer 21. The first exposure mask 32 is, as shown in FIG. , And has alignment marks 32A, 32A corresponding to the respective alignment marks 38 of the silicon wafer 21 and patterns (not shown) for forming the respective piezoresistive elements 25.

Further, another exposure mask 33 for the insulating portion 29 is used.
Also, each alignment mark 33A and a pattern for forming the insulating section 29 are provided, and each exposure mark 34 for the wiring section 28 is similarly provided with each alignment mark 34A.

Reference numeral 35 denotes a second exposure mask for forming the concave portion 26 on the back surface 21B side of the silicon wafer 21.
The exposure mask is provided with alignment marks 35A, 35A corresponding to the respective transmission holes 22 and a pattern (not shown) for forming the concave portion 26.

This embodiment has the above-described configuration. Next, a method of processing the silicon wafer 21 will be described with reference to FIGS.

First, in the through hole forming step shown in FIGS. 8 and 9, the silicon oxide films 36, 36 are formed on both sides of the silicon wafer 21 by, for example, thermal oxidation, CVD, or the like, and then the back surface 21B side is formed. The oxide film 36 is subjected to an etching process using the exposure mask 30 in FIG. 6 to form openings 36A corresponding to the respective patterns 30A.

In this case, each pattern 3 of the exposure mask 30
0A is transferred to a photosensitive resist (not shown) or the like applied on the oxide film 36 on the back side in the direction of arrow D shown in FIG. Is done.

Subsequently, an anisotropic etching process using, for example, KOH, hydrazine or the like is performed on the back surface 21B side of the silicon wafer 21 for a predetermined time using the oxide film 36 as a mask. Then, the oxide film 36 on the surface 21A side is removed.

Next, in the surface layer forming step shown in FIG.
For example, a single-crystal silicon layer is stacked on the surface 21A side of the silicon wafer 21 by using an epitaxial growth method or the like, and a surface portion 24B of the silicon substrate 24 is formed.

Next, in the alignment mark forming step shown in FIGS. 11 and 12, the silicon nitride film (Si ₃
After the formation of N ₄ ) 37, the nitride film 37 is subjected to an etching process using the exposure mask 31 shown in FIG. 6, and convex alignment marks 38, 38 corresponding to the respective patterns 31 B are formed. It is formed at a predetermined position on the wafer 21.

In this case, as shown in FIG. 6, the exposure mask 31 is held by the exposure device 41 such that each alignment mark 31A coincides with each transmission hole 22 of the silicon wafer 21 in the direction of arrow E. Then, each pattern 31B is transferred in the direction of arrow F to the nitride film 37 side.

Next, in the element forming steps shown in FIGS. 13 to 17, each piezoresistive element 25 is formed on the surface 21A side of the silicon wafer 21 using the first exposure mask 32.

That is, as shown in FIG. 13, first, a silicon oxide film 39 is formed on the surface 21 A side of the silicon wafer 21.
To form Then, as shown in FIG. 14, after applying a photosensitive resist 40 on the oxide film 39, the pattern of the first exposure mask 32 is transferred to the resist 40 by the one-sided exposure device 41 to form the opening 40A.

As shown in FIG. 17, the single-sided exposure apparatus 41 includes a wafer processing base 41A on which the silicon wafer 21 is mounted and an enlarged image of the silicon wafer 21 as a first exposure mask 32. And a position adjustment mechanism for adjusting the relative position between the first exposure mask 32 and the like and the base 41A, and irradiation equipment (neither is shown). I have.

When transferring the pattern of the first exposure mask 32, first, the silicon wafer 21 is
After being placed on the base 41A so that the A side faces upward, each alignment mark 32A of the first exposure mask 32 set in the exposure apparatus 41 and the silicon wafer seen through the first exposure mask 32 The respective alignment marks 38 of 21 are aligned with each other in the direction of arrow G. And
In this state, the irradiation device exposes the surface 21A side of the silicon wafer 21 from the direction of arrow H through the first exposure mask 32, and transfers the pattern of the first exposure mask 32 to the resist 40 to open the opening 40A. Form.

In this case, as shown in FIG. 14, the resist 40 rises in a stepped shape corresponding to these alignment marks 38 at the position of each alignment mark 38. Each alignment mark 38 is identified through the oxide film 39 and the resist 40, and the first exposure mask 32 is aligned.

After the opening 40A is formed in the resist 40, as shown in FIG. 15, the oxide film 39 is etched using the resist 40 as a mask to form an opening 39A for ion implantation. Subsequently, the oxide film 3
9 is used as a mask, ions of boron or the like are implanted into the surface 21A of the silicon wafer 21 to form the respective piezoresistive elements 25 on the surface layer portion 24B of the silicon substrate 24.
The oxide film 39 is removed as shown in FIG.

Next, in an insulating portion forming step shown in FIGS. 18 and 19, after a silicon oxide film 42 is formed on the surface 21A side of the silicon wafer 21, an exposure device 41 transfers the silicon oxide film 42 to the exposed portion. The insulating portion 29 is formed on the silicon wafer 21 by performing an etching process based on the pattern of the mask 33.

Next, in the wiring portion forming step shown in FIGS. 20 and 21, a metal film 43 of aluminum or the like is formed on the surface 2 of the silicon wafer 21 by, for example, a CVD method or a sputtering method.
An exposure mask 34 formed on the insulating portion 29 on the 1A side and transferred to the metal film 43 by an exposure device 41.
Is subjected to an etching process based on the pattern of
8 is formed on the silicon wafer 21 via the insulating portion 29.

Next, in the recess forming step shown in FIGS. 22 and 23, the recess 26 is formed on the back surface 21 B side of the silicon wafer 21 using the second exposure mask 35.

That is, in the concave portion forming step, as shown in FIG. 22, the silicon wafer 21 is turned on the base 41A of the exposure apparatus 41 in a state where the silicon wafer 21 is turned to the back surface 21B side by substantially the same procedure as the element forming step. Each alignment mark 35 of the second exposure mask 35 placed and set on the exposure device 41
A and each transmission hole 22 of the silicon wafer 21 are made to coincide with each other.

Then, in this state, the back surface 21B side of the silicon wafer 21 is exposed through the second exposure mask 35,
After the pattern of the second exposure mask 35 is transferred to the back surface 21B side, the oxide film 36 on the back surface 21B side is subjected to an etching treatment as shown in FIG. Form.

Next, an anisotropic etching process using, for example, KOH, hydrazine or the like is performed on the back surface 21B side of the silicon wafer 21 for a predetermined time using the oxide film 36 as a mask, thereby forming the concave portion 26. As a result, a diaphragm portion 27 is formed on the surface 21A side of the silicon wafer 21 by the concave portion 26.

In this case, since each piezoresistive element 25 and concave portion 26 are positioned with reference to each transmission hole 22 and each alignment mark 38, the concave portion 2
6 extends to the surface 21A side of the silicon wafer 21 along the (1,1,1) plane of the silicon crystal, so that the diaphragm 27 and the piezoresistive elements 25 are aligned with each other as shown in FIG. It is formed on both sides of the silicon wafer 21 in this state.

As shown in FIG. 5, the surface 21A serving as the cut surface of the silicon wafer 21 may have an angle variation with respect to the (1,0,0) plane S due to an error in the wafer cutting or the like. . Then, in this state, the silicon wafer 21 is subjected to the anisotropic etching process to form the concave portions 2.
When the groove 6 is formed, the concave portion 26 is formed in an inclined state like a concave portion 26 'shown by a two-dot chain line in FIG. 5, and as a result, the diaphragm portion 27 is displaced by a dimension d1 with respect to each piezoresistive element 25. become.

Therefore, in the present embodiment, each transmission hole 22 is formed by performing anisotropic etching on the back surface 21B side of the silicon wafer 21 in the transmission hole forming step, and in the element forming step, each transmission hole 22 is formed. Surface 21 of silicon wafer 21 with reference to each alignment mark 38 based on
Each piezoresistive element 25 is formed on the A side, and in the concave part forming step, the concave part 26 is formed by performing anisotropic etching on the back surface 21B side of the silicon wafer 21 with respect to each transmission hole 22 as a reference. .

Thus, even when there is a processing error in the surface 21A serving as the cut surface of the silicon wafer 21, each piezoresistive element 25 and the concave portion 26 (diaphragm 27) are easily aligned on both sides of the silicon wafer 21. be able to.

That is, in the state where there is an angular processing error between the surface 21A of the silicon wafer 21 and the (1,0,0) plane S, the concave portion 26 'is formed as shown by a two-dot chain line in FIG. The diaphragm 27 is inclined with respect to the original recess 26,
The position is shifted rightward from the original forming position by the dimension d1.

However, in this embodiment, in the transmission hole forming step, each transmission hole 22 ′ formed by the anisotropic etching process is different from the original transmission hole 22 as shown by a two-dot chain line in FIG. The one side opening 22A 'is opened at a position shifted from the original one side opening 22A to the right in FIG. 3 by the dimension d1.

As a result, the respective alignment marks 38 'are also formed at positions shifted in this direction by the dimension d1 as shown in FIG. 12, so that the respective alignment marks 38' are used as a reference in the element forming process. Similarly, each piezoresistive element 25 is formed at a position shifted in this direction from the original position by the dimension d1.

As a result, as shown in FIG. 23, each of the piezoresistive elements 25 and the diaphragm portion 27 are formed at positions deviated to the right by the dimension d1 from their original positions. Are disposed on both sides of the silicon wafer 21 with the same relative position as when the surface 21A of the silicon wafer 21 coincides with the (1, 0, 0) plane S.

Similarly, for example, the diaphragm portion 2
7 'is d1 in the right direction in FIG.
Even when the position is shifted upward by the dimension d2, each transmission hole 22 'is formed at a position shifted by the same dimensions d1 and d2 as the diaphragm portion 27' as shown by the two-dot chain line in FIG. , Each piezoresistive element 25 and diaphragm section 2
7 'are aligned with each other as shown in FIG.

Therefore, according to the present embodiment, even when the surface 21A (cut surface) of the silicon wafer 21 varies, the piezoresistive elements 25 and the diaphragm 27 (recess 26) are formed on both sides of the silicon wafer 21. And the silicon wafer 21 can be easily subjected to double-sided processing using anisotropic etching, and each piezoresistive element 25 can be properly mounted on the diaphragm 27. The pressure sensor 23 can be formed at a high accuracy with a stable detection performance.

Further, each of the transmission holes 22 is formed in the silicon wafer 21.
Can be applied to each of the piezoresistive elements 25 by sequentially processing the silicon wafer 21 one by one using a single exposure apparatus 41.
And the diaphragm 27 can be aligned with high accuracy, and the equipment for exposure can be greatly simplified as compared with the prior art.

Further, in the alignment mark forming step,
Since the respective alignment marks 38 are formed on the front surface 21A side of the silicon wafer 21 with reference to the respective transmission holes 22, for example, in the element forming step, for example, the oxide films 39, 42,
When the metal film 43, the resist 40, and the like are formed on the surface 21A of the silicon wafer 21, even if one side opening 22A of each of the transmission holes 22 is closed by these film members, a step is formed through these film members. The alignment of the first exposure mask 32 and the like can be reliably performed using the alignment marks 38 that are raised in the form of a stick, and the degree of freedom in processing the silicon wafer 21 can be increased.

In the above embodiment, each alignment mark 38 is formed on the surface 21A of the silicon wafer 21 by the alignment mark forming step. However, the present invention is not limited to this, and each alignment mark 38 is formed. May be omitted, and the silicon wafer 21 may be subjected to double-sided processing with reference to the opening 22A on one side and the opening 22B on the other side of each transmission hole 22.

In the above embodiment, each transmission hole 22 is opened on both sides of the silicon wafer 21.
The present invention is not limited to this. For example, any transmission hole that can substantially transmit light or the like to both sides of the silicon wafer 21 may be used. For example, as shown in FIG. The element forming step and the concave part forming step are performed while keeping
May be formed as small-diameter holes that can be seen through from both sides of the silicon wafer 21.

Further, in the above embodiment, the case where the pressure sensor 23 is formed on the silicon wafer 21 has been described as an example. However, the present invention is not limited to this. For example, a vibration sensor, a flow rate / flow rate sensor, or a semiconductor device may be used. The present invention may be applied to a case where a microstructure formed of an integrated circuit or the like is processed and formed on both sides of a silicon wafer.

[0078]

As described in detail above, according to the first aspect of the present invention, in the through hole forming step, through holes are formed along the crystal plane of the silicon wafer by using anisotropic etching to form recesses. Since the concave portion is formed by the same anisotropic etching in the process, even if the cut surface of the silicon wafer has a variation due to a processing error or the like, the circuit element formed on the one surface side of the silicon wafer based on the transmission hole is used. The recess formed on the other surface of the silicon wafer can be easily matched, and the circuit element and the recess can be reliably prevented from being displaced on both sides of the silicon wafer. Therefore, even when there is a variation in the cut surface of the silicon wafer, double-sided processing using anisotropic etching can be easily performed on the silicon wafer, and circuit elements formed on the front surface and the back surface of the silicon wafer can be used. The concave portion can be stably aligned on both sides of the silicon wafer. In addition, even when a single exposure apparatus is used when performing double-sided processing on a silicon wafer, circuit elements and concave portions can be formed in alignment on both sides, thereby eliminating the need to employ, for example, a double-sided exposure apparatus. The size and cost of the exposure equipment can be reduced.

According to the second aspect of the present invention, in the alignment mark forming step, the alignment mark is formed on one surface side of the silicon wafer with reference to the transmission hole. And the recess formed based on the transmission hole in the recess forming step can be easily matched on both sides of the silicon wafer. Further, even in the case where the transmission hole is blocked by, for example, an etching material during the element forming process, the circuit element can be formed on one surface side of the silicon wafer with high positioning accuracy with reference to the alignment mark.

Further, according to the third aspect of the present invention,
By aligning the alignment mark of the first exposure mask with the alignment mark of the silicon wafer in the element forming step, and aligning the alignment mark of the second exposure mask with the transmission hole in the concave part forming step, the first and second exposure masks are formed. The respective patterns of the mask can be transferred to both sides of the silicon wafer in a state where they are aligned with each other with reference to the transmission holes. Based on these transferred patterns, the circuit element and the recess can be aligned with each other with high precision.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a silicon wafer used in an embodiment of the present invention.

FIG. 2 is an enlarged plan view showing a transmission hole formed in a silicon wafer.

FIG. 3 is an enlarged sectional view as seen from the direction of arrows III-III in FIG. 2;

FIG. 4 is a plan view showing a pressure sensor formed from a silicon wafer.

FIG. 5 is an enlarged cross-sectional view as viewed from a direction indicated by arrows VV in FIG. 4;

FIG. 6 is a perspective view showing a state in which an exposure mask and the like for each transmission hole are aligned with a silicon wafer.

FIG. 7 is a perspective view showing a state in which first and second exposure masks and the like are aligned with respect to a silicon wafer.

FIG. 8 is an enlarged longitudinal sectional view showing a state in which oxide films are formed on both sides of a silicon wafer.

9 is a vertical sectional view similar to FIG. 8, showing a state in which a transmission hole is formed from the back surface side of the silicon wafer in the transmission hole forming step.

FIG. 10 is a longitudinal sectional view showing a state in which a surface layer portion of silicon is formed on the front surface side of the silicon wafer after the through hole forming step.

FIG. 11 is a longitudinal sectional view showing a state in which a silicon nitride film is formed on the front side of a silicon wafer.

FIG. 12 is a longitudinal sectional view showing an alignment mark forming step of forming an alignment mark on the front surface side of a silicon wafer with a nitride film.

FIG. 13 is a longitudinal sectional view showing a state where a silicon oxide film is formed on the front surface side of the silicon wafer after the alignment mark forming step.

FIG. 14 is a longitudinal sectional view showing a state where a pattern of a first exposure mask is transferred to a resist applied on the oxide film in FIG. 13 in an element forming step.

FIG. 15 is a longitudinal sectional view showing a state in which a piezoresistive element is formed on the front surface side of a silicon wafer using the oxide film in FIG. 14 as a mask in an element forming step.

FIG. 16 is a longitudinal sectional view showing a state in which an oxide film has been removed from the surface side of a silicon wafer on which a piezoresistive element has been formed.

FIG. 17 is a perspective view showing a state in which the front side of a silicon wafer placed on a base of an exposure apparatus in a device forming step is exposed through a first exposure mask.

FIG. 18 is a longitudinal sectional view showing a state in which a silicon oxide film is formed on the surface side of a silicon wafer from above a piezoresistive element.

FIG. 19 is a longitudinal sectional view showing a state in which an insulating portion is formed on the front side of a silicon wafer by an oxide film.

FIG. 20 is a longitudinal sectional view showing a state in which a metal film is formed on the surface of the silicon wafer from above the insulating portion.

FIG. 21 is a longitudinal sectional view showing a state in which a wiring portion is formed by a metal film on the front side of a silicon wafer via an insulating portion.

FIG. 22 is a perspective view showing a state in which a pattern of a second exposure mask is transferred to the back surface side of the silicon wafer in the recess forming step.

FIG. 23 is a longitudinal sectional view showing a state in which a concave portion for a diaphragm is formed from the back surface side to the front surface side of the silicon wafer in the concave portion forming step.

FIG. 24 is a plan view similar to FIG. 4, illustrating a pressure sensor formed on a silicon wafer having a variation in cut surface.

FIG. 25 is a perspective view showing a conventional silicon wafer and the like.

FIG. 26 is a partially broken perspective view showing a pressure sensor formed from a silicon wafer.

FIG. 27 is a longitudinal sectional view of the pressure sensor shown in FIG. 26.

FIG. 28 is a vertical cross-sectional view showing a state where a concave portion for a diaphragm portion is inclined due to a variation generated on a cut surface of a silicon wafer.

[Explanation of symbols]

 Reference Signs List 21 silicon wafer 22 transmission hole 23 pressure sensor 25 piezoresistive element (circuit element) 26 recess 27 diaphragm section 32 first exposure mask 32A alignment mark 35 second exposure mask 35A alignment mark 38 alignment mark

Claims (3)

[Claims] 1. A through hole forming step of forming a through hole at a predetermined position on a silicon wafer serving as a substrate by subjecting the silicon wafer to an anisotropic etching from one side toward the other side. An element forming step of forming a circuit element on one surface side of the silicon wafer based on the transmission hole, and performing anisotropic etching from the other surface side of the silicon wafer to one surface side on the basis of the transmission hole. A recess forming step of forming a recess at a position corresponding to the circuit element. 2. A transmission hole forming step of forming a transmission hole at a predetermined position on a silicon wafer serving as a substrate by subjecting the silicon wafer to anisotropic etching from one side toward the other side. An alignment mark forming step of forming an alignment mark on one surface side of the silicon wafer based on the transmission hole; and an element forming step of forming a circuit element on one surface side of the silicon wafer based on the alignment mark. And a recess forming step of forming a recess at a position corresponding to the circuit element by performing anisotropic etching from the other surface of the silicon wafer toward the one surface with reference to the transmission hole. Silicon wafer processing method. 3. In the element forming step, the alignment mark of the first exposure mask prepared in advance is matched with the alignment mark of the silicon wafer, and in this state, the first exposure mask is placed on one surface side of the silicon wafer. The pattern is transferred to form the circuit element, and in the recess forming step,
The alignment mark of the second exposure mask prepared in advance is aligned with the transmission hole of the silicon wafer, and in this state, the pattern of the second exposure mask is transferred to the other surface of the silicon wafer to form the recess. 3. The method for processing a silicon wafer according to claim 2, comprising: