JPH10303384A - Method for producing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a producing method for semiconductor device with high memory holding characteristics. SOLUTION: Gate electrodes 9b, 9d and (n) and source/drain areas 4a-4d are respectively formed in a memory cell area A and a peripheral circuit area B. A silicon nitride film 8 is formed so as to cover gate electrodes 9a-9c. A side wall is formed by executing aeolotropic etching only to the silicon nitride film 8 located in the peripheral circuit area B. Further, a borophospho-silicate glass(BPSG) film 15 and a silicon oxide film 20 are formed, and a storage node contact hole 11 is formed on these films. At the storage node contact hole 11, a storage node pillar part 21a is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device capable of reducing a leakage current.

[0002]

2. Description of the Related Art First, as an example of a conventional semiconductor device, a dynamic random access memory (hereinafter referred to as "DR") is used.
AM ”) will be described with reference to the drawings.

Referring to FIG. 11, a memory cell region A and a peripheral circuit region B which are electrically insulated by an element isolation oxide film 2 are formed on the surface of a semiconductor substrate 1. Gate electrodes 9a and 9b are formed on the semiconductor substrate 1 in the memory cell region A. Further, a gate electrode 9c is formed on the element isolation oxide film 2. The gate electrodes 9 a and 9 b are formed between the gate insulating film 3 and the semiconductor substrate 1.
a and 3b are interposed.

The upper surfaces and both side surfaces of each of the gate electrodes 9a, 9b, 9c are covered with silicon nitride films 7a, 7b, 7c,
They are covered with sidewalls 8a, 8b, 8c, respectively. A pair of n ^- source / drain regions 4a and 4b are formed in the semiconductor substrate 1 with the gate electrode 9b interposed therebetween. MOS transistor T1 is constituted by gate electrode 9b and a pair of n ^- source / drain regions 4a and 4b.

On the other hand, on the semiconductor substrate 1 in the peripheral circuit region B,
Means that the gate electrode 9d is formed with the gate insulating film 3c interposed.
Has been established. The upper surface and both side surfaces of the gate electrode 9d are
Recon nitride film 7d and side wall 8d
And coated. Semiconductor substrate with gate electrode 9d interposed
One has a pair of n^-Source / drain regions 4c, 4d and n
⁺Source / drain regions 4e and 4f are formed.
You. Gate electrode 9d, a pair of n^-Source / drain region
4c, 4d, n⁺Source / drain regions 4e, 4f
A MOS transistor T2.

Gate electrodes 9a-7d covered with silicon nitride films 7a-7d and side walls 8a-8d.
BPSG (Boro P) on the semiconductor substrate 1 so as to cover 9d.
(Hospho Silicate Glass) film 15 is formed. A bit line contact hole 13 exposing the surface of n ⁻ source / drain region 4a is formed in BPSG film 15. In the bit line contact hole 13, a bit line 18 including a doped polysilicon film 17 and a tungsten silicide film 19 is formed.

The BPSG film 15 covers the bit line 18.
A silicon oxide film 20 is formed thereon. In silicon oxide film 20 and BPSG film 15, storage node contact hole 11 exposing the surface of n ^- source / drain region 4b is formed. On the silicon oxide film 20, a storage node 21 is formed. Storage node 21 is electrically connected to n ^- source / drain region 4b by storage node pillar 21a embedded in storage node contact hole 11.

A cell plate 23 made of a doped polysilicon film is formed on storage node 21 with a capacitor insulating film 22 made of a silicon nitride film or the like interposed. Storage node 21, capacitor insulating film 2
2 and the cell plate 23 form a capacitor 24. One memory cell is constituted by the capacitor 24 and the MOS transistor T1. In the memory cell area A, a plurality of such memory cells are formed. In order to control the memory cell, a semiconductor element including a MOS transistor T2 is formed in the peripheral circuit region B. The main part of the DRAM is configured as described above.

Next, an example of a method of manufacturing the above-described DRAM will be described with reference to the drawings. First, referring to FIG. 12, a thermal oxide film 27 is formed on the surface of semiconductor substrate 1 by a thermal oxidation method. A thickness of about 50 is formed on the thermal oxide film 27 by the CVD method.
A 0 ° nitride film 26 is formed.

Referring to FIG. 13, anisotropic etching is performed on nitride film 26 using a predetermined photoresist pattern (not shown) formed on nitride film 26 as a mask.
The region where the nitride films 26a and 26b exist is a region where a predetermined semiconductor element is formed in a later step.

Next, referring to FIG. 14, the region where the nitride film shown in FIG.
Is selectively formed. After that, the remaining nitride film is removed. Thus, a memory cell region A and a peripheral circuit region B which are electrically insulated by the element isolation insulating film 2 are formed on the surface of the semiconductor substrate 1.

Referring to FIG. 15, a silicon thermal oxide film 3 of about 90 ° is formed on semiconductor substrate 1 by a thermal oxidation method. 5 × 1 on the silicon thermal oxide film 3 by the CVD method.
A phosphorus-doped polysilicon film 5 of about 500 ° doped with about ²⁰ / cm ³ of phosphorus is formed. On the phosphorus-doped polysilicon film 5, about 500 °
Of tungsten silicide film 6 is formed. Thereafter, about 1 nm of the tungsten silicide film 6 is formed by CVD.
A silicon nitride film 7 of 000 ° is formed.

Referring to FIG. 16, anisotropic etching is performed on silicon nitride film 7 using a predetermined photoresist pattern (not shown) formed on silicon nitride film 7 shown in FIG. 15 as a mask. . Further, using the remaining silicon nitride film as a mask, the tungsten silicide film and the doped polysilicon film are anisotropically etched to form gate electrodes 9a to 9d including doped polysilicon films 5a to 5d and tungsten silicide films 6a to 6d. Are formed respectively. At this time, the gate length of the gate electrode is about 0.3 μm.
m. Thereafter, ion implantation is performed using the gate electrodes 9a to 9d and the element isolation oxide film 2 as a mask to obtain 1 × 10
Phosphorus ions of about ¹³ / cm ² are implanted into the silicon substrate 1. Thereby, shallow n ^- source / drain regions 4a to 4
4d is formed.

Next, referring to FIG.
A silicon nitride film 8 of about 800 ° is formed by CVD to cover 9d.

Next, referring to FIG. 18, using a fluorocarbon-based etching gas and a pressure of about 100 mTorr.
Under 1 Torr, the silicon nitride film 8 shown in FIG. Thereby, the gate electrode 9
Side walls 8a to 8d are formed on both side surfaces of a to 9d, respectively. At this time, the width of the side walls 8a to 8d is about 800 °.

Referring to FIG. 19, memory cell region A
After forming a photoresist pattern 28 covering the gate electrode 9, the gate electrode 9 d and the sidewall 8
5 × 10 ¹⁵ / c by ion implantation using d as a mask
Arsenic ions of about m ² are implanted. Thereby, n ⁺ source / drain regions 4e and 4f are formed. Note that, in the memory cell region A, in order to suppress a connection leak current from the storage node to the silicon substrate, n ⁺
No source / drain regions are formed.

Next, referring to FIG. 20, the photoresist pattern 28 shown in FIG. 19 is removed.

Next, referring to FIG. 21, gate electrodes 9a to 9a
A BPSG film of about 4000 ° is formed on the silicon substrate 1 by CVD to cover 9d. Thereafter, a heat treatment of about 850 ° C. is performed in a nitrogen atmosphere for about 20 minutes,
The surface of the BPSG film 15 is flattened. At this time, BPS
The distance from the surface of G film 15 to, for example, the surface of n ^- source / drain region 4a is about 6000 degrees.

Next, referring to FIG. 22, anisotropic etching is performed on BPSG film 15 using a predetermined photoresist pattern (not shown) formed on BPSG film 15 as a mask, and n ^- source / drain A bit line contact hole 13 exposing the surfaces of the regions 4a and 4c is formed.
Here, in the anisotropic etching, after the n ^- source / drain regions 4a and 4c are exposed, over-etching is performed for about 50% of the time required for just etching the BPSG film. The thickness of the BPSG film 15 is n ⁻ source / drain region 4a from its surface.
4c, which corresponds to the distance to the surface and is about 6000 °.
Therefore, including the time for over-etching, about 9
The BPSG film corresponding to Å is etched.

The height of the gate electrodes 9a and 9b including the silicon nitride films 7a and 7b is about 2000 °. Therefore, the surfaces near the edges of the silicon nitride films 7a and 7b are exposed when the BPSG film 15 is etched by about 4000 °. Thereafter, the remaining BPSG film of about 2000 ° is anisotropically etched to form n ⁻ source / drain regions 4a.
The surface of is exposed. After the surface of n ^- source / drain region 4a is exposed, over-etching is further performed.

During this time, the exposed silicon nitride films 7a and 7b and part of the side walls 8a and 8b are slightly etched. The time required for these etchings can be reduced from the time required to etch the BPSG film corresponding to about 9000 ° to the BPSG equivalent to about 4000 °.
This corresponds to a time obtained by subtracting the time required for etching the G film. That is, it corresponds to the time required to etch the BPSG film of about 5000 °. The etching rate of the silicon nitride films 7a and 7b is about 1/20 of the etching rate of the BPSG film. For this reason, BPSG
The silicon nitride films 7a and 7b are etched by about 250 ° while the film is etched by about 5000 °.

Next, referring to FIG. 23, a doped polysilicon film doped with phosphorus is formed on BPSG film 15 including the inside of bit line contact hole 13 by the CVD method. A tungsten silicide film is formed on the doped polysilicon film by a CVD method. Thereafter, the doped polysilicon film and the tungsten silicide film are anisotropically etched by a predetermined photoresist pattern (not shown) to form the bit lines 18. The bit line 18 is connected to the source / drain regions 4a, 4c. The line width of the bit line is about 0.3 μm.

Referring to FIG. 24, a silicon oxide film 20 is formed on BPSG film 15 by a CVD method so as to cover bit line 18.

Next, referring to FIG.
The silicon oxide film 20 and the BP are formed using a predetermined photoresist pattern (not shown) formed on
Anisotropic etching is performed on SG film 15 to form storage node contact hole 11 exposing the surface of n ⁻ source / drain region 4b. The opening diameter of the storage node contact hole 11 is about 0.3 μm.

Referring to FIG. 26, a doped polysilicon film doped with about 7000 ° of phosphorus is formed on silicon oxide film 20 including inside storage node contact hole 11 by the CVD method. Using a predetermined photoresist pattern (not shown) formed on the doped polysilicon film as a mask, the doped polysilicon film is anisotropically etched to form a storage node 21. Storage node 21 is electrically connected to n ⁻ source / drain region 4b via storage node columnar portion 21a formed in storage node contact hole 11.

Then, referring to FIG. 11, a silicon nitride film of about 60 ° is formed on silicon oxide film 20 by CVD method so as to cover storage node 21. On the silicon nitride film, a doped polysilicon film doped with about 1000 ° of phosphorus is formed by a CVD method. Anisotropic etching is performed on the doped polysilicon film using a predetermined photoresist pattern (not shown) formed on the doped polysilicon film as a mask. Thus, a capacitor 24 including a storage node 21, a capacitor insulating film 22 made of a silicon nitride film, and a cell plate 23 made of a doped polysilicon film is formed. Thus, the main part of the DRAM is completed.

[0027]

As described above, in the conventional manufacturing method, in the step shown in FIG. 18, the side walls 8a to 8d are formed on the respective side surfaces of the gate electrodes 9a to 9d.
In order to form d, anisotropic etching is performed on the entire surface of the silicon nitride film 8 formed in the step shown in FIG. At this time, even after the surfaces of the respective source / drain regions 4a to 4d are exposed, the source / drain regions 4a to 4d are exposed to a plasma atmosphere by over-etching, and crystal defects may enter the surfaces.

At this time, a problem such as a crystal defect existing at the end of the surface of n ^- source / drain region 4b located near the boundary of element isolation oxide film 2 becomes a problem. That is, since the storage node of the capacitor of the memory cell is electrically connected to n ⁻ source / drain region 4b as shown in FIG. May leak to the silicon substrate 1. As a result, there is a problem that the storage retention characteristics of the DRAM deteriorate.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device in which deterioration of storage retention characteristics is suppressed and, consequently, generation of leak current is suppressed. And

[0030]

A method of manufacturing a semiconductor device according to one aspect of the present invention includes the following steps. The first surface of the semiconductor substrate with an element isolation insulating film interposed
An area and a second area are formed. A first gate electrode is formed in a first region on the main surface with a gate insulating film interposed. A second gate electrode is formed in the second region on the main surface with a gate insulating film interposed. A pair of first source / drain regions is formed in the first region on the main surface with the first gate electrode interposed therebetween. A pair of second source / drain regions is formed in the second region on the main surface with the second gate electrode interposed therebetween. A first insulating film is formed on the semiconductor substrate so as to contact the side surfaces of the first and second gate electrodes and cover the first and second gate electrodes.
A first region including the first gate electrode is covered with a photoresist. Using the photoresist as a mask, the first insulating film is anisotropically etched to form sidewalls on both side surfaces of the second gate electrode. A first gate electrode covered with a first insulating film and a second gate electrode provided with sidewalls;
A second insulating film is formed over the semiconductor substrate so as to cover the gate electrode. The first source film is formed on the second insulating film and the first insulating film.
A contact hole exposing the surface of the drain region is formed. A conductive layer is formed in the contact hole.

According to this manufacturing method, the first region includes the M including the first gate electrode and the first source / drain region.
An OS transistor is formed. The second region includes a MOS including a second gate electrode and a second source / drain region.
A transistor is formed. When sidewalls are formed on both side surfaces of the second gate electrode, a photoresist is formed on the first insulating film located in the first region, and is not subjected to anisotropic etching. Therefore, the first source
No crystal defects or the like are generated on the surface of the drain region due to plasma accompanying the anisotropic overall etching.
This suppresses leakage of current from the conductive layer embedded in the contact hole exposing the surface of the first source / drain region to the semiconductor substrate via the first source / drain region. As a result, a semiconductor device in which leakage current can be reduced can be formed.

Preferably, the method further includes a step of forming a storage node on the second insulating film, and a step of forming a cell plate on the storage node with a capacitor insulating film interposed. Forming the storage node includes forming the conductive layer.

In this case, a memory cell including a capacitor and a MOS transistor is formed. The storage node of the capacitor is connected to the conductive layer. Therefore, the electric charge accumulated in the storage node is
Leakage from the drain region to the semiconductor substrate is suppressed. As a result, it is possible to obtain a semiconductor device in which deterioration of the memory retention characteristics is suppressed.

Preferably, the step of forming a contact hole includes the following steps. Utilizing a difference in etching characteristics between the first insulating film and the second insulating film, the second insulating film is etched while substantially leaving the first insulating film formed on the side surface and the upper surface of the first gate electrode. Then, the surface of the first insulating film located on the first source / drain region is exposed. The exposed first insulating film is subjected to anisotropic etching to expose the surface of the first source / drain region.

In this case, the second insulating film is etched without substantially etching the first insulating film in contact with the side surface of the first gate electrode, and the first insulating film located on the first source / drain region is etched. The surface of the film is exposed. Further, anisotropic etching is performed on the first insulating film to form a contact hole. As a result, a contact hole can be easily formed in a self-aligned manner.

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a DRAM as an example of a semiconductor device obtained by a method of manufacturing a semiconductor device according to the present invention.
Will be described with reference to the drawings. Referring to FIG. 1, a memory cell region A and a peripheral circuit region B which are electrically insulated by an element isolation oxide film 2 are formed on the surface of a semiconductor substrate 1. In the memory cell region A, gate electrodes 9a and 9b are formed on the semiconductor substrate 1 with gate insulating films 3a and 3b interposed therebetween. Gate electrode 9
Silicon nitride films 7a and 7b are formed on the upper surfaces of a and 9b, respectively. The silicon nitride film 8 covers the gate electrodes 9a and 9b and the silicon nitride films 7a and 7b.
Are formed.

A pair of n ^- source / drain regions 4a and 4b are formed in the semiconductor substrate 1 with the gate electrode 9b interposed therebetween. MOS transistor T1 is constituted by gate electrode 9b and a pair of n ^- source / drain regions 4a and 4b. BPSG film 15 having an etching characteristic different from that of silicon nitride film 8 so as to cover silicon nitride film 8.
Are formed. In the BPSG film 15 and the silicon nitride film 8, a bit line contact hole 13 exposing the surface of the n ^- source / drain region 4a is formed.

In the bit line contact hole 13,
A bit line 18 including a doped polysilicon film 17 and a tungsten silicide film 19 is formed. The silicon oxide film 2 is formed on the BPSG film 15 so as to cover the bit line 18.
0 is formed. In silicon oxide film 20, BPSG film 15 and silicon nitride film 8, storage node contact hole 11 exposing the surface of n ⁻ source / drain region 4b is formed.

On the silicon oxide film 20, a storage node 21 is formed. The storage node 21
The storage node pillar portion 21a embedded in the storage node contact hole 11 is electrically connected to the n ⁻ source / drain region 4b. The remaining structure is the same as that of the conventional semiconductor device shown in FIG. 11 described in the section of the related art, so that the same members are denoted by the same reference numerals and detailed description thereof will be omitted.

According to this structure, in the gate electrodes 9a and 9b in the memory cell area A, the silicon nitride film 8 is anisotropically etched as in the case of the gate electrode 9d in the peripheral circuit area B. Gate electrode 9
No process for forming sidewalls is performed only on both side surfaces of a and 9b. Therefore, the n ^- source / drain regions 4a and 4b are not subjected to plasma damage due to etching of the entire surface, and the occurrence of crystal defects on the surface is suppressed. In particular, in n ⁻ source / drain region 4 b located near the boundary with element isolation oxide film 2, charge leakage from storage node 21 to semiconductor substrate 1 via n ⁻ source / drain region 4 b is suppressed. You.
As a result, the storage retention characteristics of the DRAM are improved.

Next, a method of manufacturing the above-described DRAM will be described as an example of a method of manufacturing the semiconductor device according to the embodiment of the present invention. After going through the steps shown in FIGS. 12 to 17 described in the section of the prior art, with reference to FIG.
A photoresist pattern 28 is formed on the memory cell area A. Using the photoresist pattern 28 as a mask, the silicon nitride film is subjected to anisotropic etching to form sidewalls 8d on both sides of the silicon nitride film 7d and the gate electrode 9d. Thereafter, arsenic ions of about 5 × 10 ¹⁵ / cm ² are implanted by ion implantation using the element isolation oxide film 2, the silicon nitride film 7d and the side walls 8d as a mask. Thereby, the n ⁺ source / drain region 4
e, 4f are formed.

In the memory cell region A, n ⁺ source / drain regions are not formed for the purpose of suppressing a connection leak current from the storage node to the silicon substrate, as described in the section of the prior art.

Next, referring to FIG. 3, the photoresist pattern 28 shown in FIG. 2 is removed. Next, referring to FIG.
On the silicon substrate 1 so as to cover the silicon nitride film 8 and the like,
A BPSG film 15 of about 4000 ° is formed by the CVD method. Thereafter, a heat treatment at about 850 ° C. in a nitrogen atmosphere is performed for about 2 hours.
By applying for 0 minutes, the surface of the BPSG film 15 is flattened.

Next, referring to FIG.
Predetermined photoresist pattern formed (not shown)
BPSG film is anisotropically etched using
Then n ^-Silicon located on source / drain region 4a
The surface of the nitride film 8 is exposed. At this time,
Pressure of about 100mTorr ~ 1To using Bon-based gas
It is desirable to perform etching under the range of rr. Also,
The end point is preferably controlled by the etching time.

In this case, the etching selectivity between the BPSG film 15 and the silicon nitride film 8 is large, and the BPSG film is etched while substantially leaving the silicon nitride film.

Referring to FIG. 6, silicon nitride film 8 located on n ^- source / drain region 4a is anisotropically etched to expose the surface of n ^- source / drain region 4a. At this time, a fluorocarbon-based gas containing CHF ₃ is used and the pressure is about 100 mTorr to 1 Torr.
It is desirable to etch under the range of. By these etchings, bit line contact holes 13 are formed in a self-aligned manner.

The silicon nitride film 8 at the upper end of the gate electrodes 9a and 9b is etched by about 250 ° in the same manner as described in the step shown in FIG.

Next, referring to FIG. 7, a doped polysilicon film doped with phosphorus is formed on BPSG film 15 including the inside of bit line contact hole 13 by the CVD method.
A tungsten silicide film is formed on the doped polysilicon film by a CVD method. Thereafter, the doped polysilicon film and the tungsten silicide film are anisotropically etched by a predetermined photoresist pattern (not shown) to form the bit lines 18.

Next, referring to FIG. 8, a silicon oxide film 20 is formed on BPSG film 15 by a CVD method so as to cover bit line 18.

Next, referring to FIG.
Using a predetermined photoresist pattern (not shown) formed thereon as a mask, silicon oxide film 20 and BPS
The G film 15 is subjected to anisotropic etching using a fluorocarbon-based gas to expose the surface of the silicon nitride film 8.
Subsequently, the silicon nitride film 8 is subjected to anisotropic etching using a fluorocarbon-based gas containing CHF ₃ , and n
^- exposing the surface of the source-drain region 4b. Thereby, a storage node contact hole 11 is formed. The pressure during the etching was about 10
A range of 0 mTorr to 1 Torr is desirable.

At this time, if the photoresist pattern for forming the storage node contact hole is temporarily
Even if it is formed shifted to the gate electrode 9b side, the storage node contact hole is formed while substantially leaving the silicon nitride film in contact with the side surface of the gate electrode 9b.

Next, referring to FIG. 10, on the silicon oxide film 20 including the inside of the storage node contact hole 11, a doped polysilicon film doped with about 7000 ° of phosphorus is formed by the CVD method. Using a predetermined photoresist pattern (not shown) formed on the doped polysilicon film as a mask, the doped polysilicon film is anisotropically etched to form a storage node 21. This storage node 21 is electrically connected to n ⁻ source / drain region 4b via storage node columnar portion 21a formed in storage node contact hole 11.

Thereafter, as described in the section of the prior art, a cell plate is formed on storage node 21 with a capacitor insulating film interposed. Thus, the DRAM shown in FIG. 1 is completed.

According to this manufacturing method, in particular, in forming the side wall 8d of the gate electrode 9d in the peripheral circuit region B in the step shown in FIG. Has a photoresist pattern formed thereon. Therefore, the silicon nitride film 8 located in the memory cell region A is not subjected to anisotropic etching. Thereby, the source / drain regions 4a, 4b
No crystal defects or the like are generated on the surface of the substrate by plasma accompanying the anisotropic overall etching. As a result, in particular, charge is prevented from leaking from the source / drain region 4b to which the storage node is connected to the silicon substrate, and deterioration of the memory retention characteristics of the DRAM is suppressed.

The silicon nitride film 8 covering the gate electrode
And the BPSG film 1 formed on the silicon nitride film 8
5, the BPSG film 1 is substantially etched without etching the silicon nitride film 8.
5 can be etched, and a bit line contact hole can be formed in a self-aligned manner.

In the above embodiment, an example in which the storage node is connected to the source / drain region has been described. However, the present invention is not limited to the storage node, and other conductive layers may be used. A semiconductor device in which the reduction of the number of pixels can be achieved can be formed.

In this case, a silicon nitride film and BPSG
Although a film is taken as an example, the film is not limited to these films as long as the film has a large etching selectivity.

It should be noted that the embodiments disclosed this time are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the range described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0059]

According to the method of manufacturing a semiconductor device according to one aspect of the present invention, a MOS transistor including a first gate electrode and a first source / drain region is formed in a first region. In the second region, a MOS transistor including a second gate electrode and a second source / drain region is formed. When sidewalls are formed on both side surfaces of the second gate electrode, a photoresist is formed on the first insulating film located in the first region, and is not subjected to anisotropic etching. Therefore, crystal defects and the like do not occur on the surface of the first source / drain region due to plasma accompanying the anisotropic overall etching. This allows
Leakage of current from the conductive layer embedded in the contact hole exposing the surface of the first source / drain region to the semiconductor substrate via the first source / drain region is suppressed. As a result, a semiconductor device in which leakage current can be reduced can be formed.

Preferably, the method further includes a step of forming a storage node on the second insulating film, and a step of forming a cell plate on the storage node with a capacitor insulating film interposed. Forming the storage node includes forming the conductive layer.

In this case, a memory cell including a capacitor and a MOS transistor is formed. The storage node of the capacitor is connected to the conductive layer. Therefore, the electric charge accumulated in the storage node is
Leakage from the drain region to the semiconductor substrate is suppressed. As a result, it is possible to obtain a semiconductor device in which deterioration of the memory retention characteristics is suppressed.

Preferably, the step of forming a contact hole includes the following steps. Utilizing a difference in etching characteristics between the first insulating film and the second insulating film, the second insulating film is etched while substantially leaving the first insulating film formed on the side surface and the upper surface of the first gate electrode. Then, the surface of the first insulating film located on the first source / drain region is exposed. The exposed first insulating film is subjected to anisotropic etching to expose the surface of the first source / drain region.

In this case, the second insulating film is etched without substantially etching the first insulating film in contact with the side surface of the first gate electrode, and the first insulating film located on the first source / drain region is etched. The surface of the film is exposed. Further, anisotropic etching is performed on the first insulating film to form a contact hole. As a result, a contact hole can be easily formed in a self-aligned manner.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device obtained by a method of manufacturing a semiconductor device according to the present invention.

FIG. 2 is a sectional view showing one step of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a step performed after the step shown in FIG. 2 in the embodiment.

FIG. 4 is a cross-sectional view showing a step performed after the step shown in FIG. 3 in the embodiment.

FIG. 5 is a cross-sectional view showing a step performed after the step shown in FIG. 4 in the embodiment.

FIG. 6 is a cross-sectional view showing a step performed after the step shown in FIG. 5 in the embodiment.

FIG. 7 is a cross-sectional view showing a step performed after the step shown in FIG. 6 in the embodiment.

FIG. 8 is a cross-sectional view showing a step performed after the step shown in FIG. 7 in the embodiment.

FIG. 9 is a cross-sectional view showing a step performed after the step shown in FIG. 8 in the embodiment.

FIG. 10 is a cross-sectional view showing a step performed after the step shown in FIG. 9 in the embodiment.

FIG. 11 is a cross-sectional view of a conventional semiconductor device.

FIG. 12 is a cross-sectional view showing one step of a conventional method for manufacturing a semiconductor device.

13 is a cross-sectional view showing a step performed after the step shown in FIG.

FIG. 14 is a cross-sectional view showing a step performed after the step shown in FIG.

15 is a cross-sectional view showing a step performed after the step shown in FIG.

16 is a cross-sectional view showing a step performed after the step shown in FIG.

FIG. 17 is a cross-sectional view showing a step performed after the step shown in FIG.

18 is a cross-sectional view showing a step performed after the step shown in FIG.

FIG. 19 is a cross-sectional view showing a step performed after the step shown in FIG.

20 is a cross-sectional view showing a step performed after the step shown in FIG.

21 is a cross-sectional view showing a step performed after the step shown in FIG.

FIG. 22 is a cross-sectional view showing a step performed after the step shown in FIG. 21.

FIG. 23 is a cross-sectional view showing a step performed after the step shown in FIG. 22.

FIG. 24 is a cross sectional view showing a step performed after the step shown in FIG. 23.

FIG. 25 is a cross-sectional view showing a step performed after the step shown in FIG. 24.

FIG. 26 is a cross-sectional view showing a step performed after the step shown in FIG. 25.

[Explanation of symbols]

1 silicon substrate, 2 element isolation oxide films, 3a, 3b,
3c gate insulating film, 4 a to 4 d n ^- source and drain regions, 8 silicon nitride film, 9a to 9d gate electrode, 11 a storage node contact hole, 13
Bit line contact hole, 15 BPSG film, 18
Bit line, 20 silicon oxide film, 21 storage node, 22 capacitor insulating film, 23 cell plate, 2
4 Capacitor.

Claims (3)

[Claims] Forming a first region and a second region on a main surface of a semiconductor substrate with an element isolation insulating film interposed therebetween; and forming a first region on the main surface with a gate insulating film interposed therebetween. Forming a first gate electrode; forming a second gate electrode in the second region of the main surface with a gate insulating film interposed; interposing the first gate electrode; Forming a pair of first source / drain regions in a first region; and forming a pair of second source / drain regions in the second region on the main surface with the second gate electrode interposed therebetween. Forming a first insulating film on the semiconductor substrate so as to cover the first and second gate electrodes in contact with side surfaces of the first and second gate electrodes; Covering the first region with a photoresist Using the photoresist as a mask, performing anisotropic etching on the first insulating film to form sidewalls on both side surfaces of the second gate electrode; and forming the first insulating film covered with the first insulating film. Forming a second insulating film on the semiconductor substrate so as to cover a second gate electrode provided with a gate electrode and a sidewall; and forming the first source film on the second insulating film and the first insulating film. A method of manufacturing a semiconductor device, comprising: a step of forming a contact hole exposing a surface of a drain region; and a step of forming a conductive layer in the contact hole. 2. The method according to claim 1, further comprising: forming a storage node on the second insulating film; and forming a cell plate on the storage node with a capacitor insulating film interposed. The method according to claim 1, further comprising forming the conductive layer. 3. The step of forming the contact hole is formed on a side surface and an upper surface of the first gate electrode by utilizing a difference in etching characteristics between the first insulating film and the second insulating film. Etching the second insulating film while substantially leaving the first insulating film to expose a surface of the first insulating film located on the first source / drain region; 3. The method of manufacturing a semiconductor device according to claim 1, further comprising: performing anisotropic etching on the first insulating film to expose a surface of the first source / drain region.