JPH10301910A - Data transfer device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data transfer device capable of scalably extending hardware while depending on the number of controllers and maintaining transfer performance without depending on the number of controllers to be connected. SOLUTION: A network connection device connected to various connectors is constituted of plural pass connection parts 7c each of which includes a transmitting pass checking circuit 6c for checking a transfer pass, a transmitting buffer 4c for storing output data, a receiving matching circuit 5c for entering input data, and a receiving buffer 3c for storing input data, a selector for selecting the input data of the buffers 3c, and a distribution circuit 2c for transferring the output data of the buffers 4c and connected to plural loop type transfer passes capable of transferring data only to one direction. Thus output data are transferred to a sending destination through the shortest transfer pass, and when the shortest transfer pass is busy, the data are successively transferred to a nearer transfer pass.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device, and more particularly, to a data transfer device for performing high-speed transfer between a plurality of control devices.

[0002]

2. Description of the Related Art A conventional general data transfer apparatus will be described. FIG. 12 is a block diagram showing a conventional data transfer device. Referring to FIG. 12, this data transfer device includes CPU-side bus connection devices # 0 to #m [5a] to [8a].
a] and memory-side bus connection devices # 0 to #n [11a] to
[14a] and CPU-side bus connection devices # 0 to #m [5
a] to [8a] and memory-side bus connection devices # 0 to #n
A contention arbitration unit [10a] for performing contention arbitration of transfer data from [11a] to [14a], and a CPU-side bus connection device #
A bus [9a] for transferring transfer data from 0 to #m [5a] to [8a] and memory-side bus connection devices # 0 to #n [11a] to [14a], and paths [101a] to [13]
3a], CPUs # 0 to #m [1a] to [4a], and memories # 0 to #n [15a] to [18a].

Next, the operation of this conventional technique will be described. A load request (hereinafter referred to as RQ01) is issued from the CPU # 0 [1a] to the memory # 0 [15a], and a load request (hereinafter referred to as RQ11) is issued from the CPU # 1 [2a] to the memory # 0 [15a]. The following describes the case where Thereafter, the CPU # 1 [2a] sends the memory # 1
A load request (hereinafter RQ12) to [16a] is issued. Also, if requests conflict at the same time, C
It is assumed that the priority is higher in ascending order of the PU device number and the memory device number. It is also assumed that the CPU and the memory have a higher priority on the memory.

RQ0 issued from CPU # 0 [1a]
1 is transferred to the CPU-side bus connection device # 0 [5a] via the path [101a]. At the same time, CPU # 1 [2
RQ11 issued from [a] is transferred to the CPU-side bus connection device # 1 [6a] via the path [103a].
Next, RQ01 and RQ11 notify the contention arbitration unit [10a] via the path [133a] whether or not transmission is possible.

Next, in the contention arbitration unit [10a], RQ01 is selected from the priority order, and RQ01 is set to the path [10].
9a], the bus [9a], and the path [117].
a] and transferred to the memory-side bus connection device # 0 [11a].

Next, RQ01 accesses memory # 0 [15a] via path [125a], and the load data (hereinafter DT01) is read. In addition, the RQ11 lost in the competition is selected in the competition arbitration unit [10a],
The RQ 11 is transferred to the memory-side bus connection device # 0 [11a] via the bus [9a] via the path [111a] and via the path [117a]. At the same time, CPU # 1
The RQ12 issued from [2a] is transferred to the CPU-side bus connection device # 1 [6a] via the path [103a].

Next, DT01 is transferred to the memory side bus connection device # 0 [11a] via the path [126a]. Also, the RQ 11 accesses the memory # 0 [15a] via the path [125a], and loads the load data (hereinafter referred to as D
T11) is read. At the same time, RQ12 sets path [1
33a] to the contention arbitration unit [10a] as to whether transmission is possible.

Next, in the contention arbitration unit [10a], RQ
12 is selected, and the RQ 12 is transferred to the memory-side bus connection device # 1 [12a] via the bus [9a] via the path [111a] and via the path [119a]. At the same time, DT01 notifies the contention arbitration unit [10a] via the path [133a] whether or not transmission is possible.

Next, in the competition arbitration unit [10a], DT
01 is selected, and DT01 is transferred to the CPU-side bus connection device # 0 [5a] via the path [118a], via the bus [9a], and via the path [110a]. Also, the DT 11 notifies the contention arbitration unit [10a] via the path [133a] whether or not transmission is possible. At the same time, R
Q12 is stored in memory # 1 [16] via path [127a].
a], and the load data (hereinafter referred to as DT12) is read.

Next, DT01 is transferred to CPU # 0 [1a] via path [102a], and a series of operations is completed. Also, the DT11 is selected in the contention arbitration unit [10a], and the DT11 is transmitted via the bus [9a] via the path [118a] and the CPU via the path [112a].
The data is transferred to the side bus connection device # 1 [6a]. At the same time, D
T12 is transferred to the memory-side bus connection device # 1 [12a] via the path [128a].

Next, the DT 11 is transferred to the CPU # 1 [2a] via the path [104a], and a series of operations is completed. At the same time, the DT 12 notifies the contention arbitration unit [10a] via the path [133a] whether or not transmission is possible.

Next, in the contention arbitration unit [10a], DT
12 is selected, and the DT 12 is transferred to the CPU-side bus connection device # 1 [6a] via the path [120a], via the bus [9a], and via the path [112a].

Finally, the DT 12 is transferred to the CPU # 1 [2a] via the path [104a], and a series of operations is completed.

Next, a description will be given of a conventional data transfer device having a crossbar typified by the technique described in Japanese Patent Laid-Open No. 7-38596. FIG. 13 is a block diagram showing a conventional data transfer device. Referring to FIG. 13, this data transfer device includes CPU-side crossbar connection devices # 0 to #m [5b] to [8b], memory-side crossbar connection devices # 0 to #n [13b] to [16b], CPU-side crossbar connection devices # 0 to #m [5b] to [8b] Memory-side crossbar connection devices # 0 to #n [13b] to [16b]
Crossbar control unit [9]
b] and the results of the competition arbitration of the crossbar control unit [9b], the CPU-side crossbar connection devices # 0 to #m [5b] to
From [8b], the memory-side crossbar connection devices # 0 to #n [1
3b] to [16b] to perform data transfer.
0b] and the memory-side crossbar connection devices # 0 to #n [13
b] to [16b] to the CPU-side crossbar connection devices # 0 to
#M [5b] to [8b], a crossbar control unit [12b] that performs contention arbitration of transfer data, and a crossbar control unit [12b].
b], the plurality of memory-side crossbar connection devices # 0 to #n [13b] to [16b] are converted from the plurality of CPU-side crossconnection devices # 0 to #m [5b] to
A crossbar [11b] for transferring data to [8b];
Paths [101b] to [134b] and CPUs # 0 to #m
[1b] to [4b] and memories # 0 to #n [17b] to
[20b].

Next, the operation of the conventional technique will be described. A load request (hereinafter RQ01) is issued from CPU # 0 [1b] to memory # 0 [17b], and a load request (hereinafter RQ11) is issued from CPU # 1 [2b] to memory # 0 [17b]. The following describes the case where

Thereafter, the CPU # 1 [2b] sends the memory # 1
It is assumed that a load request (hereinafter RQ12) to [18b] has been issued. At the same time, when requests conflict, the priority is assumed to be higher in ascending order of the device number of the CPU and the device number of the memory.

RQ0 issued from CPU # 0 [1b]
1 is transferred to the CPU-side crossbar connection device # 0 [5b] via the path [101b]. At the same time, CPU # 1
The RQ 11 issued from [2b] is transferred to the CPU side crossbar connection device # 1 [6b] via the path [103b].

Next, RQ01 is transmitted from the CPU-side crossbar connection device # 0 [5b] via the path [109b] to m × n.
Is transferred to the crossbar [10b], and at the same time, RQ11 is also
Path [111] from U-side crossbar connection device # 1 [6b]
b] to the m × n crossbar [10b]. RQ12 issued from CPU # 1 [2b]
Is transferred to the CPU-side crossbar connection device # 1 [6b] via the path [103b].

Next, the access information of RQ01 and RQ11 is transmitted via the path [133b] to the crossbar control unit [9b].
Is forwarded to Contention occurs because RQ01 and RQ11 access the same memory, RQ01 is selected from the priority order, and the contention arbitration result is transferred to the m × n crossbar [10b] via the path [133b]. As a result RQ
01 is transferred to the memory-side crossbar connection device # 0 [13b] via the path [117b]. At the same time, RQ12
Is the path [1] from the CPU-side crossbar connection device # 1 [6b].
11b] to the m × n crossbar [10b].

Next, RQ01 accesses memory # 0 [17b] via path [125b], and the load data (hereinafter DT01) is read. In addition, the contention arbitration result of the RQ11 lost in the contention is transferred to the m × n crossbar [10b] via the path [133b]. As a result RQ
11 is transferred to the memory-side crossbar connection device # 0 [13b] via the path [117b]. Originally, at this timing, the RQ12 should have been transferred to the memory side crossbar connection device # 1 [14b] via the path [119b]. I will.

Next, DT01 is transferred to the memory side crossbar connection device # 0 [13b] via the path [126b]. The RQ 11 accesses the memory # 0 [17b] via the path [125b], and the load data (hereinafter, DT11) is read. At the same time, the access information of the RQ 12 is transferred to the crossbar control unit [9b] via the path [133b]. Since no conflict occurs, RQ1
2 is selected, and the contention arbitration result is transferred to the m × n crossbar [10b] via the path [133b]. As a result, the RQ12 is transferred to the memory-side crossbar connection device # 1 [14b] via the path [119b].

Next, DT01 is transferred to the n × m crossbar [11b] via the path [118b]. Also, D
T11 is transferred to the memory-side crossbar connection device # 0 [13b] via the path [126b]. At the same time, RQ1
2 is memory # 1 [18b] via path [127b]
And the load data (hereinafter, DT12) is read.

Next, the access information of DT01 is changed to the path [1].
34b] to the crossbar controller [12b]. Since no conflict occurs, DT01 is selected, and the conflict arbitration result is transferred to the n × m crossbar [11b] via the path [134b]. As a result, DT01 is connected to the CPU-side crossbar connection device # 0 via the path [110b]
Transferred to [5b]. Also, DT11 passes the path [118
b] to the n × m crossbar [11b]. At the same time, the DT 12 is transferred to the memory-side crossbar connection device # 1 [14b] via the path [128b].

Next, DT01 is transferred to CPU # 0 [1b] via path [102b], and a series of operations is completed. Also, the access information of DT11 is the path [134b].
Is transferred to the crossbar control unit [12b] via. Since no conflict occurs, DT11 is selected, and the result of the conflict arbitration is sent to the nxm crossbar [11] via the path [134b].
b]. As a result, the DT11 passes the path [112].
b] via the CPU side crossbar connection device # 1 [6b]
Is forwarded to At the same time, the DT 12 is transferred to the n × m crossbar [11b] via the path [120b].

Next, the DT 11 is transferred to the CPU # 1 [2b] via the path [104b], and a series of operations is completed. At the same time, the access information of DT12 is
b] to the crossbar controller [12b]. Since no contention occurs, DT12 is selected, and the contention arbitration result is transferred to the n × m crossbar [11b] via the path [134b]. As a result, the path DT12 becomes the path [1
12b] and the CPU-side crossbar connection device # 1 [6]
b].

Finally, the DT 12 is transferred to the CPU # 1 [2b] via the path [104b], and a series of operations is completed.

[0027]

A first problem of the above-mentioned prior art is that, in the bus connection technique, the transfer capacity decreases in inverse proportion to the number of control devices to be connected. The reason is that at a certain timing, only one control device can be given a transfer permission.

The second problem is that in the technique of crossbar connection, the cost of hardware increases when the number of control devices to be connected is different. The reason is that the development cost increases when the crossbar is developed according to the number of connected control devices. Further, when only the crossbar having the maximum configuration is developed and adapted to a configuration smaller than the maximum configuration, the hardware becomes redundant and the manufacturing cost of the hardware increases.

An object of the present invention is to provide a data transfer device which can expand the hardware scalably depending on the number of control devices to be connected and which does not reduce the transfer performance regardless of the number of control devices to be connected. is there.

[0030]

A first data transfer device according to the present invention is a data transfer device including a plurality of various control devices represented by a CPU and a memory, a transfer path, and a network connection device. The network connection device checks whether the transfer path is available when transmitting transfer data from the various control devices, and determines whether the shortest transfer path to the various control devices at the destination or the various When the transfer path of the shortest distance to the control device is in use, the transmission path check circuit connected to the next closest transfer path, and the transfer data transmitted from the various control devices to the transmission path check circuit. The transmission buffer to be held, when the transfer data from the transfer path is received, it is determined whether the transfer data is the transfer data to the various control devices. A plurality of path connection units having a reception matching circuit that captures the transfer data based on the data, a reception buffer that holds the transfer data from the reception matching circuit, and the various control devices from the reception buffer. A first selection circuit for selecting the transfer data and transferring the transfer data to the various control devices; and a distribution circuit for transferring the transfer data from the various control circuits to the transmission buffer.

A second data transfer device according to the present invention is the first data transfer device, wherein the plurality of loop-type transfer paths are transfer paths that sequentially connect the network connection devices in series at the shortest distance; And a plurality of the path connection units corresponding to the loop-type transfer paths connected to the respective loop-type transfer paths in the network connection device.

A third data transfer device according to the present invention is the second data transfer device, wherein when the transfer data is not transferred over the shortest distance between the network connection devices, The receiving matching circuit for determining whether to transfer the transfer data back to the path of the closer loop-type transfer path and capturing the output data, and the network connection device, wherein the various control devices A second selection circuit for selecting one of the transfer data from the network and the transfer data transferred between the network connection devices, and transmitting the transfer data from the reception matching circuit to the second selection circuit And a folding circuit.

A fourth data transfer device of the present invention is the first, second, or third data transfer device, wherein
Connection between the first selection circuit of the network connection device and the distribution circuit of the second network connection device, and the distribution circuit and the second network connection of the first network connection device And a connection between the first selection circuits of the device, and transfers the transfer data between the first network connection device and the second network connection device.

[Operation] Since the network connection device having the above configuration uses a plurality of loop transfer paths as data transfer paths, if one loop transfer path is in a busy state, another loop transfer path is connected. It can be used to transfer to various control devices. Further, unlike the bus connection, a plurality of data transfers can be performed at the same timing. Also,
Unlike crossbar connection, hardware and transfer performance can be changed in a scalable manner.

[0035]

Next, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the present invention. Referring to FIG. 1, according to a first embodiment of the present invention, a transmission path check circuit [6c] for checking whether a transfer path is available when transmitting output data from various control devices, and various control devices. A transmission buffer [4c] for holding output data to be transmitted to the transmission path check circuit [6c] from the controller, and determine whether or not transfer data from another control device is input data to the own control device upon reception, and A matching circuit for receiving [5c] to be input to the own network connection device in the case of input data to the own control device, and a receiving buffer [3c] for holding the input data to the own control device from the matching circuit for receiving [5c] ], A plurality of path connection units [7c] having a plurality of path connection units [7c]. A selector [1c] for selecting input data to the control device and transferring the data to various control devices, and transferring output data from the various control devices to a transfer path of the shortest distance to the destination control device or a destination control device; On the other hand, if the shortest distance transfer path is in use, it is connected to a sequentially closer transfer path,
This is a data transfer device connected by a network connection device having a transmission path check circuit [6c] in the path connection unit [7c] or a distribution circuit [2c] for transferring to the transmission buffer [4c]. The inside is connected by paths [101c] to [106c].

Next, the operation of the first embodiment of the present invention will be described. First, an operation of processing input data will be described. First, one or more path connection parts [7c]
, The reception matching circuit [5c] determines whether the data is input data to the own control device.

Next, if the input data is not input data to the own control device, or if the input data is input data to the own control device but the receiving buffer [3c] is busy, the transmission path check is performed. It is sent to the transfer path through the circuit [6c]. If the input data is input data to the own control device and the receiving buffer [3c] is not busy, the following operation is performed. Receive buffer [3
If the input data exists in [c], the input data is transferred to the reception buffer [3c] through the path [105c]. If there is no input data in the receiving buffer [3c], the following operation is performed. Selector [1
c], the reception buffer [3c] in one or a plurality of path connection units [7c] is searched, and if there is no input data in the reception buffer [3c], the reception matching circuit [5c] is searched. A search is performed, and input data having a higher priority is selected through a route [103c].
c] to the read path of the own control device. Here, the input data not selected by the reception matching circuit [5c] is routed to the reception buffer [3c] via the path [105].
c].

Next, the operation of processing the output data will be described. First, output data is transferred to the distribution circuit [2c] from the write path [102c] of the own control device.

Next, in the distribution circuit [2c], the transmission buffer [4] in the path connection unit [7c] to be transferred is set.
c], and when the transmission buffer [4c] is not busy, the path connection unit [7c] connected to the shortest distance transfer path to the destination of the output data,
The data is transferred to the transmission buffer [4c] and the transmission path check circuit [6c] through the path [104c] by the following operation. Further, a path connection unit [7] connected to the transfer path of the shortest distance to the transmission destination of the transmission buffer [4c].
c], when the transmission buffer [4c] is busy, the transmission buffer [4c] and the transmission buffer [4c] in the path connection unit [7c] connected to the transfer path closest to the shortest distance transfer path. A path [104] to a closer transfer path that can be sequentially transferred to the path check circuit [6c].
c], the data is transferred by the following operation. Further, the transmission buffer [4] in all the path connection units [7c].
If [c] is busy, it notifies the own control device of busy, and suppresses output from the write path [102c].

Next, the transmission path check circuit [6c] determines whether the transfer path is busy. When busy, when the output data goes to the transfer path to be transferred to the distribution circuit [2c], the data is transferred from the distribution circuit [2c] to the transmission buffer [4c] through the path [104c]. If not busy, if there is output data in the transmission buffer [4c], there is no output data in the transmission buffer [4c] from the transmission buffer [4c].
When the output data from the distribution circuit [2c] goes to the transfer path to be transferred, the data is transferred from the distribution circuit [2c] to the transmission path check circuit [6c] through the path [106c] and sent out to the transfer path. . In the case where the data is transferred from the transmission buffer [4c] to the transmission path check circuit [6c] and the output data from the distribution circuit [2c] is directed to the transfer path to be transferred, the output data is transmitted to the distribution circuit. The data is transferred from [2c] to the transmission buffer [4c] through the path [104c].

Here, the receiving matching circuit [5c],
The path connection unit [7c] in the network connection device including the reception buffer [3c], the transmission buffer [4c], and the transmission path check circuit [6c] can be scalably increased or decreased according to the connection configuration.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram showing a second embodiment of the present invention. Referring to FIG.
# 0 to #m [1d] to [4d] are arithmetic units and memories # 0 to
#N [17d] to [20d] are main memories. CPU-side network connection devices # 0 to #m [5d] to [8d]
Are the CPUs # 0 to #m [1d] to [4d], respectively.
, And controls input data from the transfer path and output data to the transfer path.

Similarly, the memory-side network connection device #
0 [13d] to the memory-side network connection device #n [1
6d] are memory # 0 [17d] to memory #n, respectively.
It is connected to the main memory of [20d] and controls input data from the transfer path and output data to the transfer path.

Loop type transfer paths # 1- # L [9d]-
[12d] is the CPU-side network connection device # 0 [5
d] to CPU-side network connection device #m [8d] and memory-side network connection devices # 0 to #n [13]
[d] to [16d] are connected by the following connection method.

In FIG. 2, connections similar to those in the crossbar configuration are made. CPU side network connection device # 0
[5d] is the memory-side network connection device # 0 to #n
[13d] to [16d] are all connected at the shortest distance. Similarly, CPU-side network connection devices # 1 to #m
Each of [6d] to [8d] is also connected to the memory-side network connection devices # 0 to #n [13d] to [16d] with the shortest distance.

As an example of connection, a case where the number of CPUs is 4 and the number of memories is 4 (n, m = 3), that is, CPU-side network connection devices # 0 to # 3 (hereinafter, CP # to CP)
# 3), a connection method of the memory-side network connection devices # 0 to # 3 (hereinafter, MM # 0 to MM # 3) will be described.

In order to make the same connection as in the crossbar configuration, CP # 0 is CP # 0 → MM # 0, CP # 0 → MM
# 1, CP # 0 → MM # 2, CP # 0 → MM # 3, CP
# 1 is CP # 1 → MM # 0, CP # 1 → MM # 1, C
P # 1 → MM # 2, CP # 1 → MM # 3, CP # 2
CP # 2 → MM # 0, CP # 2 → MM # 1, CP # 2 →
MM # 2, CP # 2 → MM # 3, CP # 3 is CP # 3
→ MM # 0, CP # 3 → MM # 1, CP # 3 → MM #
2, CP # 3 → MM # 3, MM # 0 is MM # 0 → CP
# 0, MM # 0 → CP # 1, MM # 0 → CP # 2, MM
# 0 → CP # 3, MM # 1 is MM # 1 → CP # 0, M
M # 1 → CP # 1, MM # 1 → CP # 2, MM # 1 → C
P # 3 and MM # 2 are MM # 2 → CP # 0, MM # 2 →
CP # 1, MM # 2 → CP # 2, MM # 2 → CP # 3,
MM # 3 is MM # 3 → CP # 0, MM # 3 → CP #
1, the shortest transfer path of MM # 3 → CP # 2, MM # 3 → CP # 3 is required.

By rearranging these and creating a plurality of loop transfer paths, loop type transfer path # 1: CP # 0 → MM # 3 → CP # 3
→ MM # 2 → CP # 2 → MM # 1 → CP # 1 → MM # 0
→ CP # 0, loop type transfer path # 2: CP # 0 → MM # 2 → CP # 1
→ MM # 3 → CP # 2 → MM # 0 → CP # 3 → MM # 1
→ CP # 0, loop type transfer path # 3: CP # 0 → MM # 1 → CP # 3
→ MM # 0 → CP # 2 → MM # 3 → CP # 1 → MM # 2
→ CP # 0, Loop type transfer path # 4: CP # 0 → MM # 0 → CP # 1
→ MM # 1 → CP # 2 → MM # 2 → CP # 3 → MM # 3
→ CP # 0, which is connected by L = 4 loop-type transfer paths, and can perform the same connection as the crossbar configuration.

When the shortest distance loop-type transfer path is busy, the transfer is performed by the next closest loop-type transfer path, so that a decrease in performance due to output busy in various control devices can be reduced.

Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a block diagram showing a third embodiment of the present invention. Referring to FIG. 3, a third embodiment of the present invention provides a transmission path check circuit [8e] for checking whether a transfer path is available when transmitting output data from the various control devices, A transmission buffer [6e] for holding output data to be transmitted from the control device to the transmission path check circuit [8e], and whether or not transfer data from another control device is input data to the own control device upon reception is determined. Further, in the case of input data to the own control device, it is taken into the own network connection device, and when the transfer data between the other network connection devices is not transferred over the shortest distance, the transfer data between the other network connection devices is Judge whether to forward the data to the transfer path closer to the nearest transfer path. Incorporated into the over-click connection device, receiving matching circuit [7e]
And a plurality of path connection units [9e] each having a reception buffer [5e] for holding input data from the reception matching circuit [7e] to the own control device. A selector [3e] for selecting input data from the reception matching circuit [7e] or the reception buffer [5e] to the own control device and transferring the data to the various control devices; ,
A path connection unit [9e] that is connected to a transfer path that is the shortest distance to the destination control device or a transfer path that is shortest to the destination control device when the shortest distance is being used. Distribution path check circuit [8e] or distribution circuit [4] for transfer to transmission buffer [6e]
e], a selector [2e] for selecting output data from the own control device or transfer data between the other network connection devices, and transfer data between the other network connection devices from the reception matching circuit [7e]. Selector [2
e] is a data transfer device connected by a network connection device having a loopback circuit [1e] for transmission to the data transfer device. The inside is connected by paths [101e] to [109e].

Next, the operation of the third embodiment of the present invention will be described. First, an operation of processing input data will be described. First, one or more path connection units [9e]
In the above, the reception matching circuit [7e] determines whether or not the data is input data to the own control device.

Next, if the input data is not input data to the own control device, or if the input data is input data to the own control device but the receiving buffer [5e] is busy, the transmission path check is performed. It is sent to the transfer path through the circuit [8e]. If the input data is input data to the own control device and the receiving buffer [5e] is not busy, the following operation is performed.

If input data exists in the receiving buffer [5e], the route [108] is sent to the receiving buffer [5e].
e) to transfer the input data. If there is no input data in the receiving buffer [5e], the following operation is performed.

In the selector [3e], the reception buffer [5e] in one or more path connection units [9e].
Is searched, and if no input data exists in the reception buffer [5e], the reception matching circuit [7e] is searched, and input data having a higher priority is selected through the path [106e], and is input through the path [104e]. The signal passes through the loopback circuit [1e] and is transferred to the read path of the own control device through the path [101e]. Here, the input data not selected by the reception matching circuit [7e] is transferred to the reception buffer [5e] through the path [108e].

Next, the operation of processing the output data will be described. First, output data from the write path [102e] of the own control device is selected by the selector [2e], and transferred to the distribution circuit [4e] through the path [105e].

Next, in the distribution circuit [4e], the transmission buffer [6] in the path connection unit [9e] to be transferred is set.
e], and if the transmission buffer [6e] is not busy, the transmission buffer [9e] in the path connection unit [9e] connected to the shortest distance transfer path to the destination of the output data. 6e] and the transmission path check circuit [8e] through the path [107e] by the following operation. When the transmission buffer [6e] is busy in the path connection unit [9e] connected to the transfer path of the shortest distance to the transmission destination of the transmission buffer [6e], the shortest transfer path Transmission buffer [6e] and transmission path check circuit [8e] in the path connection unit [9e] connected to the next closest transfer path.
To a closer transfer path that can be sequentially transferred [107
e] through the following operation. Further, when all the transmission buffers [6e] are busy, the busy buffer is notified to the self-control device, and the writing path [10
2e].

Next, the transmission path check circuit [8e] determines whether the transfer path is busy. In the case of busy, when the output data goes to the transfer path to be transferred to the distribution circuit [4e], the data is transferred from the distribution circuit [4e] to the transmission buffer [6e] through the path [107e]. If not busy, if there is output data in the transmission buffer [6e], there is no output data in the transmission buffer [6e] from the transmission buffer [6e],
When the output data from the distribution circuit [4e] goes to the transfer path to be transferred, the output data is transferred from the distribution circuit [4e] to the transmission path check circuit [8e] via the path [109e] and transmitted to the transfer path. . Further, when the data is transferred from the transmission buffer [6e] to the transmission path check circuit [8e] and the output data from the distribution circuit [4e] is directed to the transfer path to be transferred, the output data is transmitted to the distribution circuit [8e]. 4e] to the transmission buffer [6e] through the path [107e].

Further, in the reception matching circuit [7e] in the path connection section [9e], when the transferred data is not input data to the own control device and the reception buffer [5e] is not busy. In such a case, if it is determined that the transfer data between the other network connection devices is not transferred over the shortest distance, the data is taken into the own network connection device as described below in order to return the transfer data to a transfer path that is closer.

The operation up to the selector [3e] is performed in the same manner as the processing operation of the input data, and the transfer data between the other network connection devices is routed to the path [10] by the loopback circuit [1e].
3e] to the selector [2e], and the distribution circuit [4e] and thereafter operate in the same manner as the output data processing operation. Here, at the timing when the transfer data between the other network connection devices is selected by the selector [2e], a busy is notified to the own control device, and the output from the write path [102e] is suppressed.

Here, the receiving matching circuit [7e],
The path connection unit [9e] in the network connection device including the reception buffer [5e], the transmission buffer [6e], and the transmission path check circuit [8e] can be scalably increased or decreased according to the connection configuration.

Next, a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a block diagram showing a fourth embodiment of the present invention. Referring to FIG. 4, in a fourth embodiment of the present invention, a plurality of network connection devices that do not connect various control devices (CPU and the like) are added, and a side of the added network connection device that connects various control devices is connected. And a multi-node connection by connecting the connection side of the data transfer device to be connected to the various control devices of the added network connection device. The network connection device (same as that of the first embodiment) has a node (including the network connection device and its higher level) on both the X and Y sides of the route [105s],
[106s]. With this connection method, connection between nodes can be realized using the network connection device of the present invention.

Next, a fifth embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a block diagram showing a fifth embodiment of the present invention. Referring to FIG. 5, in a fifth embodiment of the present invention, a plurality of network connection devices (CPU and the like) to which various control devices are not connected are added, and a side of the added network connection device that connects various control devices. And a multi-node connection by connecting the connection side of the data transfer device to be connected to the various control devices of the added network connection device. The network connection device (same as that of the third embodiment) has a node (including the network connection device and its higher level) on both the X and Y sides of the route [108s],
[109s]. With this connection method, connection between nodes can be realized using the network connection device of the present invention.

Next, a sixth embodiment of the present invention will be described with reference to the drawings. FIG. 6 is a block diagram showing a sixth embodiment of the present invention. Referring to FIG. 6, a sixth embodiment of the present invention is such that the loop-type transfer paths of the second embodiment are multiplexed (a plurality of paths are set in parallel) and can be used simultaneously. is there. The configuration and the connection method are the same as those of the “paths # 1, # 2, # 3, #
4 "are multiplexed, and"# 11- # 1p, # 2 "
1 to # 2p, # 31 to # 3p, # 41 to # 4p ". Here, “# 11 to # 1p” means that p loop transfer paths of “# 1” are prepared. In other words, to prepare p all loop-type transfer paths,
= 4 × p loop-type transfer paths.

When there is no contention, the transfer performance is p times that of the second embodiment, and the transfer performance can be increased scalably.

Next, a seventh embodiment of the present invention will be described with reference to the drawings. FIG. 7 is a block diagram showing a seventh embodiment of the present invention. Referring to FIG. 7, a seventh embodiment of the present invention is obtained by connecting a plurality of the first embodiment or the third embodiment, and has one loop-type transfer path. This is the minimum configuration.

The configuration of this embodiment is the same as that of the second embodiment. However, the connection method of the loop type transfer path is as follows.

Loop type transfer path # 1: CP # 0 → CP #
1 → CP # 2 → CP # 3 → MM # 3 → MM # 2 → MM #
1 → MM # 0 → CP # 0 are connected by one loop-type transfer path, and the transfer performance is uneven between the CPU and the memory. However, when the performance is not so required, the network connection device or the loop-type transfer path , A transfer operation with a minimum configuration can be performed even when a certain loop-type transfer path becomes unusable due to a failure or the like.

Next, an eighth embodiment of the present invention will be described with reference to the drawings. FIG. 8 is a block diagram showing an eighth embodiment of the present invention. Referring to FIG. 8, an eighth embodiment of the present invention is obtained by connecting two units of the first embodiment or the third embodiment, and has one loop-type transfer path. This is the minimum configuration.

CPU # 0 [1f] and memory # 0
[5f] corresponds to various control devices, and CPU # 0 [1f]
Is an arithmetic unit, and the memory # 0 [5f] is a main memory. CPU
The side network connection device # 0 [2f] is connected to the CPU # 0
[1f] connected to a computing unit, and loop-type transfer path # 1
Input data from [3f] and loop-type transfer path #
1 [3f] is controlled. Similarly, the memory-side network connection device # 0 [4f]
[5f] connected to the main memory, and loop-type transfer path # 1
Input data from [3f] and loop-type transfer path #
1 [3f] is controlled. The loop type transfer path # 1 [3f] is connected to the CPU side network connection device # 0.
[2f] and the memory-side network connection device # 0
[4f] is connected by the following connection method.

Loop type transfer path # 1: CP # 0 → MM # 0 → CP # 0 This is a CPU connected by one loop type transfer path.
This is a minimum configuration example of one unit and one memory unit.

Next, a ninth embodiment of the present invention will be described with reference to the drawings. FIG. 9 is a block diagram showing a ninth embodiment of the present invention. Referring to FIG. 9, the embodiment of the present invention is different from the loop-type transfer path of the second embodiment. CPU # 0 to #m [1d] to [4
d] and memories # 0 to #n [17d] to [20d]
Corresponds to various control devices, and CPUs # 0 to #m [1d]
To [4d] are arithmetic units, memories # 0 to #n [17d] to
[20d] is a main memory. The CPU-side network connection devices # 0 to #m [5d] to [8d]
# 0 to #m [1d] to [4d] are connected to the operation units, and input data from loop type transfer paths # 1 to #R [9g] to [12g] and loop type transfer paths # 1 to #R. [9
g] to [12g].

Similarly, the memory-side network connection device #
0 to #n [13d] to [16d] are memory #
0 to #n [17d] to [20d],
Input data from loop-type transfer paths # 1 to #R [9g] to [12g] and loop-type transfer paths # 1 to #R [9
g] to [12g]. Loop-type transfer paths # 1 to #R [9g] to [12g] are connected to CPU-side network connection devices # 0 to #m [5d] to [8d] and memory-side network connection devices # 0 to #n [13].
[d] to [16d] are connected by the following connection method.

CPU side network connection device # 0 [5
d] are CPU-side network connection devices # 1 to #m [6
d] to [8d] and the memory-side network connection devices # 0 to #n [13d] to [16d] are all connected with the shortest distance. Similarly, CPU side network connection device #
1 to #m [6d] to [8d] and the memory side network connection devices # 0 to #n [13d] to [16d] are all connected to the control devices other than the own control device at the shortest distance.

As an example of connection, in the case of four CPUs and four memories (n, m = 3), ie, CPU-side network connection devices # 0 to # 3 (hereinafter, CP # to CP)
# 3), a connection method of the memory-side network connection devices # 0 to # 3 (hereinafter, MM # 0 to MM # 3) will be described. In order to make a connection with a control device other than the own control device at the shortest distance, CP # 0 is CP # 0 → CP # 1, CP # 0 → CP
# 2, CP # 0 → CP # 3, CP # 0 → MM # 0, CP
# 0 → MM # 1, CP # 0 → MM # 2, CP # 0 → MM
# 3, CP # 1, CP # 1 → CP # 0, CP # 1 → C
P # 2, CP # 1 → CP # 3, CP # 1 → MM # 0, C
P # 1 → MM # 1, CP # 1 → MM # 2, CP # 1 → M
M # 3 and CP # 2 are CP # 2 → CP # 0, CP # 2 →
CP # 1, CP # 2 → CP # 3, CP # 2 → MM # 0,
CP # 2 → MM # 1, CP # 2 → MM # 2, CP # 2 →
MM # 3 and CP # 3 are changed from CP # 3 to CP # 0 and CP # 3.
→ CP # 1, CP # 3 → CP # 2, CP # 3 → MM #
0, CP # 3 → MM # 1, CP # 3 → MM # 2, CP #
MM # 3 → MM # 0, MM # 0 → MM # 1, MM
# 0 → MM # 2, MM # 0 → MM # 3, MM # 0 → CP
# 0, MM # 0 → CP # 1, MM # 0 → CP # 2, MM
# 0 → CP # 3, MM # 1 is MM # 1 → MM # 0, M
M # 1 → MM # 2, MM # 1 → MM # 3, MM # 1 → C
P # 0, MM # 1 → CP # 1, MM # 1 → CP # 2, M
M # 1 → CP # 3, MM # 2 is MM # 2 → MM # 0,
MM # 2 → MM # 1, MM # 2 → MM # 3, MM # 2 →
CP # 0, MM # 2 → CP # 1, MM # 2 → CP # 2
MM # 2 → CP # 3, MM # 3 is MM # 3 → MM #
0, MM # 3 → MM # 1, MM # 3 → MM # 2, MM #
3 → CP # 0, MM # 3 → CP # 1, MM # 3 → CP #
2, a shortest transfer path of MM # 3 → CP # 3 is required.

By rearranging these and creating a plurality of loop transfer paths, loop type transfer path # 1: CP # 0 → CP # 1 → CP # 2
→ CP # 3 → MM # 0 → MM # 1 → MM # 2 → MM # 3
→ CP # 0, loop type transfer path # 2: CP # 0 → CP # 2 → MM # 0
→ MM # 2 → CP # 1 → CP # 3 → MM # 1 → MM # 3
→ CP # 0, Loop type transfer path # 3: CP # 0 → CP # 3 → MM # 3
→ CP # 1 → MM # 0 → MM # 1 → CP # 2 → MM # 2
→ CP # 0, loop type transfer path # 4: CP # 0 → MM # 0 → MM # 3
→ CP # 2 → CP # 3 → MM # 2 → CP # 1 → MM # 1
→ CP # 0, loop type transfer path # 5: CP # 0 → MM # 1 → CP # 1
→ MM # 2 → CP # 3 → CP # 2 → MM # 3 → MM # 0
→ CP # 0, loop type transfer path # 6: CP # 0 → MM # 2 → CP # 2
→ MM # 1 → MM # 0 → CP # 1 → MM # 3 → CP # 3
→ CP # 0, loop type transfer path # 7: CP # 0 → MM # 3 → MM # 1
→ CP # 3 → CP # 1 → MM # 2 → MM # 0 → CP # 2
→ CP # 0, loop type transfer path # 8: CP # 0 → MM # 3 → MM # 2
→ MM # 1 → MM # 0 → CP # 3 → CP # 2 → CP # 1
→ CP # 0 is connected by eight loop-type transfer paths, and the loop-type transfer path can be connected to all control devices with the shortest distance.

However, since the total number of various control devices is an even number, [CP # 0 → MM # 3, MM # 3 → CP #
0, MM # 0 → MM # 1, MM # 1 → MM # 0, CP #
2 → CP # 3, CP # 3 → CP # 2, CP # 1 → MM #
2, MM # 2 → CP # 1], for a total of eight shortest transfer paths
There is a book at a time.

Here, when the total number of the various control devices is an even number, and when the total number is a, the shortest transfer path is a × (a−1). Is required, and there is a shortest transfer path that exists every two. However, as an exception, when the total number of various control devices is two, the shortest transfer path needs to be 2 × (2-1) = 2, and the loop type transfer path needs to be (2-1) = 1. There is no two shortest transfer paths. When the total number of various control devices is an odd number, the total number is a
When the number of transfer paths is one, a × (a−1) shortest transfer paths are required, and (a−1) loop type transfer paths are required. Therefore, two shortest transfer paths do not exist.

Next, a tenth embodiment of the present invention will be described with reference to the drawings. FIG. 10 is a block diagram showing a tenth embodiment of the present invention. Referring to FIG. 10, a tenth embodiment of the present invention is the same as the ninth embodiment of the present invention, and has another control device #M [4h] and another control device side network connection device #M [8h. ], Other control device #N [20h], other control device side network connection device #
N [16h] is added. This is a connection of different control devices.

Next, an eleventh embodiment of the present invention will be described with reference to the drawings. FIG. 11 is a block diagram showing an eleventh embodiment of the present invention. Referring to FIG. 11, an eleventh embodiment of the present invention has a configuration in which the configuration of the tenth embodiment is connected to two nodes as one node, and “the other control device #N [20h] of the node X”. Is replaced with “node Y”, and “other control device #M [4h] of node Y” is replaced with “node Y”.

According to this method, no special design is required,
Multi-node connections are also possible. Further, the above-mentioned connection between nodes is one set, but connection in a plurality of sets is also possible.

[0081]

A first effect of the present invention is that the transfer performance is not so affected by the number of connected control devices, and the required hardware can be changed in a scalable manner according to the number of connected devices. The reason is that the number of loop-type transfer paths can be connected from one, the path connection unit in the network connection device can be connected from one, and even if the number of loop-type transfer paths is one, data transfer between various control devices is possible. Because it can be.

The second effect is that when the performance is not so required, the multiplicity of the loop type transfer path can be reduced to reduce the hardware cost, and when the performance is required, the multiplicity can be increased to increase the performance. Priority. By increasing or decreasing the multiplicity in this manner, the network performance can be changed in a scalable manner. The reason is the same as that of the first effect.

The third effect is that when multi-stage connection is performed due to hardware restrictions in crossbar connection, there is a case where transfer data destined for different control devices use the same path in crossbars other than the last stage. Although there is a possibility of degradation, the present invention suggests that the likelihood of performance degradation is lower for crossbar connections. The reason is,
Since there are multiple loop-type transfer paths and a loop structure,
This is because when the shortest loop-type transfer path cannot be used, a loop-type transfer path that is close in sequence may be used.

The fourth effect is that, when performing an operation in each control device after a large amount of memory access, a memory access process unrelated to the operation may be blocked, and the operation may have to be waited. The proposal of the present invention is to reduce the number of cases waiting for the operation as in the case described above. The reason is that the loop-type transfer path serves as a buffer depending on the transfer length and the transfer path, so that the memory access processing irrelevant to the operation can be quickly cleared from each control device.

The fifth effect is that data can be transferred even when a certain loop-type transfer path becomes unusable due to a failure of the network connection device or the loop-type transfer path. The reason is that a plurality of loop-type transfer paths have a loop structure, and a plurality of loop-type transfer paths other than the disabled transfer path can be used.

The sixth effect is that the design can be saved in connection between nodes. The reason is that, for a plurality of data transfer devices to be connected, a plurality of network connection devices that do not connect various control devices are added, and a certain data transfer device connects the various network control devices of the added network connection device to the control device. This is because a multi-node connection can be made by connecting the side of the network connection device to which various control devices are added to the data transfer device to be connected, so that a dedicated design of the inter-node network connection device is not required.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a second embodiment of the present invention.

FIG. 3 is a block diagram of a third embodiment of the present invention.

FIG. 4 is a block diagram of a fourth embodiment of the present invention.

FIG. 5 is a block diagram of a fifth embodiment of the present invention.

FIG. 6 is a block diagram of a sixth embodiment of the present invention.

FIG. 7 is a block diagram of a seventh embodiment of the present invention.

FIG. 8 is a block diagram of an eighth embodiment of the present invention.

FIG. 9 is a block diagram of a ninth embodiment of the present invention.

FIG. 10 is a block diagram of a tenth embodiment of the present invention.

FIG. 11 is a block diagram of an eleventh embodiment of the present invention.

FIG. 12 is a block diagram showing a conventional technique.

FIG. 13 is a block diagram showing another conventional technique.

[Explanation of symbols]

1a to 4a CPU # 0 to #m 5a to 8a CPU side bus connection device # 0 to #m 9a bus 10a contention arbitration unit 11a to 14a memory side bus connection device # 0 to #n 15a to 18a memory # 0 to #n 101a to 133a Path 1b to 4b CPU # 0 to #m 5b to 8b CPU side crossbar connecting device # 0 to #m 9b, 12b Crossbar control unit 10b, 11b Crossbar 13b to 16b Memory side crossbar connecting device # 0 to #b
n 17b-20b Memory # 0- # n 101b-134b Path 1c Selector 2c Distribution circuit 3c Reception buffer 4c Transmission buffer 5c Reception matching circuit 6c Transmission path check circuit 7c Path connection unit 101c-106c Path 1d-4d CPU # 0 to #m 5d to 8d CPU side network connection device # 0 to #d
m 9d to 12d Loop type transfer paths # 1 to #L 13d to 16d Memory side network connection device # 0
To #n 17d to 20d Memory # 0 to #n 1e Return circuit 2e, 3e Selector 4e Distribution circuit 5e Receiving buffer 6e Transmission buffer 7e Receiving matching circuit 8e Transmission path check circuit 9e Path connection unit 101e to 109e Route 1f CPU # 0 2f CPU-side network connection device # 0 3f Loop-type transfer path # 1 4f Memory-side network connection device # 0 5f Memory # 0 9g to 12g Loop-type transfer path # 1 to #R 4h Other control device #M 8h and others Control device side network connection device #M 16h Other control device side network connection device #N 20h Other control device #N 105s, 106s, 108s, 109s Route

Claims (4)

[Claims] 1. A data transfer device comprising a plurality of various control devices typified by a CPU and a memory, a transfer path, and a network connection device, wherein the network connection device is configured to transfer data from the various control devices. It is checked whether the transfer path is available at the time of transmission, and the shortest transfer path to the various control devices at the destination or the shortest transfer path to the various control devices at the destination is being used. In this case, a transmission path check circuit connected to the next closest transfer path, a transmission buffer for holding the transfer data to be sent from the various control devices to the transmission path check circuit, and a transfer buffer for transmitting the transfer data from the transfer path. At the time of reception, it is determined whether or not the data is the transfer data to the various control devices, and a reception match for capturing the transfer data based on the result. A plurality of path connection units each having a receiving buffer for holding the transfer data from the reception matching circuit; and selecting the transfer data from the reception buffer to the various control devices, A data transfer device comprising: a first selection circuit that transfers data to a control device; and a distribution circuit that transfers the transfer data from the various control circuits to the transmission buffer. 2. A plurality of loop-type transfer paths, which are transfer paths for sequentially connecting the network connection devices in series at the shortest distance, and are connected to each of the loop-type transfer paths in the network connection device. 2. The data transfer device according to claim 1, further comprising a plurality of the path connection units corresponding to the loop-type transfer paths. 3. When the transfer data is not transferred between the network connection devices over the shortest distance, the transfer data between the network connection devices is transferred back to the loop-type transfer path closer to the network connection device. And determining whether or not the received matching circuit captures the output data; and any of the transfer data from the various control devices and the transfer data transferred between the network connection devices in the network connection device. 3. The data transfer device according to claim 2, further comprising: a second selection circuit for selecting whether the transmission data is transmitted from the reception matching circuit, and a return circuit for transmitting the transfer data from the reception matching circuit to the second selection circuit. . 4. The connection between the first selection circuit of the first network connection device and the distribution circuit of the second network connection device, and the distribution circuit and the connection circuit of the first network connection device. And a connection between the first selection circuit of the second network connection device, and transferring the transfer data between the first network connection device and the second network connection device. 4. The method according to claim 1, wherein
A data transfer device according to claim 1.