JPH10289837A - Laminated electronic parts - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide laminated electronic parts allowed to be miniaturized and narrowed at their packaging intervals at the time of packaging them on a printed board. SOLUTION: A chip capacitor 10 to be laminated electronic parts has a substrate 11 formed by laminating plural sheet layers 11a to 11e consisting of ceramics and external electrodes 13a, 13b connected to inner electrodes 12a to 12d, formed on the sheet layers 11b to 11e and exposed only to one end face 111 of the substrate 11 by vertically dividing a via hole electrode obtained by filling a through hole with conductive past. In the case of packaging the chip capacitor 10 on a printed board, the end face 111 forming the external electrodes 13a, 13b becomes a packaging face.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated electronic component, and more particularly to a laminated electronic component provided with a plurality of external electrodes only on one end face of a substrate and having the end face as a mounting surface when mounted on a mounting board. .

[0002]

2. Description of the Related Art Multilayer electronic components typified by chip resistors and chip capacitors are indispensable for miniaturization and high performance of electronic devices, and higher densities and higher performance are increasingly required. In response to this demand, recently, a plurality of ceramic sheet layers (51a to 51a) as shown in FIG.
e) having a substrate 51 formed by laminating
A chip capacitor 50 connects internal electrodes 52a to 52d formed on 1b to 51e to the rear surface of the substrate 51 by via-hole electrodes 53a and 53b, and connects external electrodes 54a and 54b to the extracted portions of the via-hole electrodes 53a and 53b. Proposed. At this time, although not shown, the back surface of the chip capacitor 50 becomes a mounting surface, and the external electrodes 54a and 54b are connected to the wiring patterns on the printed board by soldering or the like, so that the chip capacitor 50 is mounted on the printed board. Will be done.

However, the chip capacitor 5 shown in FIG.
0, the end face of the substrate 51 and the via hole electrode 53a
Assuming that the distance between the external electrodes is L1 and the diameter of the via hole electrode 53a is L2, the internal electrodes 52a to 52d formed on the sheet layers 51a to 51d are drawn out to the back surface by the via hole electrodes 53a and 53b. Compared with the case where the substrate 51 is directly provided by printing or the like, the distance L1 between the end face of the substrate 51 and the via hole electrode 53a and the radius L2 / 2 of the via hole electrode 53a are required, and the lateral direction of the substrate 51 is increased by (L1 + L2 / 2) × 2. There was a problem. For example, L1 is about 0.1 mm, L2 is about 0.1 m
Assuming that m, the lateral direction of the substrate 51 needs to be increased by about 0.3 mm.

To solve this problem, as shown in FIG. 6, a chip capacitor as disclosed in Japanese Patent Application Laid-Open No. 7-297080 has been proposed. In FIG. 6, a chip capacitor 60 is connected to a substrate 61 formed by laminating a plurality of ceramic sheet layers (61a to 61e) and internal electrodes 62a to 62d formed on the sheet layers 61b to 61e. In addition, a conductor made of a conductive paste is filled in the through-hole, and the conductor in the through-hole has external electrodes 63a and 63b exposed at two opposite end surfaces of the substrate 61. Then, the external electrodes 63a and 63b of the chip capacitor 60 and the wiring pattern 65 on the printed circuit board 64 are soldered to each other.
Thus, the chip capacitor 60 is mounted on the printed circuit board 64.

In the case of the chip capacitor 60, since the external electrodes 63a and 63b are formed by exposing the conductors in the through holes to two opposing end surfaces of the substrate 61, the chip capacitor 60 shown in FIG. 50, the distance L between the end face of the substrate 51 and the via-hole electrode 53a
1. The radius L2 / 2 of the via hole electrode 53a becomes unnecessary, and as a result, compared with the chip capacitor 50 of FIG.
The lateral direction of the substrate 61 is reduced by (L1 + L2 / 2) × 2.

[0006]

However, in a multilayer electronic component typified by the above-mentioned conventional chip capacitor, when the multilayer electronic component is mounted on a printed circuit board using solder, an external component of the multilayer electronic component is not provided. A solder fillet is required between the electrode and the wiring pattern on the printed circuit board. Therefore, it is necessary to increase the circuit pattern from the end face of the board by the solder fillet (L3 in FIG. 6), and it is difficult to reduce the mounting interval between the respective laminated electronic components. There was a problem of becoming.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and it is an object of the present invention to provide a multilayer electronic component which can be reduced in size and can reduce the mounting interval when mounted on a printed circuit board. The purpose is to provide.

[0008]

In order to solve the above-mentioned problems, a laminated electronic component according to the present invention comprises: a substrate having a plurality of sheet layers made of at least one of a dielectric material and a magnetic material; A plurality of internal electrodes formed therein, and a plurality of external electrodes connected to the internal electrodes and formed only on one end surface of the substrate, the end surface of the substrate including the external electrodes, It is characterized by being a mounting surface when mounting on a mounting board.

According to the electronic circuit component of the present invention, one of the substrates
Since a plurality of external electrodes are provided only on one end face and the end face is used as a mounting surface, a solder fillet between the external electrodes of the multilayer electronic component and the wiring pattern on the printed board can be eliminated.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an exploded perspective view of one embodiment of the laminated electronic component of the present invention. A chip capacitor 10 that is a multilayer electronic component includes a substrate 11 formed by stacking a plurality of sheet layers (11a to 11f) made of ceramic;
Internal electrode 12a formed on sheet layers 11b to 11e
12d and external electrodes 13a and 13b formed only on one end face 111 of the substrate 11.

Then, as shown in FIG. 2, the end face 1 of the chip capacitor 10 on which the external electrodes 13a and 13b are formed.
The chip capacitor 10 is mounted on the printed circuit board 1 by connecting the external electrodes 13 a and 13 b to the wiring pattern 2 on the printed circuit board 1 as the mounting board with solder 3 using the mounting surface 11 as a mounting surface.

Next, a method of manufacturing the chip capacitor 10 will be described. First, a plurality of mother sheet layers made of ceramic are prepared. Next, through holes are formed in the mother sheet layers by punching, and conductive layers to be the internal electrodes 12a to 12d are formed by screen-printing a conductive paste. When this conductor paste is printed, the conductors made of the conductor paste are filled in the through holes, and the conductor layers on the respective mother sheet layers are connected via the conductors in the through holes.

Next, after laminating the plurality of mother sheet layers to form a mother substrate, the mother substrate is cut into blocks so that the conductor in the through hole is exposed only on one end face 111 of the substrate 11. . Next, the substrate 11, the conductive layers on the sheet layers to be the internal electrodes 12a to 12d, and the conductors in the through holes to be the external electrodes 13a and 13b are integrally fired. Thus, the chip capacitor 10 including the external electrodes 13a and 13b formed only on the end face 111 of the substrate 11 serving as a mounting surface is completed.

According to the chip capacitor which is a multilayer electronic component of the above-described embodiment, since a plurality of external electrodes are provided only on one end surface of the substrate, the mounting surface is smaller than that of the conventional chip capacitor 60 shown in FIG. In the end face opposite to the end face, the radius L2 / 2 of the via hole electrode is unnecessary.

As a result, the conventional chip capacitor 60
Compared to (FIG. 6), the horizontal direction can be reduced by L2 / 2. Conversely, in the case of the same size, the internal electrodes can be made large, and accordingly, the capacitance value of the chip capacitor can be made large.

Further, since the end surface on which the external electrodes are provided is used as the mounting surface, a solder fillet between the external electrodes of the chip capacitor and the wiring pattern on the printed circuit board can be eliminated. Therefore, it is not necessary to make the wiring pattern larger than the end surface of the chip capacitor, and when mounting a plurality of chip capacitors on a printed circuit board, the mounting interval can be reduced, and the mounting density of the chip capacitors is improved. As a result, the size of the printed circuit board can be reduced.

In the above-described embodiment, the case where the multilayer electronic component is a chip capacitor is described. However, as shown in FIG. 3, a plurality of ceramic sheet layers (21a) are formed.
To 21j), a plurality of capacitors C formed by a plurality of internal electrodes 22a to 22h are formed on a substrate 21 formed by stacking
Application to a capacitor array component in which 1 to C4 are built is also possible. At this time, the capacitor C1 is connected to the internal electrode 22.
a, 22b, the capacitor C2 is connected to the internal electrodes 22c, 22c.
At d, the capacitor C3 is formed by the internal electrodes 22e and 22f, and the capacitor C4 is formed by the internal electrodes 22g and 22h.

In this case, since there is no need for via-hole electrodes for connecting the respective capacitors C1 to C4 inside the substrate 21, the size of the capacitor array component 20 can be reduced. Therefore, the size of the printed circuit board (not shown) can be further reduced.

Further, as shown in FIG. 4, a plurality of sheet layers 31a to 31
In 1h, the external electrodes 33a and 33b may be provided also on the sheet layer 31b where the internal electrodes 32a to 32d are not formed, and the external electrodes 33a and 33b of the chip capacitor 30 may be enlarged. In this case, since the external electrodes 33a and 33b of the multilayer electronic component 30 become large, the external electrodes 3
The bonding strength between 3a, 33b and a circuit pattern (not shown) on the printed board is improved.

Although not shown, the multilayer electronic component includes a chip resistor, a chip inductor, a resistor array component,
The present invention can be applied to inductor array components and composite components thereof.

Further, a case has been described in which a conductor made of a conductive paste is filled in the through-hole, and the conductor in the through-hole is exposed only at the end face of the substrate to form an external electrode. An external electrode may be formed by applying a conductive layer made of a conductive paste on the wall surface and exposing the conductive layer on the through-hole wall surface to only one end surface of the substrate.

As a method of manufacturing a laminated electronic component, a mother substrate is cut into blocks, and then the substrate, a conductive layer on a sheet layer serving as an internal electrode, and a conductor in a through hole serving as an external electrode are integrally fired. However, the same effect can be obtained even if the mother substrate, the conductive layer on the sheet layer serving as the internal electrode, and the conductor in the through hole serving as the external electrode are integrally fired, and then the mother substrate is cut into blocks. Is obtained.

[0023]

According to the multilayer electronic component of the present invention, since a plurality of external electrodes are provided only on one end face of the substrate, the lateral direction can be reduced as compared with the conventional multilayer electronic component.

Further, since the end surface on which the external electrodes are provided is a mounting surface, a solder fillet between the external electrodes of the laminated electronic component and the wiring pattern on the printed board can be eliminated. Therefore, it is not necessary to make the wiring pattern larger than the end of the multilayer electronic component, and when mounting a plurality of multilayer electronic components on a printed circuit board, the mounting interval can be narrowed, and the mounting density of the multilayer electronic component is improved. I do. As a result, the size of the printed circuit board can be reduced.

[Brief description of the drawings]

FIG. 1 is an exploded perspective view of an embodiment according to a multilayer electronic component of the present invention.

FIG. 2 is a cross-sectional view when the multilayer electronic component of FIG. 1 is mounted on a printed circuit board.

FIG. 3 is an exploded perspective view of another embodiment of the multilayer electronic component of the present invention.

FIG. 4 is an exploded perspective view of still another embodiment according to the multilayer electronic component of the present invention.

FIG. 5 is a sectional view showing a conventional laminated electronic component.

FIG. 6 is a sectional view showing another conventional laminated electronic component.

[Explanation of symbols]

10, 20, 30 Multilayer electronic components 11, 21, 31 Substrates 11a to 11f, 21a to 21j, 31a to 31h
Sheet layer 111 End surface (mounting surface) 12a to 12d, 22a to 22h, 32a to 32d
Internal electrodes 13a, 13b, 23a to 23h, 33a, 33b
External electrode

Claims (1)

[Claims] A substrate formed by laminating a plurality of sheet layers made of at least one of a dielectric material and a magnetic material, a plurality of internal electrodes formed inside the substrate, and connected to the internal electrodes; A multilayer electronic component, comprising: a plurality of external electrodes formed only on one end surface of the substrate; and an end surface of the substrate including the external electrodes serving as a mounting surface when mounted on a mounting substrate.