JPH10260933A - Bus arbitrating function selecting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow a bus arbitrating function selecting circuit for bus arbitrating function mounted modules connected to a common bus to select the bus arbitrating function having top priority out of normal bus arbitrating function mounted modules and make it operate when a bus arbitrating function mounted module gets out of order. SOLUTION: This circuit is provided with a bus arbitrating means 1 which sets priority by the modules and arbitrates access to the common bus, a module priority deciding means 2 which gathers fault states including the priority of other modules and decides whether its module has top priority, an arbitrating opeation deciding means 3 which detects the decision result of the module priority deciding means 2 and whether bus arbitrating functions of other modules are in operation and makes the bus arbitrating means 1 of its module operate, and a module fault detecting means 4 which detects a fault in its module.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus arbitration circuit having a detachable bus arbitration circuit, for example, when any number of modules having a detachable bus arbitration circuit are mounted on a common bus of a parallel distributed processing apparatus. The present invention relates to a bus arbitration function selection circuit that automatically selects one of the bus arbitration functions to operate the bus arbitration function.

2. Description of the Related Art There is a demand for an improvement in data processing capacity accompanying a recent increase in the capacity of a transmission apparatus and an expansion in response to an improvement in the performance of the apparatus. For this reason, use of a parallel distributed processing device is mentioned, but it is necessary to arbitrate a common bus to which these modules are attached.

[0003]

2. Description of the Related Art FIG. 6 is a block diagram of a conventional example. Normally, when a single module is provided in the processing device, the processor that has acquired the right to use the internal bus in the module,
The right to use the common bus that connects this module to the input / output device is automatically acquired.

For example, as shown in FIG. 6, a plurality of processors 411 _{1 to} 411 _n , a RAM 4
13, the ROM 414 is connected, and a plurality of processors are connected to the arbitration circuit 412.

Now, assuming that a bus request signal is input to the arbitration circuit 412 from a plurality of processors, the arbitration circuit 412 determines one processor from among the processors that are transmitting the bus request signal, and determines an internal bus and a common bus. Had given both usage rights.

As a result, the processor to which the right to use both the internal bus and the common bus has been given,
And the storage device 402 can be freely accessed.

[0007]

As described above, since the arbitration is performed by one arbitration circuit 412, if the bus arbitration circuit fails, the operation of the entire system stops. As a result, there is a problem that the operation of the transmission device becomes impossible.

According to the present invention, when a failure occurs in the bus arbitration circuit itself or a module in which the bus arbitration circuit is mounted, the module having the highest priority is automatically selected from among the modules in which the bus arbitration circuit is normal. Switch to

After the bus arbitration circuit mounted on the switched module is enabled, the bus arbitration operation is performed using the arbitration function of this circuit.

[0010]

FIG. 1 is a diagram illustrating the principle of a bus arbitration function selection circuit according to the present invention. According to the first aspect of the present invention, when a plurality of modules each having a bus arbitration function are mounted on a common bus and bus arbitration is performed, a priority is set for each module.

A bus arbitration means for arbitrating access to the common bus; and a module priority determining means for collecting a failure state including the priority of another module and determining whether or not the own module has the highest priority. And a degree determining means.

Further, an arbitration operation judging means for judging whether to operate the bus arbitration means of its own module by detecting the judgment result of the module priority judging means and whether or not the bus arbitration function of the other module is in operation. And module failure detecting means for detecting a failure in the own module.

Then, only one of a plurality of bus arbitration functions mounted on each module is selected and operated. According to a second aspect of the present invention, when the module failure detecting means detects a failure, the bus arbitration function in the own module is stopped and the failure is notified to another module.

According to a third aspect of the present invention, when the arbitration operation determining means determines that the bus arbitration function of another module is in an operating state, the bus arbitration function of the own module has the highest priority. Was not enabled.

Hereinafter, the principle of the present invention will be described with reference to FIG. 1. The function of each part is as follows. Reference numeral 1 denotes a bus arbitration unit which indicates which module is to be enabled to access the common bus.

2 is a module priority determination means,
This is a section for comparing the status of the own module with the mounted other modules and the priority to determine whether the own module has the highest priority.

Reference numeral 3 denotes an arbitration operation determining means for detecting whether or not the own module has the highest priority and whether or not the bus arbitration means of any module is operating and operating the own bus arbitration means. This is a part for determining whether or not the above is true.

Reference numeral 4 denotes a module failure detecting means for detecting a bus arbitration means in the module itself or an internal failure (for example, a clock loss). Next, the principle of the operation of the present invention will be described. Priorities (module iD) are set for each module.

The module priority judging means 2 collects failure states including the priority of each module ( ₁ to ₁ ).
₃ ) Then, it is determined whether or not the own module has the highest priority, and the determination result is sent to the arbitration operation determination means 3.

Note that by making the failure state the same as the unmounted module, the unmounted module is excluded from the priority determination. In addition, the arbitration operation determining means 3 notifies other modules of the status as to whether or not the bus arbitration function is operating, thereby indicating the presence of the bus arbitration function as a whole system.

Basically, the operation of the bus arbitration function is defined as a module having the highest priority.
Is always monitored, and the signal of the status OR (logical sum of the status transmitted by each module) is monitored, and if an operating bus arbitration function exists, the bus arbitration of the own module is performed. The operation of the function is not enabled, and multiple bus arbitration functions are disabled.

Conversely, if the operation of the arbitration function of the other module cannot be confirmed by monitoring the signal of the status OR, and if the priority of the own module is the highest, the bus arbitration function of the own module is enabled. Make it work.

The arbitration operation judging means 3 determines that a failure occurs in its own module even while the bus arbitration means 1 is operating.
Arbitration operation is stopped by forced stop. Accordingly, the bus arbitration function can be switched by having a bus arbitration function that can operate normally and enabling the bus arbitration function of another module having the highest priority.

That is, since one bus arbitration function operates at all times as a whole system, the common bus can be used almost without being affected by module insertion / removal or failure.

[0025]

FIG. 2 is a block diagram of a processing apparatus to which the first to third bus arbitration function selection circuits of the present invention are applied, FIG. 3 is an explanatory diagram of connection between modules, and FIG. _1-3 "pin input corresponding view, FIG 5 is a diagram showing a condition in which the module itself becomes the highest priority.

Although there are, for example, four modules in FIG. 2, each module has the same configuration, and therefore, is represented by the module 1 and the configurations of the modules 2 to 4 are omitted.

Here, the same reference numerals indicate the same objects throughout the drawings. Further, the details already described above are briefly described above, and the portions of the present invention are described in detail.
First, in FIG. 2, four modules 1 to 4 are connected to an input / output device 201 and a common RAM 202 via a common bus 108.

In these modules 1 to 4, the processor 101, the R0M 102, the RAM 10
3 and an interface (I / F) LSI 106 are connected to each other via an internal bus 105, and the internal bus 105 is connected to a common bus 108 via a bidirectional buffer 104.

The I / FLSI 106 shown in FIG.
Receives the address output to the internal bus 105,
The common bus is arbitrated according to the address and an arbitration signal received from an I / FLSI (not shown) provided in another module via the gate circuit 107, and a bidirectional buffer is responsive to the arbitration result. The operation of the control unit 104 is controlled.

The address space of the system shown in FIG. 2 is divided into an internal space allocated to the RAM 103 and the ROM 102 in the modules 1 to 4 and a shared bus space allocated to the input / output device 201 and the shared RAM 202. And a predetermined range of addresses is assigned to each of them.

The configuration of the above-mentioned I / FLSI is the same as that of the principle configuration diagram shown in FIG. here,
3 to 5 which are used when describing an embodiment of the present invention (see FIG. 1).

FIG. 3 shows the connection between the modules, taking as an example the case of four modules from module 1 to module 4. Since there are _three input terminals ₁ to ₃ for the signal of other module failure (these terminals are collectively referred to), the signal of the module to be input to the input terminal is switched in each module iD. The signal of the own module is turned back internally and compared with the signal.

As shown in FIG. 1, a failure of the own module (including not mounted) in each module, a failure of another module
_The signals of _1-3 , the status OR, and the status of the own module are information exchanged with other modules, and other signals are transmitted via three intermediate lines among the right lines in FIG. Sent to three modules.

However, other signals of the module iD (priority), bus arbitration means failure, other failure, determination result, and forced stop are exchanged in the own module. Flows.

FIG. 4 is a diagram corresponding to the " ₁ to ₃ " terminal input for each module, and shows which module failure information is input to the " ₁ to ₃ " terminals of the modules ₁ to 4 shown in FIG. It is a thing.

For example, terminal ₁ of the module having the highest iD (priority) has failure information of module 2, terminal ₂ has failure information of module 3, terminal ₃ has failure information of module 4, Each of these failure information is sent to the module priority determination means 2 as other module failure information in FIG.

It should be noted that failure information is transmitted to modules having iD (priority) of 2 to 4 as in the case of the module having iD1. FIG. 5 shows conditions for the own module to have the highest rank.

For example, the module having the highest iD (priority) (hereinafter abbreviated as module 1) has the highest priority, and its own module is operating normally regardless of the state of other modules. Then, when a bus arbitration request is made, the bus arbitration must be performed.

The module 2 cannot perform an arbitration operation if the module 1 having a higher priority than its own module is operating normally. However, if a failure (including unmounted) occurs in the module 1, the module 1 cannot enable the arbitration function. Therefore, the module 2 must perform the arbitration operation with the arbitration function enabled.

Therefore, the conditions under which the module 4 can enable the arbitration function are as follows:
Indicate that a failure has occurred. Here, it is assumed that the tables shown in FIGS. 4 and 5 are stored in the module priority determination means 2 of FIG. 1, and the iD (priority) of the own module is known in advance.

Now, the operation of FIG. 1 will be specifically described with reference to FIGS. Each module has a priority set in advance, and the module iD, the failure information input terminal, and the highest priority condition shown in FIGS. It is assumed that it is stored in the priority determination means 2.

Also, by making the failure state synonymous with the module not mounted, the module not mounted is excluded from the priority determination. Now, when a failure state of another module is input to the module priority determination means 2, this priority determination means determines the priority of the failed module and the priority of its own module using the stored FIGS. By comparison, it is determined whether or not the own module has the highest priority, and the determination result is sent to the arbitration operation determining means 3.

Since the comparison between the priority of the failed module and the priority of the own module as described above is also performed for the remaining three modules, it is erroneously determined that these modules have the highest priority. The possibility of doing so disappears.

Here, whether or not the arbitration function is to be operated from the own module is determined as a status signal from the arbitration operation determination means 3 by a common line to another module (this common line is
As shown in FIG. 3, it is one line, but it is connected to other modules).

Other modules also send status signals. As a result, since the signal of the status OR is input to the own module, the arbitration operation determining means 3 can determine whether or not there is a module operating the arbitration function including the other module and the own module.

Basically, the operation of the bus arbitration function is defined as the highest-priority module, and the arbitration operation determining means 3 constantly monitors and determines the status of the signal of the status OR. If the bus arbitration function of the module is in operation, the bus arbitration function of the own module is not made valid (not operated).

Conversely, if it is determined that the signal state of the status OR indicates that the bus arbitration function is not operating and that the own module is in the highest priority state, the own module's bus arbitration function is operated.

However, when the module failure detecting means 4 detects a failure of its own module, even if the arbitration operation determining means 3 is transmitting a valid signal of the bus arbitration function, the transmission of this signal is stopped, and It sends a signal of its own module failure to another module to notify it.

As a result, even if a module that is operating the bus arbitration function fails, the bus arbitration function that can operate normally can be operated from another module immediately. In this way, only one bus arbitration function operates at all times as a whole system, and it becomes possible to use the common bus almost without being affected by module insertion / removal or failure.

[0050]

As described in detail above, when the module with the bus arbitration function fails, the bus arbitration function with the highest priority is automatically selected from the modules with the normal bus arbitration function to operate. There is an effect that it can be done.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining the principles of first to third bus arbitration function selection circuits according to the present invention;

FIG. 2 is a configuration diagram of a processing device to which the first to third bus arbitration function selection circuits of the present invention are applied;

FIG. 3 is an explanatory diagram of connection between modules.

FIG. 4 is a diagram corresponding to “ ₁ to ₃ ” terminal input for each module.

FIG. 5 is a diagram showing a condition under which the own module has the highest rank.

FIG. 6 is a configuration diagram of a conventional example.

[Explanation of symbols]

 Reference Signs List 1 bus arbitration unit 2 module priority determination means 3 arbitration operation determination means 4 module failure detection means 101 processor 102, 414 ROM 103, 413 RAM 104 bidirectional buffer 105 internal bus 106 interface LSI 107 gate circuit 108 common bus 201 input / output device 202 Shared RAM 401 I / O device 402 Storage device 411 Processor 412 Arbitration circuit

Claims (3)

[Claims] When a plurality of modules each having a bus arbitration function are mounted on a common bus and bus arbitration is performed, a priority is set for each module and a bus that arbitrates for access to the common bus is provided. Arbitration means; module priority determination means for collecting a failure state including the priority of another module to determine whether the module itself has the highest priority; determination results of the module priority determination means; Arbitration operation determining means for detecting whether or not the bus arbitration function of the own module is operating and determining whether to operate the bus arbitration means of the own module; and module failure detecting means for detecting a failure in the own module. , Of the multiple bus arbitration functions mounted on each module,
A bus arbitration function selection circuit, wherein only one is selected and operated. 2. When the module failure detecting means detects a failure, the bus arbitration function in the own module is stopped, and
2. The bus arbitration function selection circuit according to claim 1, wherein a failure is notified to another module. 3. When the arbitration operation determination means determines that the bus arbitration function of another module is in an operating state, the bus arbitration function of the own module is not enabled even if the own module has the highest priority. 2. The bus arbitration function selection circuit according to claim 1, wherein: