JPH10257004A - Communication equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To count accurately an interval of intermittent reception. SOLUTION: The communication equipment is provided with an error measurement control section 17, a bit counter 21 operated only for an error measurement and a correction purpose bit count value register 22 in addition to a timing control section 2 for an interval of intermittent reception having been used for a conventional receiver. This receiver counts a BSClock from an inexpensive crystal oscillator 5 to measure an error of a BS timer 9 counting an interval time to control the error not to be accumulated by correcting the error based on the measurement value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an intermittent communication apparatus configured to receive only a time during which an object to be received is being transmitted.

[0002]

2. Description of the Related Art FIG. 1 shows an example of the configuration of a conventional intermittent receiver.
The configuration of the intermittent receiver according to the TDMA communication standard shown in FIG.

In FIG. 1, reference numeral 1 denotes a receiving unit, and 2 denotes a timing control unit of a block for controlling reception timing. The timing control unit 2 includes an intermittent reception control unit 3 for controlling intermittent reception and a burst and reception control unit 4 for controlling burst reception. The intermittent reception control unit 3 and the burst reception control unit 4 respectively include a slow reference clock BSCLock generated by the crystal oscillation circuit 5 and a TCXO.
(Temperature Compensated Crystal Oscillation Circuit) It operates in synchronization with the early reference clock Main Clock generated by 6. Further, the intermittent reception control unit 3 receives a signal from the BS timer 9, and the burst reception control unit 4 outputs a slot counter 10.
And a bit counter 11. Reference numeral 12 denotes a power supply control unit that turns on and off the main reception unit power supply 13 at a predetermined timing during intermittent reception.

[0004] The operation of the intermittent receiving apparatus having such a configuration is described below.
The description will be given according to the timing of PHS, which is one of the TDMA communication systems shown in FIG.

In FIG. 2, the horizontal axis represents time, and the operation timing of (a) MainClock, (b) slot counter 10, and (c) bit counter 11 in FIG.

In the PHS standard, one frame (5 m
s) is divided into eight slots. A reception slot of each receiver is assigned to one slot in one frame. Each slot contains 240 bits of data.

The bit counter 11 in the burst reception controller 4 counts 240 bits with a 384 kHz clock. The slot counter 10 includes:
Eight slots are counted at a cycle of 6 kHz to control burst reception timing. These counters 10 and 11 are operating in synchronization with the early MainClock. Mai where TCXO6 occurs
nClock has a small error of several ppm, and can precisely control burst reception timing.

Next, the operation timing at the time of intermittent reception will be described with reference to a timing chart shown in FIG.

In FIG. 3, the horizontal axis represents time.
In FIG. 3, (a) to (h) show BSC in FIG.
lock, BS timer 9, main receiver power signal, Main
Clock, slot counter 10, bit counter 11, slots actually received by the receiver, and operation timings of radio waves to be received are shown.

The reception operation at the time of intermittent reception will be described with reference to FIG. At the time of intermittent reception, a predetermined timing STEP0
Then, the power supply control unit 12 lowers the output signal of the main reception unit, which is the output of the main reception unit.
No ock is supplied (see FIGS. 3C and 3D). Therefore, the slot counter 10 and the bit counter 11 stop their operations (see FIGS. 3E and 3F). Hereinafter, a state in which the main receiving unit power signal falls is referred to as a sleep state, and the length of the sleep state is referred to as a sleep interval.

On the other hand, the power supply of the crystal oscillation circuit 5 is always turned on, and the BSCLock is supplied even during sleep (see FIG. 3A). Therefore, BSC during sleep
The BS timer 9 synchronized with the lock counts the sleep interval. The BS timer 9
When the counting of the interval is completed (STEP 1),
The power control unit 12 raises the main reception power signal. Therefore, Main Clock is turned ON, and the stopped bit counter 11 and slot counter 10 start operating. Thereafter, when the slot counter value becomes the value of the reception slot (STEP 2), the reception unit 1 performs reception.

[0012]

In the conventional intermittent receiving apparatus shown in FIGS. 1 to 3, in the case of intermittent reception, since Main Clock is not supplied during sleep, current consumption can be suppressed. However, since the inexpensive crystal oscillation circuit 5 is used for the BSLock for measuring the sleep interval, the error of the oscillator itself is ± 50%.
There is a problem that an error occurs in the sleep interval as large as ppm.

The error at the time of STEP 1 in FIG. 3 is caused by the BSClock having an error in the oscillation circuit 5 itself.
This represents the error from the ideal sleep interval that occurred when the interval was counted. This error remains even after the end of sleep, and as an error in STEP2, the intermittent reception interval itself has an error.

The amount of error actually occurring is determined by PHS
The case where the public reception of the standard is performed by the above method will be considered as an example. The public intermittent reception interval is 1.2 sec, but when the error of BSCLock is ± 50 ppm,
The interval can vary up to 1.2 sec ± 60 μsec. Converting this to a bit counter value, ± 23
Equivalent to a bit. Due to this BSCLock error, an operation of adjusting the self-running timing (bit counter 11, slot counter 10) to the radio wave to be received at each intermittent reception interval is required.

An object of the present invention is to provide a communication device that does not require such an operation of adjusting timing.

[0016]

In order to achieve the above object, according to the present invention, there is provided a communication apparatus for performing time-division communication at a timing of a predetermined slot interval. A reception timing control unit that counts and controls the reception timing, and an intermittent reception timing control unit that stops the operation of the reception timing control unit and counts an intermittent interval when receiving an interval,
A timing correction section for correcting the slot start timing of the reception timing control section at the end of the intermittent reception.

According to a second aspect of the present invention, the timing correction section measures an error of a control clock of the intermittent reception timing control section and corrects the error at the time of intermittent reception.

According to a third aspect of the present invention, the reception timing control section includes a slot counter section for counting slots,
A main clock generating unit that generates a reference clock that controls the slot counter unit, the intermittent reception timing control unit includes a timer unit that counts intermittent intervals,
The timing correction unit measures an error of a clock generated by the timer unit, and corrects the error at the end of intermittent reception.

According to a fourth aspect of the present invention, in the error measurement of the timing correction section, an intermittent reception state is set at the time of error measurement, the intermittent reception timing control section and the reception timing control section are operated, and The error is corrected by calculating the count value of the clock, and the error is corrected by correcting the count-up timing of the slot counter unit based on the count value at the time of intermittent reception in a normal reception period.

As described above, the timing correction unit is provided,
Since the reception timing is corrected, accurate intermittent reception can be performed even if the reception timing is measured by an inexpensive oscillation circuit.

[0021]

Embodiments of the present invention will be described with reference to the drawings.

FIG. 4 is a block diagram showing an example of the configuration of the intermittent receiver according to the present invention. In FIG. 4, components similar to those of the related art use the same reference numerals.

Referring to FIG. 4, a receiving apparatus according to an embodiment of the present invention includes a timing control unit 2 used in a conventional receiving apparatus.
Measurement control unit 1 that controls error measurement in addition to
7. Bit counter 21 that operates only during error measurement
And a correction bit counter value register 22 used for error correction. Using these, the receiving apparatus of the present invention measures the error of the BS timer that counts the BSCLock, corrects the error based on the measured value,
Control is performed so that errors do not accumulate.

First, the function of each block in measuring the error of the BS timer will be described with reference to the flowchart of FIG. 5 and the timing chart of FIG.

In FIG. 6, the horizontal axis represents time. FIG. 6 (a)
To (k) are BSLock, BS timer 9,
Main receiver power signal, error measurement flag, MainClock
k, an error measurement bit counter 21, a correction bit
It shows a counter value register 22, a slot counter 10, a bit counter 11, slots to be received, and operation timings of radio waves to be received.

In the flowchart of FIG. 5, when the error measurement is started, the error measurement control unit 17 sends an error measurement signal to the power supply control unit 12 (S102, S1).
03: STEP 3) of FIG. 6, initialize the error measurement bit counter.

Normally, at the time of intermittent reception, the power supply control unit 1
2 is to turn off the main receiving unit power supply signal and maintain the Main Clock.
Stop. However, at the time of error measurement, an error measurement signal is sent from the error measurement control unit 17 and the main reception unit power signal is kept on.

At the same time as the BS timer starts counting the sleep interval, the error measurement bit counter also starts counting (S104: STEP in FIG. 6).
4). The error measurement control unit 17 controls the error measurement bit counter 18 to perform an operation of counting 240 bits in the same 384 kHz cycle as the bit counter of the burst reception control unit in synchronization with Main Clock. At this time, the bit counter and the slot counter used at the time of burst reception are in a stopped state, as in the normal sleep mode.

At the same time when the BS timer finishes counting the sleep interval, the error measurement bit counter is also stopped (S105: STEP5 in FIG. 6), and the value is held (S106). Hereinafter, the retained error measurement bit counter value is referred to as a measurement value, and the measurement value does not change until the next error measurement signal rises.

Thereafter, the error measurement control section 17 lowers the error measurement signal, indicating that the error measurement cycle has been completed (S107: STEP6 in FIG. 6).

At the end of the error measurement cycle, in the example shown in the timing diagram of FIG. 6, the sleep interval counted by the BS timer is the ideal sleep interval.
There is an error shorter than the interval (STEP 5
reference).

End of sleep interval (STEP)
5) Thereafter, normal intermittent reception is performed, and the bit counter and the slot counter start operating.

In the present invention, at the time of intermittent reception,
The measured value obtained in the above-described error measurement cycle is reflected on the bit counter 11, the counting of the slot counter 10 is corrected, and an ideal sleep interval is obtained. The operation at this time will be described with reference to FIG.

Now, the correction operation will be described with reference to an example in which error correction is performed in the first slot at the start of operation after the end of the sleep interval. A slot for correcting an error is called an error correction slot. Also, BSLock
Is assumed to be 0, the expected measured value is called an expected value (239 in FIG. 6). By comparing the expected value with the actual measured value, the error of the BSCLock can be found.

In the error correction slot, the error is expressed as a bit
Correction is performed by reflecting the count value of the counter. The bit counter normally repeats counting up from 0 to 239, but counts up to the value set by the error measurement control unit 17 in the correction bit counter value register 22 in the error correction slot.

Here, the method of setting the correction bit counter value will be described in detail with reference to FIGS.

After the error measurement signal falls (STEP 6), the error control section 17 reads the measured value from the error measurement bit counter 21 (S108) and compares it with the expected value (S109). Thus, it is determined whether the count of the sleep interval has ended earlier or later. If the counting is completed earlier, 239+ (the difference between the expected value and the measured value) is set in the correction bit counter value register 22 (S11).
0) When the count is completed late, the correction bit
239- (difference between expected value and measured value) is set in the counter value register 22 (S110). In the error correction slot, the bit counter 11 counts up to the value set in the correction bit counter value register 22, so that the error in the sleep interval is absorbed at the end of the error correction slot.

As shown in FIG. 6, a case where the expected value 239 and the measured value 220 are considered. If there is no error, the error measurement bit counter value should have ended at 239, but the sleep interval counted by the BS timer at 220 before counting to 239 has ended and 239
−220 = This indicates that the sleep interval has ended 19 bits earlier.

In this case, the correction bit / counter value register 12 is set to 239 + 19 = 258. In the error correction slot, the bit counter 11 counts up to the value set in the correction bit counter value register. Therefore, the normal slot 239 does not become the next slot, and starts counting up to 258 which is 19 bits larger. Move to the next slot (SETP7). Thereby, 19b
The error that ended the sleep interval earlier by it is absorbed at the end of the error correction slot.

Conversely, when the measured value is 10 with respect to the expected value 239, if there is no error, the error measurement bit counter value should have ended at 239.
Continue counting up with 1, 2, 3, ..., 9, 10
Indicates that the sleep interval has ended 11 bits later. In this case, the correction bit counter value register is set to 239-11 = 228. When counting up to 228, the bit counter in the error correction slot moves to the next slot 11 bits earlier than usual.
An error that ends the sleep interval one bit later is absorbed.

Thereafter, when the slot counter value becomes the value of the reception slot (STEP 2), the reception section performs reception. By performing the above-described error correction, the slots subsequent to the error correction slot do not receive the BSCLock error, and the timing of receiving by the value of the self-running slot counter matches the ideal intermittent interval. .

It is desirable that such error measurement is performed when the power of the receiving apparatus is turned on and the receiving apparatus enters a steady state.

Next, a description will be given of a steady operation after an error is measured once to obtain a measured value and a correction bit counter value register is set, with reference to a timing chart of intermittent reception shown in FIG.

In FIG. 7, the horizontal axis represents time, and FIGS.
(I) respectively shows BSCLock, BS timer 9, main receiving unit power signal, MainClock, correction bit counter value register 22, slot counter 10, bit counter 11, and slot to be received in FIG.
The operation timing of the radio wave to be received is shown.

As in the case of the conventional intermittent reception, in STEP0, the power supply control unit lowers the main reception power, enters sleep mode,
The sleep interval is counted by the S timer. When the BS timer finishes counting the sleep interval in STEP 1, the power control unit starts up the main reception power supply, Main Clock is supplied, and the bit counter and the slot counter start operating. In the operation start slot, the bit counter performs error correction by counting up to the error correction value bit counter value (STEP 7: the same as STEP 7 in FIG. 6).
In STEP2, when the slot counter value reaches the value of the receiving slot, the receiving unit performs reception. The timing at which reception is to be performed based on the value of the self-running slot counter matches the ideal intermittent interval.

By performing the above-described error correction, there is no need to adjust the timing of self-propelled operation to the radio wave to be received at each intermittent reception interval.

In the block diagram shown in FIG. 4, an error measurement bit counter 18 that operates only at the time of error measurement is provided separately from the bit counter 11 that controls burst reception, and performs error measurement. However, the error measurement may be performed by using the bit counter 11 in a configuration also serving as the error measurement bit counter.

In the error measurement shown in FIGS. 5 and 6, after the error measurement is completed, the measured value is compared with the expected value, and the error measurement control unit 17 sets a correction bit counter value register. I have. This may be configured to be performed by the timing control unit.

In addition, the error correction described with reference to FIG. 7 is performed based on the count value of the bit counter in the first slot after the end of sleep. This may be corrected by loading a bit counter value in consideration of the correction amount at an arbitrary timing after the end of sleep.

Each of the above configurations can also be configured by a program using a CPU.

[0051]

The intermittent receiving apparatus of the present invention described above can perform accurate intermittent reception even if an inexpensive oscillation circuit having a large error is used for a timer for measuring the time of intermittent reception, thereby reducing power consumption. There is an effect that can be done.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of a conventional intermittent receiving device.

FIG. 2 is an operation timing diagram at the time of burst reception using the PHS standard as an example.

FIG. 3 is an operation timing chart at the time of conventional intermittent reception.

FIG. 4 is a block diagram illustrating a configuration of an intermittent receiving apparatus according to an embodiment of the present invention.

FIG. 5 is a flowchart illustrating an error measurement operation according to the present invention.

FIG. 6 is a diagram illustrating operation timing of an error measurement operation according to the embodiment of the present invention.

FIG. 7 is a diagram showing an operation timing at the time of intermittent reception according to the embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 reception unit 2 timing control unit 3 intermittent reception control unit 4 burst reception control unit 5 crystal oscillation circuit 6 temperature-compensated crystal oscillation circuit 9 BS timer 10 slot counter 11 bit counter 12 power supply control unit 17 error measurement control unit 21 error Measurement bit counter 22 Correction bit counter value register

Claims (4)

[Claims] 1. A communication device for performing time-division communication at a timing of a predetermined slot interval, comprising: a reception timing control unit that counts slots at said predetermined slot interval during burst reception and controls reception timing; An intermittent reception timing control unit that stops operation of the reception timing control unit and counts an intermittent interval, and a timing correction unit that corrects a slot start timing of the reception timing control unit at the end of the intermittent reception. Communication device. 2. The apparatus according to claim 1, wherein the timing correction unit measures an error of a control clock of the intermittent reception timing control unit, and corrects the error at the time of intermittent reception.
The communication device according to claim 1. 3. The reception timing control unit includes: a slot counter unit that counts slots; and a main clock generation unit that generates a reference clock that controls the slot counter unit. A timer unit for counting an intermittent interval, wherein the timing correction unit measures an error of a clock generated by the timer unit, and corrects the error at the end of the intermittent reception. The communication device according to claim 1. 4. An error measurement of the timing correction unit is performed by setting an intermittent reception state at the time of the error measurement, operating the intermittent reception timing control unit and the reception timing control unit, and measuring the count value of the main clock at the end of the intermittent reception. 4. The method according to claim 3, wherein the error is corrected by correcting the count-up timing of the slot counter unit based on the count value during intermittent reception during a normal reception period. Communication device.