JPH10256512A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a high-capacity semiconductor device by placing first to fourth decoder circuits along connections of first regions and first to fourth memory arrays and fifth to eighth decoder circuits along connections of second regions and first to fourth memory arrays. SOLUTION: Memory arrays are disposed at four divided areas of a cross area composed of the longitudinal and transverse center zones of a chip; areas A and B are at the left and right of the transverse center zone, areas C and D are the upper and lower parts of the longitudinal center zone, and area E is at the cross section of both zones. Decoders and drivers for selecting the memory arrays are disposed at the periphery of the area A adjacent to the arrays, and bonding pads are disposed at the longitudinal center areas.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device such as a dynamic RAM (random access memory) having a large storage capacity of about 16 Mbits. It is about effective technology.

[0002]

2. Description of the Related Art A dynamic RAM having a large storage capacity of about 16 Mbits has been developed.
Examples of such a dynamic RAM include, for example, pages 67 to 81 of "Nikkei Micro Devices" magazine published on March 1, 1988 by Nikkei McGraw-Hill.

[0003]

With the increase in storage capacity as described above, the size of memory chips is inevitably increased. Along with this, special consideration is required for reduction in speed due to miniaturization of elements and wiring routing. That is, to realize a large storage capacity of about 16 Mbits,
No longer about 1Mbit or about 4Mbit dynamic R
A new technical development different from the technical method used for AM is required.

It is an object of the present invention to provide a semiconductor device with a large storage capacity or a large scale integration. Another object of the present invention is to provide a semiconductor device which achieves high-speed integration and large-scale integration. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0005]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, a first region extending in a first direction along a center line crossing a short side of a substantially rectangular region of the semiconductor substrate main surface, and intersects the first region along a center line crossing a long side thereof. Providing a second region extending in a second direction, dividing the rectangular region into third, fourth, fifth, and sixth regions to provide first, second, third, and fourth memory arrays, respectively; First, second, third and fourth decoding circuits are arranged along respective tangents of the first region and the first to fourth memory arrays, and the second region and the first to fourth memory arrays are arranged. Fifth along each tangent to the memory array,
Sixth, seventh, and eighth decoding circuits are arranged, and a plurality of bonding pads provided in the second region are provided.

The third region and the fourth region are opposed to each other across the second region, and the fifth region and the sixth region are opposed to each other.
The region is opposed to the second region, the third region is opposed to the fifth region across the first region, and the fourth region and the sixth region are the first region. And a plurality of dynamic memory cells provided at predetermined intersections of a plurality of word lines and a plurality of data lines in each of the third, fourth, fifth, and sixth regions. Providing a memory array including a plurality of sense amplifiers,
A plurality of main amplifiers are arranged in the two regions.

[0007]

FIG. 1 is a basic layout diagram of an embodiment of a dynamic RAM to which the present invention is applied. In this embodiment, in order to prevent the operation speed from being reduced due to an increase in the length of various wirings such as a control signal and a memory array drive signal due to an increase in chip size due to an increase in memory capacity, and the like. The following arrangement is made for the arrangement of the memory array unit constituting the RAM and the peripheral unit for selecting an address.

In FIG. 1, there is provided a cross-shaped area formed from the vertical center and the horizontal center of the chip. A peripheral circuit is mainly arranged in the cross-shaped area, and a memory array is arranged in an area divided into four by the cross-shaped area. The cross-shaped area is divided into areas A to D as shown in FIG. That is, the area A is the left side in the horizontal center of the chip, and the area B is the right side in the horizontal center of the chip. Area C is the upper vertical center of the chip, and area D is the lower vertical center of the chip. The area E is a chip center where the horizontal center and the vertical center of the chip intersect.

In the memory chip of this embodiment, a memory array is formed in an area divided into four by the cross-shaped area including the areas A to E. Although not particularly limited, each of the four memory arrays has a storage capacity of about 4 Mbits, as described later. Accordingly, the four memory arrays as a whole have a large storage capacity of about 16 Mbits.

[0010] In the peripheral area adjacent to each memory array in the cross-shaped area, a decoder and a driver for selecting the memory array are arranged. That is, a Y (column) decoder (Yd) corresponding to two memory arrays divided into upper and lower areas in the areas A and B.
ec) and a Y select (column selection) driver (YS driver). Of the areas C and D, X corresponds to two memory arrays divided into right and left.
(Row) decoder (Xdec) and word line driver (W
L driver). Therefore, in the memory array divided into four, the word lines are extended in the horizontal direction and the data lines (bit lines or digit lines) are extended in the vertical direction. However, since one memory array has a large storage capacity of about 4 Mbits as described above, the number of memory cells connected to one data line or the like becomes enormous, which is not practical. Therefore, each memory array is composed of a plurality of memory mats as described later.

The following main circuit blocks are arranged in the remaining portions of the areas A to E of the cross-shaped area. In the areas A and B, an address buffer, an address comparison circuit (redundancy decoder), a control clock generation circuit, a data input buffer, and the like are arranged.
Area C and area D have a common source switch circuit,
A sense amplifier control signal circuit, a mat selection control circuit, a main amplifier, and the like are provided. And in the central area E,
An X decoder, an address signal generation circuit for a Y decoder, an internal step-down power supply circuit, and the like are arranged.

FIG. 2 is an overall layout diagram of one embodiment of the dynamic RAM according to the present invention.
That is, a portion corresponding to the area A includes a Y-related circuit including a Y address buffer, a Y redundant circuit, and a Y address driver (logical stage), a test function circuit, and a CAS.
A system control signal circuit is provided. Near the center of this area A, an internal step-down voltage VDL limiter circuit for receiving an external power supply voltage VCCE such as about 5 V and converting it to a voltage such as about 3.3 V supplied to the memory array, and DV1 to DV3. The illustrated Y address driver, X address driver, and mat selection driver are provided.

The portion corresponding to the area B includes an X-system circuit including an X-address buffer, an X-redundancy circuit, and an X-address driver (logical stage), a RAS-system control signal circuit,
A WE-related signal control circuit and a data input buffer are provided. Near the center of the area B, an external power supply VCCE such as about 5V is received and supplied to peripheral circuits by about 3.3V.
And a Y-address driver, an X-address driver and a mat selection driver indicated by DV1 to DV3.

As in the areas A and B, when a redundant circuit including an address buffer and an address comparing circuit corresponding to the address buffer and CAS and RAS control signal circuits for generating a control clock are arranged in one place, for example, a wiring channel In other words, sharing the clock generation circuit and other circuits with the interposition, in other words, sharing the above-mentioned wiring channel enables high integration, and also allows signals to be transmitted to address drivers (logic stages) at the shortest and equal distances. Speed can be improved because it can be transmitted.

In the portion corresponding to the area C, four main amplifiers corresponding to a total of eight memory mats symmetrically arranged with respect to the central axis of the area C, an internal boosted voltage circuit VCHG, and a substrate The voltage generating circuit VBBG and four main amplifiers corresponding to the remaining eight memory mats symmetrically arranged with respect to the center axis of the area C in the same manner as described above are provided. Therefore, in this embodiment, eight memory mats are arranged in one memory array, and a total of 16 memory mats are provided by two memory arrays arranged symmetrically with the area C as a center. become. By arranging the main amplifiers in this manner, the number of main amplifiers can be reduced, and the signal propagation distance can be shortened, so that the speed can be increased.

In a portion corresponding to the area D, four main amplifiers corresponding to a total of eight memory mats symmetrically arranged with respect to the center axis of the area D, and a data output buffer comprising four , And four main amplifiers corresponding to the remaining eight memory mats symmetrically arranged with respect to the center axis of the area D in the same manner as described above. Therefore, in this embodiment, since the memory array is constituted by four memory arrays as described above, the number of memory mats is constituted by 32 in total.

Although not particularly limited, in this embodiment, bonding pads indicated by small squares are arranged in the above-mentioned vertical center area. The detailed arrangement of the bonding pads is specifically shown in the layout diagram of FIG. In the figure, the black ones of the bonding pads indicated by □ are pads for supplying external power. That is, a total of thirteen pads VSS for supplying the ground potential of the circuit in order to increase the input level margin, in other words, to lower the power supply impedance, are arranged in a straight line.

These pads VSS are connected to ground potential leads extending in the vertical direction formed by LOC technology. Among these pads VSS, one pad provided in each of the areas C and D is used as a ground potential for clearing a word line and preventing floating due to coupling of a non-selected word line of a word driver. Area C,
Two pads provided in each of D are provided for the common source VSS of the sense amplifier, and reduce the wiring resistance of the common source to realize high-speed operation. Area D has two of the above-mentioned data output buffers, and area E has X
An address buffer and a Y address buffer are provided for supplying a ground potential and simultaneously corresponding to a power supply generating circuit. One pad is provided in each of the areas C and D, and two pads provided in the area E correspond to other peripheral circuits.

As a result, the ground potential of the circuit is reduced in power supply impedance with respect to the operation of the internal circuit, and the VSS wiring between the five types of internal circuits is separated from the LOC lead frame and the bonding wire. Connected with a low-pass filter to minimize the generation of noise, and to reduce the VSS between internal circuits.
Noise propagation can also be minimized.

The pads corresponding to the external power supply VCCE such as about 5 V are provided at two positions in the center corresponding to the internal step-down voltage generating circuits VCC limiter and VDL limiter for performing the above-mentioned voltage conversion operation, and at the positions corresponding to the data output buffer. Is provided for each. This also lowers the power supply impedance as described above, and also sets the voltages (VCC, VDL and V
This is for suppressing noise propagation between CCEs.

The address input pads A0 to A11 are
It is arranged at the center. This is intended to minimize the signal transmission distance and increase the speed by providing the X address buffer and the Y address buffer in close proximity to each other.

Control signal pads RASB, CASB,
WEB and OEB are arranged close to the corresponding circuits. Here, the letter B added to the end of each symbol
Indicates that the bar signal is a low-level active level. However, in the drawings, each symbol is represented by an overbar according to the conventional logical notation. This is the same in the following description and drawings. Data output pads DQ1 to DQ4 are provided in each data output buffer. Pad D is for data input in a × 1 bit configuration, and Q is for data output in a × 1 bit configuration. The above is the pad for the external pin.

In this embodiment, the following pads are provided for bonding master, monitor and monitor pad control in addition to the above-mentioned external pins. Pads FP0 and FP1 are provided for the bonding master. FP0 is for designating the SC (static column) mode, and FP1 is for designating the NB (nibble) mode and the write mask function in the × 4 bit configuration. Pad VCC for monitor,
There are VDL, VL, VBB, VCH and VPL.

These pads are provided with corresponding internal voltages VCC, VDL, VL, VBB, VCH and VPL.
Is for monitoring. VCC is about 3.3V
VDL is a power supply voltage supplied to a memory array of about 3.3 V, that is, a sense amplifier, and VCH is a word boosted to about 5.3 V in response to the internal voltage VDL. Line selection level, boost power supply voltage to select shared switch MOSFET,
VBB is a substrate back bias voltage such as -2V, VP
L is the plate voltage of the memory cell, and VL is V of about 3.3V.
Reference voltage for CC limiter and VDL limiter. There are pads VBT, VHT and VPLG for controlling the monitoring pads. These functions will be apparent from the description of the monitor voltage function later.

In this embodiment, the bonding pad is
They are arranged in two rows. In addition, the pitches are alternately arranged while being shifted by about a half pitch. In other words, a plurality of bonding pads are arranged in zigzag.
Thereby, the substantial interval between the pads can be increased. In other words, a large number of bonding pads can be arranged at a high density in a relatively small area.

The bonding pad requires a relatively large occupied area for bonding such as wire bonding, and the pitch thereof needs to be relatively large since it is necessary to provide an electrostatic breakdown prevention circuit. It is. Therefore, the zigzag arrangement as in this embodiment makes it possible to arrange a large number of bonding pads in a relatively small area. Further, in the configuration in which the bonding pads are arranged in the vertically central portion of the vertically long chip, a larger number of pads can be provided as described above.

FIG. 4 is a block diagram showing an embodiment of address assignment to the memory array having the above configuration. The RAM of this embodiment has a storage capacity of about 16 Mbits as described above. The address signal adopts an address multiplex system in which the X address signal and the Y address signal are supplied in time series in synchronization with the address strobe signals RASB and CASB. Therefore,
As address signals, X address signals are X0 to X11.
And the Y address signal is composed of 12 bits Y0 to Y11.

In the figure, address signals X0 to X11
Are true signals indicating a selected state when an externally supplied address signal is at a high level, and address signals X0B to X11B are bar signals indicating a selected state when an externally supplied address signal is at a low level. is there. Similarly, the address signals Y0 to Y11 are true signals indicating a selected state when an externally supplied address signal is at a high level, and the address signals Y0B to Y11
B is a bar signal indicating a selected state when an externally supplied address signal is at a low level.

The memory mat has a 2
One area SL and SR and the corresponding X decoder, word line driver, and column selection circuit as the minimum unit, and the memory array divided into four as described above has eight areas.
Memory mats are arranged in units. The memory mats of these units are MS0L, MS0R through MS3L,
It is divided into eight types like MS3R. 4 as above
Since each of the divided memory arrays has a memory mat of eight units, MS0L, MS0R to MS0L
3L and MS3R are allocated to memory mats of four units each.

The X decoder of the memory mat of the above unit has an 8-bit address signal of address signals X0 to X7, and SL, which designates two areas sandwiching the sense amplifier.
SR signal and MS0L / R designating the memory mat
To MS3L / R. One memory mat has 512 word lines. The memory mat of the unit employs a so-called shared sense amplifier system in which complementary data lines (bit lines or digit lines) are arranged on the left and right of the sense amplifier. The left and right addressing signals SL and SR are added to the address signal X.
8 and X8B are used. Therefore, the X decoder circuit has a function of substantially decoding a 9-bit address signal of X0 to X8 and performing an operation of selecting one word line.

The 3-bit address signals X9 to X11 form a mat select signal MSIL / R. That is, the address signals X9 and X9B correspond to the memory mat MS0L exemplarily shown in FIG.
And the adjacent memory mats such as MS1L and the address signals X11 and X11B are applied to the adjacent memory mats MS0L and MS1L, and the memory mats MS0R and MS1R exemplarily shown in FIG. With one memory mat as one set, one of two sets of left and right memory blocks is selected. The address signals X10 and X10B are used to select any one of the memory arrays divided by the area at the center in the vertical direction in FIG. By the combination of the address signals composed of three bits as described above, the memory mat of each unit has the eight kinds of address assignments MS as described above.
0 to 3 L / R is specified.

When an X address signal is taken in synchronism with row address strobe signal RASB, an X-system selecting operation is performed. At this time, by the address allocation as described above, one of the memory arrays divided into two with the vertical center area therebetween is selected from the four memory arrays in accordance with the address signals X10 and X10B. Is done. Then, the address signals X11 and X11B
, One of the memory mats to which R or L is added is selected, and one of the adjacent memory mats is designated by the address signals X9 and X9B.
Therefore, of the 32 memory mats in total, one word line specified by the address signals (X0 to X8) of the remaining 9 bits is selected in each of the four memory mats.

A Y decoder provided corresponding to each memory array (eight memory mats in total) decodes Y address signals Y2 to Y9 and selects a complementary data line of the memory array. That is, by decoding the 8-bit address signal consisting of Y2 to Y9, a 1/256 address selection operation is performed. However, the column selection circuit is 4
The operation of selecting a complementary data line is performed in bit units. Therefore, one memory mat is 512 × 256 ×
It has a storage capacity of four and eight memory mats are provided in one memory array.
It has a storage capacity of about 4 Mbits of 12 × 256 × 4 × 8 = 4194304. Therefore, since the entire DRAM is constituted by four memory arrays, about 16
It has a large storage capacity of M bits.

Here, the memory mats MS0L to MS0L
A set of four memory mats consisting of 3L is made up of a set of four memory mats MS0R to MS3R adjacent thereto.
Using one memory mat as another set, one memory block is constituted by a total of eight memory mats. Four main amplifiers MA are provided for this memory block.

By the row-related address determination as described above, the eight memory mats MS0L to MS3L and MS0 constituting one memory block as described above.
R to MS3R, as described above, the address signal X
One memory mat is selected by a 3-bit address signal consisting of 10, X10B and X11, X11B and X9, X9B, and the 4-bit signal is output corresponding to the four main amplifiers.

Of the Y address signals, the address signal Y0
And Y1, the above four main amplifiers AS0 to AS3
Is selected. The remaining address signals Y10 and Y11 are used to set the four main amplifier groups N
One of A0 to NA3 is selected. In this way,
Address signals Y0, Y1 and Y1 consisting of the above 4 bits
One of the 16 main amplifiers is activated by 0 and Y11, and a 1-bit read signal is output through the data output circuit.

In the case of memory access in units of 4 bits, although not particularly limited, the addresses Y10 and Y11 are invalidated, and a total of four addresses designated by the address signals Y0 and Y1 from the four main amplifier groups are set. What is necessary is just to output the signal of the main amplifier in parallel. Further, in the read operation in the nibble mode, although not particularly limited, the main amplifier can output 4 bits serially by incrementing the address signals Y0 and Y1 or Y10 and Y11 by the address.

FIG. 7 is a schematic layout diagram for specifically explaining the relationship between the power supply line, the internal power supply circuit associated therewith, and the pad. Reference numeral 1 denotes an external power supply pad VCCE, which supplies the power supply voltage to an internal step-down power supply circuit (VCC) 3 through a wiring layer. The internal step-down power supply circuit (VCC) 3 receives the power supply of the power supply voltage VCCE such as about 5 V, and receives the reference voltage VCE as described above.
Internal voltage V for peripheral circuits, such as about 3.3V according to L
Form a CC.

The voltage VCC is extended in the horizontal direction by the wiring 5 and is used for supplying an operating voltage to an address buffer, a decoder and the like. Further, the wiring 5 is branched into two at a substantially central portion and is extended in the vertical and vertical directions. This corresponds to the power supply of the X decoder, the main amplifier and the like as described above. The wiring 5 is branched and extended in the vertical direction as described above, and is also branched and extended in the horizontal direction at a location corresponding to the Y decoder and the redundant circuit.

Reference numeral 2 denotes an external power supply pad VCCE, which supplies a power supply voltage VCCE to an internal step-down power supply circuit (VDL) 4 in a wiring layer. Internal step-down power supply circuit (VD
L) 4 receives the power supply of the power supply voltage VCCE such as the above-mentioned about 5 V, and according to the above-described reference voltage VL, about 3.
An operating voltage VDL of the memory array (sense amplifier) such as 3V is formed. The voltage VDL is arranged in the shape of the sun as a whole by the wiring 6. That is, the wiring 6
The wiring is extended in the horizontal direction from the output point of the internal step-down power supply circuit (VDL) 4 and is arranged in a rectangular shape so as to surround the wiring 5 extending in the vertical direction inside. In this manner, the wiring 6 forms the above-mentioned character. Reference numeral 7 denotes a power supply pad for a data output buffer and a guard ring. The power supply pad 7 extends left and right from the power supply buffer, and is vertically arranged in parallel so as to surround a pad, a main amplifier, and the like in a vertical central portion. The upper and lower ends are formed so as to surround the entire chip. Thereby, a guard ring function is provided.

FIG. 8 is a schematic layout diagram for specifically explaining the relationship between the ground line of the above-mentioned circuit, the internal power supply circuit associated therewith, and the pad. Numerals 11 provided at the upper and lower ends of the central portion of the chip are pads VSS for supplying a ground potential for word clearing and word line latching. The pads VSS extend from the pad once in the horizontal direction and branch at a portion corresponding to the word driver. It is extended vertically. In addition, the ends extending in the horizontal direction and extending in the vertical direction at the ends corresponding to the word clear portions are connected to each other. Reference numeral 12 denotes a ground potential pad for a common source of the sense amplifier, and supplies a ground potential for activating the sense amplifier.

In this embodiment, they are arranged vertically symmetrically with respect to the horizontal center. On the upper side, the pads are provided at two locations and each extend in the horizontal direction from there, and extend in the vertical direction corresponding to the locations where the power switch MOSFETs for supplying the ground potential to the sense amplifier are provided. 13
Supplies the ground potential to the data output buffers, and is arranged corresponding to the four data output buffers.
It is composed of a number of pads and wires connecting them. 14
Is a ground potential pad for the internal step-down power supply circuits VCC and VDL and an address buffer, and is connected to a wiring extending in the horizontal direction. Reference numeral 15 denotes a ground potential pad for other circuits for supplying a ground potential to the decoder circuit and other circuits such as a main amplifier. Therefore, the circuit for supplying the ground potential has many objects and covers a wide area, so that the number of pads is as large as four, and the wiring connected to them is horizontal, as shown in FIG. It is relatively complicated in the longitudinal direction.

In this embodiment, as described above, the ground line
They are divided into one to five types according to their circuit functions, and are commonly connected by a lead frame having a LOC configuration. As a result, noise leakage between the circuits having the ground lines divided as described above is suppressed, so that the noise margin can be increased. For example, an address buffer having a strict noise margin is provided with a ground potential by an independent pad 14 and a relatively short wiring, so that a sufficient input noise margin can be secured. This is intended to substantially isolate a portion, such as a sense amplifier, which generates a relatively large noise on the ground line due to the operation thereof from the above-mentioned noise-sensitive circuit.

FIGS. 9A and 9B show a specific layout diagram and a cross-sectional view of an input protection circuit provided corresponding to the above bonding pad. In this embodiment, although not particularly limited, as is apparent from the layout diagram (A) and its partial cross-sectional view (B), a lateral type bipolar transistor of N ⁺ -PWELL (substrate) -N ⁺ is used as a protection element. Is used.

In this case, the voltage VCCE is used as the emitter.
And VSS are both used. When a high voltage (positive / negative) is applied to the input, the potential is relaxed by the lateral transistor. In this embodiment, as shown in the layout diagram of FIG. The element lowers the potential transmitted to the input gate. Although the resistance value of this high resistance element cannot be so high from the viewpoint of the transmission speed of the input signal, it is 300Ω to 500Ω.
The degree is reasonable in terms of signal transmission function and protection function.

The guard ring formed of N ⁺ provided around the NWELL (N-type well region) is for preventing an abnormal voltage of the input section from affecting the peripheral circuits. The guard ring is supplied with an externally supplied voltage VCCE. When the bonding pads are arranged at the center of the chip as in this embodiment, the memory array and peripheral circuits are more susceptible to the surge voltage than in the conventional case where the bonding pads are provided at the periphery of the chip. Therefore, the bonding pad is surrounded by a guard ring as a diffusion layer with a well as described above, and an external power supply voltage VCCE level is supplied thereto to reduce the influence of a surge voltage through the substrate.

The purpose of using a lateral type bipolar transistor as in this embodiment is as follows. Since the lateral type transistor can be reduced in area, the opposing length (base width) of the N ⁺ diffusion layers serving as the collector and the emitter
To reduce the current value per unit length to prevent current concentration, and it is not necessary to add a special process to form it.

In the figure, AL2 is a second aluminum layer, and AL1 is a first aluminum layer. Further, SiL is an opening layer for passivation, and TC is a through hole connecting the second aluminum layer AL2 and the first aluminum layer AL1.

FIG. 10 shows a specific layout of an input protection circuit provided on the external power supply voltage VCCE pad. When a high voltage is applied to the VCCE pad,
An NWELL-PWELL (substrate) -NWELL lateral bipolar transistor allows charge to escape to the ground potential VSS. This protection element is provided at the upper and lower ends in the vertical center of the chip. As a result, LOC as described later
The structure allows the high voltage to drop at the entrance of a lead running vertically in the center of the chip. By adopting such a configuration, the protection element is provided only on a pair of pads near the lead entrance, instead of providing the protection element in one-to-one correspondence with the case where a plurality of power supply pads are provided. It is possible to prevent a high voltage from being applied to the pad corresponding to the center of the lead.

FIG. 11 is a layout diagram of a peripheral portion of the semiconductor chip, and FIG. 12 is a cross-sectional view of a part of FIG. 11 and a memory cell (not shown). In this example,
As described above, a configuration is adopted in which peripheral circuits and bonding pads are arranged in the vertical and horizontal central portions of the chip. Therefore, the memory array is arranged up to the peripheral portion and the four corners of the chip.
In this case, cracks may occur in the passivation and the like at the four corners (corners) of the chip due to the stress caused by the resin of the package.

In order to prevent this, in other words, in order to increase the mechanical strength, FG (polysilicon gate electrode of MOS transistor), WSi / Poly Si (polycide layer forming complementary data lines) is provided. Then, as shown in the schematic sectional view of FIG. 12, the first aluminum layer AL1 and the second aluminum layer AL2 are overlapped with an interlayer insulating film interposed therebetween. By providing such a gradual step at the corner portion of the chip, it is possible to prevent resin-induced stress from being directly applied to the memory array portion. Further, the stress can be dispersed by increasing the lengths of FG and WSi / Poly Si at the corners.

[0052] As shown in the layout view and a sectional view of FIG. 13 in FIG. 11, the outermost periphery of the semiconductor chip P ⁺
A diffusion layer is arranged, and there is a first layer Alnuium AL1,
The substrate bias voltage VBB is supplied by the second aluminum layer AL2. And inside that is NWELL
Are arranged as guard rings, and N ⁺ for ohmic contact is formed at the center of the guard ring. The external power supply voltage VCCE is supplied thereto by the first aluminum layer AL1 and the second aluminum layer AL2.

The guard ring by NWELL is used when the voltage such as about -2 V formed by the substrate back bias voltage generation circuit VBBG suddenly changes for some reason, the substrate bias voltage VBB is applied. ⁺ Has the effect of absorbing minority (minority) carriers generated from the diffusion layer. This prevents the minority carriers generated from the P ⁺ diffusion layer from proceeding to the memory array side and combining with the information charges stored in the storage capacitor of the memory cell, thereby reducing or destroying the amount of information. can do.

FIG. 5 is a block diagram focusing on control signals in the dynamic RAM according to the present invention. This drawing is drawn corresponding to the layout diagram shown in FIG. The RAS control circuit is used to activate the X address buffer in response to the signal RASB.

The address signal taken into the X address buffer is supplied to an X-system redundant circuit. Here, a comparison with the stored defective address is performed, and it is determined whether or not switching to the redundant circuit is performed. The result and the address signal are supplied to an X-system predecoder. Here, a predecode signal composed of Xi and AXnl is formed, and each X decoder provided corresponding to the above-mentioned memory mat is provided via X address drivers XiB and AXnl provided corresponding to each memory array. Supplied to In the figure, only one driver is exemplarily shown as a representative.

On the other hand, the RAS internal signal is supplied to a WE control circuit and a CAS control circuit. For example, the RASB signal, CASB signal, and W
From the determination of the input order with the EB signal, identification of an automatic refresh mode (CBR), a test mode (WCBR), and the like is performed.

In the test mode, the test circuit is activated, and a test function is set according to a specific address signal supplied at that time. Among the address signals taken into the X address buffer, an address signal instructing selection of a memory mat is a mat selection circuit M
The data is transmitted to the SiL / R, from which one of a plurality of memory mats provided in each memory array is selected. Here, CS provided corresponding to the memory mat is provided.
Is a common source switch MOSFET.

As shown in the address allocation shown in FIG. 4, the four main amplifiers MA have four pairs of complementary data lines (4) from a total of eight memory mats provided symmetrically about the main amplifiers MA. Bit). One of the eight memory mats is selected by a memory mat selection signal MSiL / R. The unit mat control circuit UMC performs such a selection operation. In the figure, four pairs of main amplifiers MA are illustratively shown as one set.
The remaining three sets of main amplifiers are indicated by broken lines as black boxes.

The mat selection circuit MSiL / R forms selection signals MS0L / R through MS3L / R. For example, M
When S0L is formed, four memory mats corresponding to MS0L shown in FIG. 4 are selected. Each of these four memory mats MS0L has an input / output node of 4 bits, so that each of the four memory mats MS0L has the four main amplifiers MA0L.
Is supported.

The CAS control circuit outputs the signal CA
It is used for receiving various SBs and forming various Y-system control signals. The address signal taken into the Y address buffer in synchronization with the change of the signal CASB to the low level is
It is supplied to the system redundant circuit. Here, comparison with the stored defective address is performed to determine whether or not switching to the redundant circuit has been performed. The result and the address signal are supplied to a Y-system predecoder. Where Yi and AYnl
Is formed. The predecode signals Yi and AYnl are provided in a Y address driver (final stage) provided corresponding to each of the four memory arrays.
The signals are supplied to the respective Y decoders via YiB and AYnl. In the figure, one Y driver YiB,
Only AYnlB is illustratively shown as a representative.

When the CAS control circuit receives the RASB signal and the WEB signal as described above and determines the test mode from the determination of the input order, it activates the adjacent test circuit. Although omitted in FIG.
Bonding pads to which address signals and control signals are supplied are collected and arranged at the center of the chip. Therefore, the distance from each pad to the corresponding circuit can be made short and almost uniform. Thus, by adopting the layout as in this embodiment, the address signal and the control signal are fetched at high speed, and the skew generated in the multi-bit address signal in the case of the multi-bit address signal is reduced. Can be kept to a minimum.

As shown in the figure, a sense amplifier (SA)
The power supply VDL for power supply and the power supply VCC for peripheral circuits are also arranged at the center of the chip. As a result, various voltages can be supplied to the circuits arranged at the four corners of the chip at equal distances and with short wiring. Although not shown according to each circuit, capacitors having a relatively large capacitance value for stabilizing the voltage, in other words, lowering the power supply impedance are provided in the circuit along the respective power supply wirings. Can be

FIG. 6 is a block diagram that focuses on the operation sequence in the x1 bit configuration. In the figure,
Each circuit block is mainly indicated by a signal name, and a main circuit is indicated by a circuit name. Therefore, in FIG.
The signal path indicating the flow of the read signal is omitted.
Hereinafter, an outline of the operation of the dynamic RAM according to the present invention will be described with reference to FIG.

The row-related address selecting operation is performed as follows. The address signals Ai (A0 to A11) and, apart from these, especially the address signals A9 to A11 and A8,
Each is taken into an address buffer in synchronization with a row address strobe signal RASB, and held as row-related internal address signals BXi, MSiL, MSiR, SL, and SR. On the other hand, the address signal BXi taken into the address buffer is input to a redundancy circuit to determine whether or not a memory access to a defective address is made.

On the other hand, the address signal BXi is supplied to a predecoder to form a predecode signal AXNL, which is input to an X decoder X-DEC provided corresponding to each memory mat. Address signals A8 to A11
For another buffer MSi as described above.
L, MSiR and SL, SR are provided to speed up the mat selection operation. That is, the address signals A0 to A11
Is supplied to a redundant circuit and a predecode circuit, and is input to a large number of address comparison circuits and a large number of gate circuits in the redundant circuit, so that the load is relatively heavy. In this embodiment, by providing the address buffers MSiL, MSiR, SL, and SR for mat selection as described above, the influence of signal delay due to a relatively large load due to the input capacitance of the redundant circuit and the predecoder circuit is eliminated. Since it is no longer received, the speed becomes higher as described above.

X decoder X-DEC has mat selection signals MSiL / R and S which control the operation timing thereof.
X decoder precharge signal X formed from L, SR
DP and X decoder extraction signal XDG are input. X
The decoder X-DEC outputs the timing signals XDP and XDP.
The DG decodes the predecode signal AXNL to form a word line selection signal. At this time, when accessing the defective address, the signal X output from the redundant circuit is output.
RiB is formed, the operation of selecting a word line by the output of the X decoder X-DEC is inhibited, and the operation of selecting a redundant word line is performed. For such a word line selection operation, the boosted voltage VCH as described above is used. Thereby, signal charges are transferred between the memory cell and the complementary data line without level loss regardless of the threshold voltage of the address selection MOSFET having the gate coupled to the word line.

The mat select signal MSiL / R forms a complementary data line precharge signal PCB. That is, since the memory mat selected by the mat selection signal MSiL / R is determined, the precharge operation is released (finished) only to the complementary data line of the selected mat.

A selection signal SL / SR for specifying the left area SL or the right area SR of the memory mat specified by the address signal A8 is formed. This signal SL / S
A switch MOSF for selecting a region SL or SR to be coupled to a sense amplifier from R and a mat selection signal MSiL / R
A selection signal SHR for controlling ET is formed. here,
The selection signal SHR is the boosted voltage V as described above.
CH is used. Thus, signals are transmitted and received between the sense amplifier and the selected complementary data line without level loss.

The sense amplifiers control the power switch MOSFET control signals PN1 and PP generated from the RASB signal.
1, the word line selection signal and the mat selection signal MS
It is activated when the conditions of iL / R are satisfied. At this time, the sense amplifier is activated by the internally lowered voltage VDL as described above. At this time, although not shown, a two-stage amplification operation is performed to reduce the peak current accompanying the operation of the sense amplifier. That is, in the first stage, the switch MOSFET that allows a relatively small current to flow is turned on to activate the sense amplifier, and in the second stage where the amplified output is relatively large, the switch MOSFET that allows a relatively large current to flow is turned on. The state is changed to a high-speed amplification operation.

The signal RG is a signal for determining the timing for turning on the Y switch MOSFET. That is, after a sufficient signal amount is obtained on the complementary data line, the signal R
G is generated to control the timing of a column-based selection operation described later. The signals RN and RF are signals for determining the normal read mode and the refresh mode. Signal RA
If the signal CASB changes from the high level to the low level before the SB changes from the high level to the low level, the signal RF is formed and the refresh mode (CAS before RAS refresh) is set. In this case, the subsequent column-based address selection operation is omitted by the signal CE.

When the signal CASB changes from the high level to the low level while the signal RASB is at the low level, a normal mode signal RN is formed. In response, a signal CE for performing read / write control is generated. The address signal BYi taken into the Y address buffer is supplied to a Y-system redundant circuit and a pre-decoder circuit to form a pre-decode signal AYNL. The signal AC1B is a signal for controlling the operation of the main amplifier and the Y decoder system, and is generated when the address signal changes when the signal CE falls and when the signal CE is at the high level.

In the redundant circuit, signal YiB is generated when there is no repair address, and YRiB is generated when there is a repair address. If there is no defect remedy, the Y decoder Y-DEC decodes the predecode signal AYNL and decodes the Y (column).
A selection signal is formed, and if a defect relief exists, the address selection corresponding to the predecode signal AYNL is invalidated to form a relief Y (column) selection signal.

The write signal W2 is formed from the signal WEB. The signal C2 is formed from the signal CASB. This signal C
Reference numeral 2 is used for RAS / CAS logic, read / write discrimination, and control of each setup and hold characteristics. The signal W3B is a one-shot pulse for performing a read-modify-write operation and an early write operation, and an internal write pulse is generated based on the one-shot pulse.

The signal WYP is used for controlling from the data input buffer to the input / output line I / O, and the signal WYPB is responsible for controlling the complementary data line from the input / output line I / O. The signal DL determines the data setup / hold time when the write signal Din is taken into the data input buffer.
Write data DO captured in the data input buffer
i is transmitted to input / output line I / O by signal WYP.
The write signal of the input / output line I / O is transmitted to the complementary bit line (complementary data line) selected by the Y decoder circuit Y-DEC, and coupled to the complementary bit line, and the word line is selected. Is written to one memory cell.

Signal YP is an operation control signal for the Y decoder system, and signal RYP is an operation control signal for the main amplifier. Since the signal YP controls the Y-decoder Y-DEC, it is also generated during the above-described write operation. The signal RYP activates the main amplifier activation signal MA.
And RMA are formed, and the main amplifier is activated. The signal DS controls the data output timing of the main amplifier.

Based on the mutual input timing relationship of signals RASB, CASB and WEB, test mode signals RN, R
F, signals WN and WF, and signals CR and LF are formed, respectively. The signals RN and RF and the signals WN and WF are C
BR (CAS before RAS refresh), WCB
R (WE, CAS below RAS) is controlled. The signals CR and LF are used to control a test circuit, for example, the WCBR.
Set / reset the address signal Ai at the time. The address signal AFi taken into the test system circuit is converted into FMiB that determines a test mode, and generates various test signals.

As a power supply circuit, a voltage VCCE such as about 5 V supplied from an external terminal is supplied to a power supply circuit of about 3.3 V for peripheral circuits.
A step-down voltage VCC such as V is formed.
A bootstrap voltage VCH such as about 5.2 V that determines a word line selection level is formed from CC. Also,
Using this voltage VCC, a substrate back bias voltage VBB of about -2V is formed. Further, a step-down voltage VDL such as about 3.3 V for the memory array (sense amplifier) is converted from the externally supplied voltage VCCE as described above.
In particular, the step-down voltage VST supplied during standby is formed independently.

From the above operation outline, a plurality of memory mats arranged in a memory array include an X decoder for performing a word line selecting operation. As shown in the block diagram of FIG. 5, the X decoder includes a mat selection signal MSiL / R formed by a mat selection circuit MSiL / R disposed at the center of the chip, and a predecode formed by a predecoder circuit. Outputs AXNL and XiB are provided through a final driver stage. Corresponding to the respective circuits arranged in the central portion, bonding pads for address input, control signals RASB, address buffers and redundant circuits are arranged in a concentrated manner. As a result, the length of the wiring for transmitting the address signal can be reduced, so that the speed can be increased.

For example, bonding pads are arranged on both short sides of a rectangular chip like a conventional DRAM,
In the layout method in which the address terminals and the control terminals are allocated in accordance therewith, the signal transmission distance increases according to the size of the chip. In other words, the distance between the bonding pad and the input terminal of the address buffer is long and short. In addition, the distance from the address buffer to the address decoder also depends on the position of the address buffer. In such a layout method, a large storage capacity such as about 16 Mbits has been achieved because the operation speed is restricted by the longest signal path due to the routing of the signal lines and a timing margin needs to be secured. In things
The operation speed is reduced in proportion to the size of the chip.

On the other hand, in the DRAM of this embodiment, the bonding pads for address input and the bonding pads for control input are intensively arranged at the center of the chip as described above, and the address buffer is correspondingly arranged. And a control circuit provided in close proximity. In this configuration, since the signal lines extend approximately radially from the center of the chip, the signal propagation distance can be reduced to about １ ／ of the size of the chip.

The wiring resistance increases in proportion to the wiring length.
The wiring capacitance increases in proportion to the wiring length. Therefore, the signal propagation delay time is delayed in principle in proportion to the square of the signal propagation distance. Therefore, reducing the substantial signal propagation distance to 1/2 of the chip size as described above means reducing the signal propagation delay time to 1/4.

In this embodiment, the mat selection signal MSiL
A configuration is adopted in which only the memory mat of the unit selected by / R is activated. Then, the mat selection signal MSiL / R
, A signal SHR, a PCB, and a sense amplifier activating signal necessary for an address selecting operation of each memory mat are generated. In this configuration, the signal SHR as described above is interposed between a memory mat arranged at a relatively short distance from the mat selection circuit arranged at the center and a memory mat arranged at a long distance. , There is no need to provide a timing margin for the activation pulses of the PCB and the sense amplifier. In other words, the memory mat to be activated is the mat selection signal MSiL /
The operation starts at the time when R is supplied, and various signals for address selection are generated by a timing system optimized in the unit mats thereafter.

In this configuration, the mat selection circuit arranged at the center of the chip only needs to supply eight types of mat selection signals to 32 mats in the above-mentioned embodiment, so that the signal load is reduced. And the number of signal lines can be reduced. Thereby, the delay of the selection signal transmitted to each mat can be reduced. The memory mats selected as described above operate at a timing optimized for each mat, and it is not necessary to take a timing margin between the mats, so that high-speed memory access becomes possible. Further, as in the address allocation of the memory mats shown in FIG. 4, two memory mats having an axisymmetric relationship, for example, MS0L and MS1L and MS2L and MS3L constitute one sub-block. Four sub-blocks are provided for one memory array. In this configuration, only one of the two axially symmetric memory mats is activated. Thus, one control circuit can be commonly used for two memory mats.

In the sub-block composed of two memory mats as described above, one having an axially symmetric relationship between memory arrays separated by the vertical center area, for example, M
S0L, MS1L, MS2L, and MS3L may be configured as one memory block and provided with one control circuit. Also in this case, of the four memory mats MS0L, MS1L, MS2L, and MS3L as described above,
Since only one memory mat is activated, one control circuit can be commonly used as described above.
In this case, eight memory blocks are configured in the entire memory array.

The control circuit includes, for example, the precharge operation of the complementary data line, the activation of the sense amplifier, the control of the shared sense amplifier, the activation of the X decoder, the activation of the word driver, the activation of the Y decoder, and the like. It is effective as long as it forms at least one of various signals such as selection of the common input / output line I / O and selection and activation of the main amplifier. Will be possible.

When the memory array is configured as an aggregate of unit mats as described above, it is easy to change the number of operating mats only by changing the circuit of the mat selection circuit, in other words, only by changing the mat selection logic. become. As a result, product development (low power, etc.) can be easily performed. Further, an X decoder or a Y decoder for selecting a word line or a data line may be provided adjacent to a unit memory mat, or may be shared by a plurality of unit mats. In this embodiment, an X-decoder is provided for each mat, and a Y-decoder is provided for each memory array.

FIG. 14 is a basic layout diagram of another embodiment of the dynamic RAM according to the present invention. In this embodiment, in the same manner as in FIG. 1, in each of four memory arrays divided by a cross-shaped area formed by a vertical central portion and a horizontal central portion of a chip, Y
A decoder is provided. In this configuration, the Y decoder
The column selection line can be shortened because it is arranged at the center of each memory array. This makes it possible to speed up the Y-system selection operation. In response to such a configuration, a Y-based predecode signal is supplied to each Y decoder circuit through a wiring channel provided in the vertical center. It is to be noted that an X decoder similar to the above is provided on the side in contact with the vertical center portion.

Also in this configuration, the same speed as described above can be achieved by arranging a bonding pad, an input circuit such as an address buffer, a memory mat or a sub-block or a memory block selecting circuit in the center of the chip. Is achieved.

FIG. 15 is a basic layout diagram of another embodiment of the dynamic RAM according to the present invention. In this embodiment, an X-decoder is provided at the center of each of the four memory arrays divided by a cross-shaped area formed from the vertical center and the horizontal center of the chip as in FIG. In this configuration, the length of the word line in the unit memory mat is reduced by half, so that the load on the word line is reduced and the speed of the word line selection operation can be increased. In response to such a configuration, an X-based predecode signal is supplied to an X decoder circuit corresponding to each memory mat through a wiring channel provided in the X decoder section.

A Y-decoder similar to that described above is provided on the side of the chip adjacent to the horizontal center. Also in this configuration, a bonding pad is provided at the center of the chip, an input circuit such as an address buffer corresponding thereto,
By arranging a memory mat or a sub-block or a memory block selection circuit, the same high speed as described above can be achieved.

FIG. 16 is a basic layout diagram of still another embodiment of the dynamic RAM according to the present invention. In this embodiment, in the four memory arrays divided by a cross-shaped area formed by the vertical center part and the horizontal center part of the chip similarly to FIG. 1, the vertical and horizontal directions are set so that each memory array is divided into four. X and Y
A decoder is provided. In this configuration, since the word line length and the column selection line length can be halved, the load is correspondingly reduced and the word line selection and the column selection operation can be performed at high speed.

In this configuration, one of the four memory areas divided by the X and Y decoders is selected from each memory array, and the complementary data as described above is provided at the center thereof. Line precharge operation, sense amplifier activation, shared sense amplifier control, X decoder activation, word driver activation, Y decoder activation, common input / output line I / O selection and main amplifier selection A control circuit for forming various signals such as activation can be provided.

Also in this configuration, the same high-speed operation as described above can be achieved by disposing a bonding pad, an input circuit such as an address buffer, a memory mat or a sub-block or a memory block selecting circuit in the center of the chip. Is achieved. 14 to 16, the X and Y decoders may be interchanged.

Even when any of the above-described modifications of the basic layout is adopted, the memory array is divided into four by a cross-shaped area formed by the vertical and horizontal central portions of the chip, and peripheral circuits and bonding pads are formed there. Is what you do. In particular, in a configuration in which an address pad, an address buffer, a pre-decoder receiving the same, and a final-stage driver for supplying a pre-decode signal to each decoder are arranged at the center, the propagation path of a signal for memory access is vertically It extends to the four corners on the left and right with the shortest distance and at substantially the same distance. As a result, the operation can be speeded up as described above.

As the internal power supply, the operating voltage VDL of the memory array (sense amplifier) and the operating voltage VCC of the peripheral circuits are used.
The step-down voltage generating circuit for forming the circuit is also arranged at a substantially central portion of the chip. In this configuration, as shown in the embodiment of FIG. 7, the length of the power supply wiring can be reduced.
As a result, the power supply impedance can be suppressed low, so that the circuit can be speeded up and noise can be reduced.

FIG. 17 shows a basic configuration of another embodiment of a memory mat and a layout diagram of another embodiment of a memory block formed by combining the basic configuration. FIG. 17A shows a basic configuration diagram of a memory mat. In the figure, S is a sense amplifier, M
Is a memory cell array, W is a word line drive circuit (including X decoder), and C is a control circuit. In the example of FIG.
The sense amplifier S is provided on the left side of the memory cell array M. Therefore, the memory mat of this embodiment does not employ the shared sense amplifier system as in the above embodiment.

FIG. 11B shows a sub-block in which the memory cell array M is arranged symmetrically with the sense amplifier S of the memory mat as the center. In this case, the sense amplifier S may be of a shared sense amplifier type that is selectively used for the left and right memory cell arrays M, or two sense amplifiers S are arranged adjacent to each memory cell array M. It may be something. Such sub-blocks constitute a memory array as described above by combining a plurality of sub-blocks. In this configuration, by selectively performing the left and right memory cell arrays, the control circuit C can be shared.

FIG. 9C shows that the word line drive circuit W, the memory cell array M, and the sense amplifier S are symmetrically arranged vertically with respect to the sub-block of FIG. One memory block is configured by combining the memory mats shown in FIG.

In this case, each of the pair of vertically symmetrical sub-blocks may be configured in two memory arrays. In the memory cell array M (unit memory mat) divided into four, one
By allocating addresses so that one is selected, the sense amplifier S is shared as a shared sense amplifier system in which the sense amplifier S is selectively coupled to left and right memory cell arrays via switch MOSFETs. It may be common to the cell array. In this configuration, the control circuit can be shared for a memory mat including four memory mats. However, in this case, since the Y-system decoder circuit does not exist in the mat or the block, the Y-system signal circuit is excluded.

FIG. 18 shows a basic configuration of another embodiment of a memory mat and a layout diagram of another embodiment of a memory block formed by combining the basic configuration. FIG. 18A shows a basic configuration diagram of another embodiment of the memory mat. In the example of FIG. 1, a control circuit C is provided adjacent to the sense amplifier S. Further, word line drive circuits W are provided on both upper and lower sides of the memory cell array M. The word line drive circuit W selects / deselects one word line from both ends for a high-speed word line selection operation. Instead of this configuration, the word line of the memory cell array M may be vertically divided into two at the midpoint, and each of the divided word lines may be selected by the two word line drive circuits W.

In this case, by reducing the length of the word line, a high-speed word line selecting operation can be performed. Alternatively, every other word line may be selected by two upper and lower word line driving circuits. With this configuration, the pitch of the selected word line can be doubled with respect to the word line drive circuit divided into upper and lower parts. That is, by dividing a word line driving circuit requiring a relatively large occupation area into upper and lower parts, word lines arranged at a smaller pitch can be driven. The memory mat of this embodiment does not employ the shared sense amplifier system as described above.

In FIG. 10B, a memory cell array M and sense amplifiers S provided in the memory mat array M and the sense amplifiers S provided in the memory mat control circuit C are arranged symmetrically to form a sub-block. In this case, the control circuit C is shared. The control circuit C may be arranged vertically and the sense amplifier S may be shared so as to be selectively used for both memory cell arrays.

In FIG. 10C, one memory block is constituted by arranging the memory cell array M, the sense amplifier, and the control circuit C symmetrically with respect to the word line drive circuit W of the sub-block. Things. In this case, the memory cell array M divided into four
Of the (unit memory mats), those constituting sub-blocks may be configured in two memory arrays, respectively. By allocating addresses so that one memory cell array M is selected from the memory blocks, the control circuit can be shared for a memory block including four memory mats. However, in this case, since the Y-system decoder circuit does not exist in the mat or the block, the Y-system signal circuit is excluded.

FIG. 19 shows a basic configuration of another embodiment of a memory mat and a layout diagram of another embodiment of a memory block formed by combining the basic configuration. FIG. 19A shows a basic configuration diagram of another embodiment of the memory mat. In the example shown in the figure, sense amplifiers S are provided on the left and right of the memory cell array M. Therefore, the complementary data lines (bit lines) of the memory cell array M
Is split at the center. As a result, the number of memory cells on the complementary data line coupled to the input of the sense amplifier can be reduced by half, so that the parasitic capacitance is reduced, the load is reduced, and the amount of read signals from the memory cells can be increased. The speed of the sense amplifier S is increased. Instead of this configuration, a sense amplifier S may be connected to both ends of the complementary data line to amplify a read signal from both ends of the complementary data line. In this configuration, since the current of the sense amplifier is dispersed, high-speed operation and low noise can be achieved.

Sense amplifiers may be arranged left and right every other pair of the complementary data lines. In this case,
The pitch of the sense amplifier can be reduced. In other words, by distributing the sense amplifiers as described above, one sense amplifier can be formed in an area corresponding to two pairs of complementary data lines, so that the pitch of the complementary data lines can be further increased. A word line drive circuit W is provided below the memory cell array M, and a control circuit C is arranged so as to surround it.

In FIG. 11B, two memory mats are arranged symmetrically with respect to one sense amplifier S of the above-mentioned memory mats to form a sub-block. In this case, the control circuit C is shared. When the word lines of the left and right memory cell arrays are selected only alternately, a modified shared sense amplifier system may be adopted in which the central sense amplifier S is shared and selectively used for both memory cell arrays. In this case, when the sense amplifier provided at the center is used for auxiliary amplification, the input / output of the sense amplifier is directly connected to one end of the complementary data line of one memory cell array, and the switch MOSFET is connected to the other end. There is no problem even if the input and output of the sense amplifier are coupled via the.

FIG. 11C shows a memory block composed of four memory mats arranged vertically symmetrically with respect to the control circuit C of the sub-block. In this case, of the memory cell array M (unit memory mat) divided into four, those constituting sub-blocks may be configured in two memory arrays, respectively. By allocating addresses so that one memory cell array M is selected from the memory blocks, the control circuit can be shared for a memory block including four memory mats. However,
In this case, since the Y-system decoder circuit does not exist in the mat or the block, the Y-system signal circuit is excluded.

FIG. 20 shows a basic configuration of another embodiment of the memory mat and a layout diagram of another embodiment of a memory block formed by combining the basic configuration. FIG. 20A shows a basic configuration diagram of another embodiment of the memory mat. In the example of FIG. 2, sense amplifiers S are provided on the left and right of the memory cell array M, and word line drive circuits W are provided on the upper and lower sides of the memory cell array M. Therefore, the complementary data lines (bit lines) of the memory cell array M are divided at the center.

As a result, the number of memory cells on the complementary data line coupled to the input of the sense amplifier can be reduced by half. Therefore, the parasitic capacitance is reduced, the load is reduced, and the amount of read signals from the memory cells is reduced. Since the size can be increased, the speed of the sense amplifier S can be increased. Instead of this configuration,
A sense amplifier S may be connected to both ends of the complementary data line to amplify a read signal from both ends of the complementary data line. In this configuration, since the current of the sense amplifier is dispersed, high-speed operation and low noise can be achieved. As described above, sense amplifiers may be alternately arranged at both ends of complementary data lines for high integration.

The word line drive circuit W selects / deselects one word line from both ends for high-speed word line selection operation. Instead of this configuration, the word line of the memory cell array M may be vertically divided into two at the midpoint, and each of the divided word lines may be selected by the two word line drive circuits W. In this case, by reducing the length of the word line, a high-speed selection operation of the word line becomes possible. Also, word line driving circuits may be alternately arranged at both ends of the word line in the same manner as described above, so that high density word lines can be arranged.

A control circuit C is arranged so as to surround the lower word line drive circuit W of the memory cell array M and the left sense amplifier. In FIG. 2B, two memory mats are arranged symmetrically with respect to the control circuit C on the left side of the memory mat to form a sub-block. In this case, the control circuit C is shared.
When the word lines of the left and right memory cell arrays are selected only alternately, a modified shared sense amplifier system may be adopted in which the central sense amplifier S is shared and selectively used for both memory cell arrays.

In this case, when the sense amplifier provided at the center is used for auxiliary amplification, the input / output of the sense amplifier is directly connected to one end of the complementary data line of one memory cell array, and the other end is connected to the other end. Is a switch MOSFET
There is no problem even if the input and output of the sense amplifier are coupled via the.

FIG. 14C shows a case in which the control circuit C is arranged vertically symmetrically with respect to the control circuit C below the sub-block, and
It constitutes a memory block composed of one memory mat. In this case, of the memory cell array M (unit memory mat) divided into four, those constituting sub-blocks may be configured in two memory arrays, respectively. By allocating addresses so that one memory cell array M is selected from the memory blocks, the control circuit can be shared for a memory block including four memory mats. However, in this case, since the Y-system decoder circuit does not exist in the mat or the block, the Y-system signal circuit is excluded.

FIG. 21 shows a basic configuration of another embodiment of a sub-block and a layout diagram of another embodiment of a memory block formed by combining the basic configuration. FIG. 21A shows a memory cell array M arranged on the left and right around the sense amplifier S, a word line drive circuit W arranged below each memory cell array M, and arranged below the memory cell array M. FIG. 17 including the control circuit C
Sub-blocks as shown in (B) are arranged symmetrically or in parallel, and a Y decoder commonly used for the plurality of memory cell arrays M is provided on the right side.

FIG. 18B shows a case where a common X decoder is provided in the memory block shown in FIG. 18C. In this embodiment, W is simply a word line drive circuit and has no decoding function. In this embodiment, when only one word line is selected from the four memory cell arrays M, the word line driving circuit may be shared by the two memory cell arrays.

Even when the configuration of the memory mats, sub-blocks and memory blocks as shown in FIGS. 17 to 21 is adopted, it is possible to adopt a configuration in which only the unit memory mat is activated by an appropriate mat selection signal. In this manner, the signals SHR, PC, and the sense amplifier activation signal necessary for the address selection operation of each memory mat are generated for each memory mat based on the mat selection signal. In this configuration, similarly to the above, the signal SHR, the signal SHR, as described above, is provided between a memory mat arranged at a relatively short distance from the mat selection circuit arranged at the center and a memory mat arranged at a long distance. There is no need to provide a timing margin for the activation signals of the PC and the sense amplifier.

In other words, the activated memory mat starts operating when the above-mentioned mat selection signal is supplied, and thereafter activates the unit mat by the timing system optimized in the unit mat. Various signals for the conversion are generated. Therefore, the mat selection circuit arranged at the center of the chip only needs to supply a selection signal for activating any of the plurality of mats as described above, so that the signal load can be reduced and the mat can be transmitted to each mat. The number of signals and the delay can be reduced. The memory mats selected in the same manner as described above operate at the timing optimized for each mat, and it is not necessary to take a timing margin between the mats, so that high-speed memory access is possible.

FIG. 22 is a plan view of an SOJ (small outline / J-bend package) lead frame used in the DRAM according to the present invention. In the same figure, the DRAM mounted is indicated by a two-dot chain line.
Chip. A pair of leads formed so as to extend the center of the chip in the horizontal direction from the top, bottom, left and right are used as supply leads for the ground potential VSS and the power supply voltage VCCE. In this manner, the leads are arranged so as to cross the center of the chip, and are bonded at a plurality of positions to the plurality of power supply pads VSS and VCCE shown in FIG.

As the power supply terminal, as described above,
And VSS have two terminals, and the ground potential VSS and the power supply voltage VCCE are applied to the chip at a plurality of locations by a wiring material having a low resistance value such as a lead frame. The power supply impedance can be reduced. As a result, noise generated in the power supply line due to the operation current of the circuit can be reduced. The leads for transmitting and receiving signals have connection ends extending from the top and bottom of the chip toward the center in FIG. As a result, the connection to the address signal terminals and the control terminals gathered in the central portion of the chip is efficiently performed.

FIGS. 23A to 23C show examples of connection between the above-described lead frame and the semiconductor chip. In the example shown in FIG. 2A, the surface of the lead frame 22 and the surface of the chip 23 are bonded with an adhesive A
26 and an adhesive B27. And
The terminals of the lead frame are connected to the bonding pads of the chip 23 by gold wires 25.

In the example shown in FIG.
Is connected to the insulator 8 formed on the surface of the chip 23 by the adhesive C29. The terminals of the lead frame are connected to the bonding pads of the chip 23 by the gold wires 25.

In the example shown in FIG.
Is covered with the mold resin 21 except for the surface of the lead for making the connection for bonding.
0 is connected to the surface of the chip 23. The terminals of the lead frame are connected to the bonding pads of the chip 23 by the gold wires 25.

When such a lead frame is used, the lead frame can be arranged on the surface of the semiconductor chip so as to be a part of the wiring. This allows
Even if the bonding pad is arranged at the center of the chip as shown in FIG. 3, the connection to the lead can be made without any problem.

FIG. 24A is an external view of a DRAM having a LOC (lead-on-chip) structure using the above-described lead frame, and FIG. It is shown. In the figure, 31 is a mold resin, 32 is an external terminal (lead frame), 33
Is a chip. The chip 33 is bonded to the lower side of the lead via an insulating film 34 using the above-mentioned adhesive. Inside, the tip of each lead is connected to a bonding pad 38 of a chip 33 by a gold wire 35. Reference numeral 36 denotes a bus bar lead, which is used for the above-mentioned voltage VCCE and VSS supply leads. 37 is a suspension lead, and 39 is an index.

FIG. 25A shows a pin arrangement diagram of the external terminals. Although not particularly limited, the 16-Mbit dynamic RAM is housed in a 28-pin package. FIG. 2B shows a side view as seen from the side where the pins are arranged, and FIG. 2C shows a cross-sectional view as seen from the side where the pins are not arranged.

FIG. 26 shows a dynamic RAM according to the present invention having a × 1 bit configuration when a ZIP (zigzag in-line package) type is used, and a dynamic RAM having a × 1 bit configuration.
A pin layout diagram for the 4-bit configuration is shown.
In the figure, NC indicates an empty pin, and a portion indicated by an arrow in a DRAM of a × 4 bit configuration is the same signal pin as that of a × 1 bit configuration.

FIG. 27 is a cross-sectional view of the dynamic RAM according to the present invention when the SOJ type package is used.
The pin layouts of the 1-bit configuration and the x4-bit configuration are shown. In the figure, NC indicates an empty pin, and a portion indicated by an arrow in a DRAM of a × 4 bit configuration is the same signal pin as that of a × 1 bit configuration.

When a lead frame having the above-described LOC structure is used, a bus bar lead extending in the vertical direction of the chip is used for the ground potential VSS of the circuit and the DRAM is used.
On the chip side, a pad for supplying a ground potential is provided corresponding to the operation unit, and a ground potential is supplied from a plurality of locations. In this configuration, the ground potential is directly applied to the circuit for each operation unit from the low-impedance lead frame, so that a large level margin on the ground potential side can be obtained.

The other bus bar lead extending in the vertical direction of the chip uses an external voltage VCCE and corresponds to a circuit that requires it, for example, a data output buffer, internal step-down voltage generating circuits VCC and VDL. A power pad is provided. This makes it possible to lower the power supply impedance and reduce power supply noise due to internal operation. In particular, the output buffer that forms the output signal is adapted to pass a large drive current to drive a relatively large load. Therefore, by providing dedicated power supply pads VCCE and VSS for the output buffer and arranging the power supply pads close to the power supply pads, it is possible to reduce the generation of noise and to prevent the generated noise from affecting other circuits. Can be prevented.

Hereinafter, a dynamic RA according to the present invention will be described.
M will be described in detail with reference to a specific circuit diagram and its operation waveform diagram. In the following specific circuit diagram, the signal with the letter B added at the end like the signal WKB is a bar signal whose low level is set to the active level as described above.

FIG. 28 is a partial circuit diagram of an embodiment of the RAS control circuit. FIG. 70
3 shows a timing chart of an embodiment of each signal of the RAS system.

An RASB (row address strobe) signal is supplied to an input circuit having a CMOS inverter configuration.
Although there is no particular limitation on the CMOS inverter circuit for the input buffer, a P-channel MOSFET and an N-channel MOSFET having an absolute value of a threshold voltage of about 0.5 V
And an FET. By setting the conductance ratio equal, a logic threshold voltage such as about 1.6 V is provided. The power supply voltage VCC for the peripheral circuit in the DRAM of this embodiment is
The logic threshold voltage is set to 3.3 V, which is about twice the 1.6 V. This means that other control signals C
The same applies to each input buffer that receives ASB, WEB, address signals, and write data. The logic threshold voltage as described above corresponds to a TTL level signal.

The DR with a large capacity as in this embodiment is used.
In AM, the element is miniaturized. Therefore, in a circuit such as a MOSFET constituting an internal inverter circuit, in which the element constant varies, a flat portion of the channel length Lg-threshold voltage Vth characteristic is used. For this reason, the channel length Lg becomes relatively long, the threshold voltage Vth becomes relatively high accordingly, and when operating at the relatively low voltage VCC as described above, the operation speed becomes slow.

Therefore, the MOSF constituting the first-stage inverter circuit of the input buffer for which high speed is required as described above.
ET is not particularly limited, but its channel impurity concentration is determined by M which constitutes an inverter circuit used in an internal circuit.
It is set to have a low threshold voltage as described above, for example, by making it smaller than the OSFET or the like. Such a low-threshold-voltage MOSFET is similarly used in other control signal and address signal input first-stage circuits.

As described above, MOSFETs having a low threshold voltage from the viewpoint of lowering the operation speed and level are the output-stage MOSFET of the output buffer and the first-stage MOSFE of the main amplifier in the CMOS DRAM as in this embodiment.
T, a pull-up MOSFET for the input / output line I / O, a short-circuit MOSFET for the complementary data line, and a diode-type MOSFET used for the charge pump circuit. The method for obtaining the low threshold voltage as described above is as follows.
Various embodiments other than the one in which the impurity concentration of the channel is changed by the ion implantation technique as described above can be adopted.

When signal RASB is at a low level, the DRAM is activated, and when it is at a high level, the DRAM is deactivated. The RAS signal passed through the inverter circuit as the input buffer is taken into a latch circuit composed of two NAND gate circuits whose inputs and outputs are cross-connected through a NAND (NAND) gate circuit using a signal WKB as a gate control signal. .

The signal WKB is set to a high level when the level of the substrate back bias voltage VBB is shallow. Therefore, the output of the inverter circuit goes low, and the output of the NAND gate circuit is fixed at high level.
The acceptance of ASB is prohibited. That is, when the substrate back bias voltage is not sufficient, the operation of the internal circuit cannot be guaranteed, so that the RAM access is prohibited. The output of the NAND gate circuit is positively fed back to the gate of a P-channel MOSFET provided at its input.
Between the P-channel MOSFET and the operating voltage VCC, a P-channel MOSFET acting as a resistance element when a ground potential is constantly applied to the gate.
Are provided in series. Thus, once the signal RASB is taken into the gate circuit, the logic threshold voltage is shifted to the low level side, thereby making it difficult to invert the signal.

When the level of substrate back bias voltage VBB is at a desired deep level, signal WKB attains a low level. As a result, the NAND gate circuit opens the gate, and the RASB signal passed through the input buffer is taken into the latch circuit. The signal RE is a rewrite guarantee signal, and the internal RASB signal is held by the high level of this signal.

The signal R1 passed through the latch circuit is supplied to an X address buffer, mat selection, CASB, WEB, Din
Is used to control each input buffer. That is, each circuit is activated by the high level of the signal R1. R1B is its inverted signal. A delay signal R1D is formed by an inverter circuit (hereinafter simply referred to as an inverter circuit row) formed in a cascade from the signal R1, and a signal R2 is formed by the inverter circuit and the flip-flop circuit. Control of an X address buffer, which will be described later, that is, setup / hold of the X address signal is determined by the signals R1 and R1D.

The signal R2 is used for controlling the set / reset of the word line. The reset timing of the word line is delayed for compensation of the write level. A signal FUS is formed from the signal R2 using a flip-flop circuit, an inverter circuit, and a NAND gate circuit. This signal FUS is used for setting an initial value of a redundant circuit as described later. This signal FUS
Is a one-shot pulse having a constant pulse width from the signal R2, a current is supplied to a fuse for storing a defective address for a predetermined period, and a level is held in a latch circuit according to whether or not the fuse is cut. Thereby, the initialization of the defective address storage circuit is performed. Such one
By using a shot pulse, a steady DC current does not flow through a fuse that is not blown, thereby reducing power consumption.

A signal R3 is formed from the signal R2 by using an inverter circuit row and a flip-flop circuit. This signal R3 is used to control the complementary data line system (sense amplifier SA, precharge PC, shared sense SHR, etc., and redundant decoder precharge RDP. A sufficient delay is taken from the reset (R2) of the word line to obtain the complementary data line. To reset the line, the reset timing is delayed, and a signal RDP is formed from the signals R1 and R3, the NAND gate circuit, and the inverter circuit.

FIG. 29 is a partial circuit diagram showing another embodiment of the RAS control circuit. Signal WM
Is used to monitor the set timing of the word line and control the operation of the complementary data line (sense amplifier). Therefore, the signal WM is XE, XRE0B through XRE.
It is formed from RE3B. XE, XRE0B or XR
E3B is formed by a redundant circuit as described later. When the address is not a rescue address, the signals XRE0B to XRE3B are at a high level, and the signal XE is used to output a signal WM.
Is formed, and at the time of the rescue address, the signal XE is at a low level and any one of XRE0B to XRE3B is at a low level, thereby forming a signal WM.

A signal P0 is formed from the signal WM and the signal R3. The signals PN1 and PP1 are formed by delaying the signal P0, and determine the first stage amplification timing of the sense amplifier. The signals PN1 and PP
1 is used for forming a relatively large delay signal formed by a flip-flop circuit by a multiplexer circuit or signals PN2 and PP2 having a relatively small delay time formed by the multiplexer and three inverter circuit rows. These signals PN2 and PP2 determine the second stage amplification timing of the sense amplifier. The multiplexer is switched during the test mode and used to vary the peak current of the sense amplifier.

FIG. 30 is another circuit diagram showing another embodiment of the RAS control circuit. The signal PN2 is delayed by a delay circuit including a flip-flop circuit and a series of inverter circuits to form a signal RG. This signal RG determines the timing of turning on the Y (column) switch. When a sufficient signal amount is obtained on the complementary data line by the amplification operation of the sense amplifier, the Y (column) switch is opened to output a signal to the input / output line I / O.

Signal RG is delayed by a flip-flop circuit to form signal RE. This signal RG is a rewrite guarantee signal, and is used at the time of timeout of the RASB. That is, in a dynamic memory cell in which a memory cell is selected by a row-related address selection operation, the information charge of the information storage capacitor is once destroyed by the selection operation. The recovery of the retained charge is performed. Therefore, even if the RASB signal is set to a high level before the above-described rewrite is performed, the operation time of the rewrite operation is secured by the high level of the signal RE.

FIG. 31 is a circuit diagram showing one embodiment of the unit circuit constituting the X address buffer. The NAND gate circuit that receives the address signal AI supplied from the external terminal and the signal R1 forms an input buffer. That is, the NAND gate circuit opens the gate when the signal R1 becomes high level, and takes in the address signal supplied from the external terminal AI. In the input buffer having such a gate function, the logic threshold voltage is set to about 1.6 V as described above, and the operating voltage VCC is about twice as high as described above.
Set to 3V. Thus, the logic threshold voltage is set at the midpoint of the operating voltage VCC, so that the operating voltage can be used efficiently and the input level margin can be increased.

The three-state output circuit in which the output high impedance state is controlled by the signal XLB is an input gate circuit that receives the address signal AI. Signal RL
A similar three-state output circuit controlled by B is an input gate circuit that takes in the refresh address signal ARI. The address signal selectively taken in through the two input gate circuits is transmitted to the input of the CMOS inverter circuit. An address latch circuit is formed by providing a similar three-state output circuit controlled by the signal XRLB and a feedback loop between the input and output of the CMOS. From the output of this address latch circuit, internal address signals BXI and BXIB are formed through an inverter circuit and a NAND gate circuit.
Control signals XRLB, XLB and RLB for controlling the three-state output circuit are formed from the signal R1D and the signal C1.

Here, I indicates a numerical value from 0 to 11.
In other words, the circuit shown in the figure is a unit circuit corresponding to each of the address signals A0 to A11. The output of each unit circuit corresponding to the address signals A0 to A11 is supplied to an X-system redundant circuit, and is used as a comparison address signal with a stored defective address. The address signals A8 to A11 are also provided with the following address buffer circuits for forming memory mat selection signals and the like.

FIG. 32 is a circuit diagram of an embodiment of the address buffer circuit corresponding to the address signals A9 and A10. An address input circuit for receiving an address signal supplied from an external terminal, an input circuit for a refresh address signal, and a latch circuit provided in common with each other,
Since it is the same as FIG. 31, the description is omitted. From the address signal taken into the latch circuit, a mat selection signal MS0 is output by an inverter circuit or a NAND gate circuit.
B to MS3B are formed. Also, the row signal R
3, RD1 and C1 form control signals XRLB, XLB and RLB of the input gates constituting the latch circuit.

FIG. 33 is a circuit diagram of an embodiment of an address buffer circuit corresponding to the address signal A11. An address input circuit for receiving an address signal supplied from an external terminal, an input circuit for a refresh address signal, and a latch circuit provided in common with each other are the same as those in FIG. The signals BX11LB and BX11 are converted from the address signal taken into the latch circuit by an inverter circuit or a NAND gate circuit.
RB is formed. These signals BX11LB, BX1
1RB performs left / right selection of a mat to be operated. These signals BX11LB and BX11RB are N-channel MO
CMO composed of SFET and P-channel MOSFET
The signal is output via the S transmission gate circuit. The CMOS transmission gate circuit is switch-controlled by a signal RC.
A reset MOSFET receiving the signal RC is provided on the output side of the transmission gate circuit.

From the signals BX11LB, BX11RB and the signal MSIB, the mat selection signals MSLIL, MSIR
Is formed. Here, since I indicates 0 to 3 as shown, the eight types of mat selection signals are formed as described above. The control signal XRL of the input gate constituting the latch circuit is obtained from the row-related signals R3, RD1, and C1.
B, XLB and RLB are formed.

In the normal mode, signal RC is set to low level. Therefore, the right and left mat selection signals BX11LB and BX11RB corresponding to the address signals A11 and AR11 are formed via the transmission gate circuit. On the other hand, in the test mode, the signal RC is set to the high level. Therefore, the transmission gate circuit is turned off and the signals BX11LB, B
X11RB both go low. This means that the left and right mats MSIL and MSIR are simultaneously selected. Thus, the refresh cycle in the test mode is 2084 cycles, which is a half of the 4096 cycles in the normal mode in which the signal RC is set to the low level. Thus, in this embodiment, switching of the refresh cycle is enabled.

FIG. 34 is a circuit diagram of an embodiment of an address buffer circuit corresponding to the address signal A8. An address input circuit for receiving an address signal supplied from an external terminal, an input circuit for a refresh address signal, and a latch circuit commonly provided in each of the circuits shown in FIG.
1 and the description is omitted. Signals SLB and SRB are formed from an address signal taken into the latch circuit by an inverter circuit and a NAND gate circuit. These signals SLB and SRB are for generating left and right selection signals SL and SR in the selected mat. Also, the row-related signals R3, RD1 and C
The control signals XRLB, XLB and RLB of the input gates constituting the latch circuit are formed from 1 on.

The above address signals A0 to A11 are
As described above, the signal is transmitted to the gates of a number of MOSFETs, such as the address comparison circuit in the predecoder and the redundant circuit. As a result, the address buffer drives a large capacitive load, so that the signal change of the internal address signal is made relatively slow. Therefore, by providing an address buffer circuit for selecting mats for the address signals A8 to A11 as described above, the mat selection which needs to be performed prior to the word line selection can be performed at high speed, and the access time can be shortened. It is.

FIG. 35 is a circuit diagram of a part of the row predecoder according to an embodiment. Signals AXNLD and A
XNLU is for controlling the X decoder,
The upper and lower mats are selected by the address signals BX10 and BX10B.

Signals AXIH and AXIHB control the Y-system redundant decoder (sense amplifier, corresponding to repair of Y (column) selection line defect). Here, I indicates 8 to 11. The signals AXIH and AXIH
B is formed by setting / resetting a latch circuit composed of a pair of NAND gate circuits using signals BXIB and BXI. The AX10H also controls the upper and lower mats of the Y decoder, and controls the signals AYNL and YIB. Signal AXIH is RASB for controlling Y decoder.
Is latched for one cycle.

FIG. 36 is a circuit diagram showing an embodiment of an X-system redundant circuit. FIG. 72 shows a corresponding operation timing chart. The basic concept of the redundant circuit in this embodiment is as follows. Four redundant word lines are provided in each of the left and right memory areas in each memory mat. In one conventional defect remedy method for a DRAM, a redundant decoder is provided for each redundant word line in one-to-one correspondence. In this case, a device having a large storage capacity such as a large number of memory mats as in this embodiment requires an enormous number of redundant decoders.

In another conventional defect remedy method for a DRAM, fuses are provided corresponding to the enable of the redundant decoder and the address signals X0 to X7. In this state, redundant word lines are simultaneously selected in 2 ⁴ = 16 blocks that can be specified by the address signals X8 to X11, so that the efficiency of the redundant word lines is reduced and the probability that a defect exists in the redundant word lines. , The defect relief efficiency decreases.

Therefore, a fuse is added corresponding to the address signals X8 to X11 so that only one of the 16 blocks selects a redundant word line.
That is, the block (mat) in which the defective word line exists
The switching to the redundant word line is performed only by using the word line. This operation is performed by a signal XR0 provided commonly to each block.
DB to XR3DB (BX10) to XR0UB to XR
3UB (BX10B) and mat select signal (MSiL /
R, SL / SR).

As described above, the X address direction corresponds to the address X.
When four blocks of 8 to X11 are divided into 16 parts, each block has four redundant word lines, so that a maximum of 4 × 16 = 64 redundant decoders can be provided. This allows
The number of redundant decoders can be set to any number from 4 to 64 (preferably a multiple of 4). In this embodiment, twelve pieces were selected in this embodiment so that the rescue efficiency takes the maximum value (yield is maximum) among the four to sixty-four pieces. The remedy efficiency of such a defect remedy method can be made substantially equal to the case where the number of redundant word lines is 12 (the number of redundant decoders is 12) in another defect remedy method of the conventional method. That is, the number of redundant decoders is the same and the number of redundant word lines is reduced by 1 /
3 can be reduced.

In FIG. 36, the fuse FUSE
Although not particularly limited, is formed from a polysilicon layer, and is selectively cut by irradiation with a laser beam corresponding to a defective address to be stored. Fuse F above
USE is initialized through a MOSFET that is turned on by a one-shot pulse signal FUS, and is turned on by the output high level of the inverter circuit when the fuse FUSE is cut.
Is fixed to the ground potential. If the fuse FUSE is not blown, the input of the inverter circuit is fixed at a high level.

The signal FDP causes the fuse F in the upper part of FIG.
If USE is not disconnected, it means that defect repair is not performed, and at this time, the signal XRDJB becomes low level. Here, J indicates from 0 to 11, and corresponds to the number of 12 redundant decoders. Fuse FUSE for defect relief
Is disconnected, and the signal XRDJB becomes high level by the signal RDP. In the figure, the upper fuse is for enabling, and the lower fuse is for storing a defective address. The fuse for enable is cut at the time of defect relief.

The signal XRDJ goes high when the address programmed in the redundancy decoder J and the input addresses X0 to X11 match. In the figure, the signal XND
The MOSFETs to which the sources OJ to XND2J are input are N-channel MOSFETs. The signal XRDDJB is
It becomes a high level at the time of precharge, and at the time of active, among the input address signals X0 to X11, the redundant decoder J
Becomes low if there is even one bit different from the programmed address, that is, if no defect repair address is selected. The signal XRDBJ remains at the high level when all the bits match. Signal XRD
J is at the low level during precharge, and remains at the low level when no rescue address is selected.

At the time of non-repair, the fuse for enable is not cut. As a result, the signal XRDDJB is fixed at a low level, and the signal XRDJ is fixed at a low level. The signals A, B6 and B7 are used for testing a redundant word line. In the test mode, the signal STB is set to a low level. As a result, the redundant decoders of J = 0, 3, 6, 9 are set in the rescue state, and the address fuses are equivalent by the combination (0, 0) (1, 0) (0, 1) (1, 1) of X6 and X7. XR0-X
Corresponding to the four redundant word lines of R3, a redundant word line can be selected.

At this time, the address comparison circuits of I = 8 to 11 make the coincidence state irrespective of the input address, thereby selecting the redundant word lines in all the 16 blocks as described above. By doing so, it is possible to prevent the redundant word line from being tested only in one of the 16 blocks. In this embodiment, the redundant word lines are not necessarily used in their entirety, but are often not used in their entirety. Focusing on this, in this embodiment,
As described above, the redundant decoder is commonly used for selecting a redundant word line provided in a plurality of memory mats.

In this embodiment, two address comparison circuits are provided. The reason is as follows. In a conventional redundancy decoder, only one match is determined by one address comparison circuit, and upon a match, a normal word line selection path is stopped. In this method, one-stage logic is required to inhibit a normal word line selection path and a timing margin is required to prevent racing. Therefore, in this embodiment, two address comparison circuits are provided for coincidence detection and non-coincidence detection. When a match is detected, a redundant word line is selected, and when a mismatch is detected, a normal word line is selected. This reduces the one-stage logic and
This eliminates the conventional timing relationship that causes racing, and can speed up the word line selection operation.

FIGS. 37 and 38 are circuit diagrams of a decoder circuit for selecting a word line and a redundant word line. In the circuit of FIG. 37, a signal XE is a word line selection timing signal in a normal state. When the enable fuse is cut and the access is made to a part other than the defective word line, all of the signals XRD0B to XRD11B become low level. Accordingly, none of the redundant decoders of J = 0 to 11 have cut the enable fuse FUSE. In other words, the signal BX0 or BX0B becomes low level during non-rescue, so that the signal X
E is set to high level. This and signals BX0, BX1
The predecode signals XKDB and XKUB (BX1
0, BX10B). Signal W
CKDB and WCKUB are corresponding word line clear (far end of word line) signals.

In the circuit of FIG. 38, the signal XRELB
Is made by dividing twelve redundant decoders by three.
This is a signal for selecting one redundant word line. Redundant word line selection signals XRLDB, XRLUB and redundant word line clear signals WCRLDB, WCLUUB are generated by this signal and signals BX10, BX10B corresponding to the upper and lower mats.

FIG. 39 is a circuit diagram showing one embodiment of a timing generating circuit for activating a sense amplifier.
A ground potential is applied by an N-channel MOSFET that is turned on in response to a signal formed by a timing signal PN1 for performing a first-stage amplification operation from the mat selection signal MSI and the signal R3, and performs a second-stage amplification operation. A ground potential is applied by an N-channel MOSFET which is turned on in response to a signal formed by the timing signal PN2 to be turned on. A timing signal PP1 for performing the first-stage amplification operation from the mat selection signal MSI and the signal R3.
The operating voltage VDL is provided by a P-channel MOSFET which is turned on in response to a signal formed by the P-channel MOSFET. Provides operating voltage VDL.

Although not shown, the ground potential (N-channel side) and the operating voltage (P-channel side) of at least the final stage inverter of the circuit for controlling the gates of the N-channel MOSFET and the P-channel MOSFET that supply the ground potential or the operating voltage VDL Is supplied with the ground potential or the operating voltage VDL to be applied to the sense amplifier, and receives the N-channel MOSFET or the P-channel MOSFET.
When T is turned off, the power supply line is shared so that it is not accidentally turned on due to power supply noise.

N channel M which is turned on in the first stage
The OSFET and the P-channel MOSFET are adapted to supply a relatively small current by making their conductance relatively small. N-channel MOSFET and P-channel MOSF turned on in the second stage
The ET is made to supply a relatively large current by being made to have a relatively large conductance. The mat selection signal MSI (I is 0L / 0R to 3L)
// 3R) activates the sense amplifiers of four of the 32 mats.

FIGS. 40 and 41 are circuit diagrams of an embodiment of the control circuit provided in the memory mat. The circuit of FIG. 40 includes a mat selection signal MSIL / R and a signal S
The following signals are formed from L, SR and row-related timing signals R1 and R2. Here, a description will be given as a closed signal in one of the 32 mats as described above.
Therefore, the suffix I is omitted except for the signal MSIL / R. From the above signal, the X decoder precharge signal X
DPL / R, X decoder extraction signal XDGLB / R
B, forming a complementary data line precharge signal PCB.

The word line drive signal WPHL / R and the signal MS
For H, a signal level conversion is performed by a latch-type NOR gate circuit using the bootstrap voltage VCH as an operation voltage. These level-converted high-level signals are output through an inverter circuit using the bootstrap voltage VCH as an operating voltage. Therefore, in the memory mat of this embodiment, the selected word line changes from the low-level non-selection level to the boosted selection level at once. This makes it possible to increase the speed of the word line selection operation as compared with the conventional configuration in which a word line selection signal is used and a bootstrap voltage is obtained by combining the signal with a delayed signal.

The circuit shown in FIG. 41 is a decoder and a drive circuit for forming a word line WL and a redundant word line RWL selected from the predecode signal, the X decoder precharge signal XDPL / R, and the X decoder extraction signal XDGLB / RB. is there.

Since the operating voltage of the word line drive circuit uses the boosted voltage VCH as described above, the word line drive circuit linearly raises the selected word line from the low level ground potential VSS to the boosted voltage VCH as described above. It is. The shared line drive signal SHL / R formed by the selection signal MSH, SL, and SR also uses the same boosted voltage VCH as the operation voltage. Therefore, signals can be exchanged between the sense amplifier and the selected complementary data line without level loss due to the threshold voltage of the switch MOSFET.

FIG. 42 is a circuit diagram showing one embodiment of the memory cell array. The memory cell includes a capacitor for storing information and a MOSFET for selecting an address. The drain of the address selection MOSFET is connected to one of a pair of complementary data lines arranged in parallel.
The gate of the address selection MOSFET is connected to a word line. A plate voltage is supplied to the other end (plate) of the information storage capacitor. FIG. 1 exemplarily shows a pair of complementary data lines, four word lines WL0 to WL3, and redundant word lines RWL0 to RWL3.

Coupling due to overlap between a word line and a pair of complementary data lines appears on the complementary data lines in a common mode, and can be canceled by a differential sense amplifier described later. It should be noted that the complementary data lines are crossed at regular intervals and exchanged. This makes it possible to eliminate the influence of the coupling between the complementary data lines.

At the far end of the word line, a switch MOSFET for clearing the word line is provided, and the above-mentioned clear signals WCL0 to WCL3 and RWCL0 to RWCL3 are supplied. A complementary data line is coupled to an input / output node of a sense amplifier via a switch MOSFET receiving shared line drive signal SHL. The sense amplifier is configured by cross-connecting an input and an output of a CMOS inverter circuit composed of a P-channel MOSFET and an N-channel MOSFET, one of which is exemplarily shown as a representative. It should be noted that in this embodiment, the sense amplifier refers to the unit circuit as described above, and there are cases where the source of such a unit circuit is viewed in a memory mat unit in which the source is shared.

P channel M in the sense amplifier
The operating voltage VDL is supplied to the common source PP of the OSFET via the power switch composed of the P-channel MOSFET as described above, and the N-channel MOSFET
The supply of the ground potential VSS to the common source PN of the ET through the power switch including the N-channel MOSFET as described above starts the amplification operation of the sense amplifier.

In this embodiment, a column switch MOSF is connected to four pairs of input / output lines IO0, IO0B to IO3, IO3B in units of four pairs of complementary data lines.
An ET is provided. Therefore, the Y (column) selection line YS is commonly connected to the gates of the four pairs of column switch MOSFETs. Correspondingly, redundant data lines also have 4
Although not shown, four sets are provided and a selection signal Y is provided.
SR0 to YSR3 are provided.

FIG. 43 is a circuit diagram showing one embodiment of the refresh counter circuit. In the refresh mode, the CBR counter circuit counts the signal RFDB corresponding to the RASB signal as a clock.
A refresh address signal ARJ is formed. Signal CA
I is a carry input signal, and signal CAJ is a carry out signal. Twelve such unit circuits are connected in cascade to generate refresh address signals AR0 to AR11 corresponding to the address signals A0 to A11. In this embodiment, a refresh operation of a 4096-bit scan is performed.

FIG. 44 is a partial circuit diagram of an embodiment of a CAS control circuit. Also, the 75th
The figure shows a timing chart of one embodiment of the address selection operation of the CAS system. The CASB (column address strobe) signal is supplied to an input circuit including a CMOS inverter circuit. The CMOS inverter circuit for the input buffer is made to have a logic threshold voltage such as about 1.6 V as described above. The operating voltage VCC is equal to the logic threshold voltage 1.6V.
Is set to 3.3 V, which is about twice as large as the above, and corresponds to a signal of TTL level. When the signal CASB goes low, the operation of the Y-related circuit starts.

As the CASB signal passed through the inverter circuit as the input buffer, a circuit similar to the above-mentioned RASB signal is used. However, a signal corresponding to the signal WKB of the RAS circuit is omitted, and the power supply voltage VCC of the circuit is constantly supplied. Signals C1 and C2 are formed from signal CASB. The signal C1 is a nibble counter as described later,
The signals DOE, W3B, W5B and the signal CE are used for control, the signal C2B is used for controlling the signal WYP, and the signal C2 is used for controlling the signals W3B, YL and DL. The signal AC1B is formed from the signal CE, thereby forming the signals YP and RYP.

Signal AC1B is a signal for controlling the operation of the main amplifier and Y decoder system, and is generated by signal CE. One shot pulse (RYP, YP) is internally generated by the signal AC1B and reading is performed. The signal YP is
This is an operation control signal for the Y decoder system, and is also generated during a write operation. The signal RYP is an operation control signal for the main amplifier.

FIG. 45 is a circuit diagram showing one embodiment of the unit circuit constituting the Y address buffer. The NAND gate circuit that receives the address signal AI supplied from the external terminal and the signal R1 forms an input buffer. That is, the NAND gate circuit opens the gate when the signal R1 becomes high level, and takes in the address signal supplied from the external terminal AI. This signal R1 is for reducing the current in the standby state.

That is, in the standby state in which the signal R1 is at the low level, the input circuit does not respond to the signal of the address terminal AI. Even in the input buffer having such a gate function, the logic threshold voltage is set to about 1.6 V as described above, and the operating voltage VCC is 3.3 times as large as described above.
V is set. Thus, the logic threshold voltage is set at the midpoint of the operating voltage VCC, so that the operating voltage can be used efficiently and the input level margin can be increased.

A three-state output circuit in which the output high-impedance state is controlled by the signal YL is an input gate circuit that receives the address signal AI. The similar three-state output circuit controlled by the address signal fetch signal YL forms a positive feedback loop between the input and output of the CMOS inverter circuit that receives the address signal passed through the input gate circuit, and performs address latching. Perform the operation.
From the output of this address latch circuit, internal address signals BYI and BYIB are formed through an inverter circuit. A signal ACIB is formed from the internal address signals BYI and BYIB and the signal CE.

A circuit for generating signal YL is shown in FIG. 54. The Y address buffer has four operation modes in accordance with the generation mode of signal YL. The first mode is a normal mode, in which the signal YL changes in response to the CASB signal to enable a static column operation.
The second mode is a nibble mode. At this time, a signal YL is formed by the first CASB signal, and the captured address signal is held. The third mode is the CBR mode. At this time, when the CASB signal is reset to a low level afterward, a signal YL is generated to take in an address signal. The fourth mode is WCBR,
An address signal made valid between the signal R1 and the signal YL is taken in as a signal for designating a test mode.

FIGS. 46 to 49 show circuit diagrams of an embodiment of the Y redundant circuit and the predecode circuit.
This is to relieve data lines, column selection lines (hereinafter sometimes simply referred to as YS lines) and sense amplifiers.
The basic concept of the Y-system redundant circuit in this embodiment is the same as that of the X redundant circuit. That is, the block is composed of 16 blocks divided by X8 to X11. Of these, one block of defective data lines is relieved by the redundant data lines. Accordingly, the address signals AX8H, AX8HB to AX11, AX1
1B is input.

Corresponding to four pairs of input / output lines I / O, four pairs of complementary data lines are selected in one column selection line. Therefore, repair is performed in units of four pairs of complementary data lines. Therefore, since addresses Y0 and Y1 are degenerated,
No fuse corresponding to addresses Y0 and Y1 is provided. Further, no fuse corresponding to the addresses Y10 and Y11 degenerated in the × 4 bit configuration or the nibble mode is provided. Therefore, four redundant YS lines appear simultaneously in one block. In an actual layout, one block is divided into four (Y10, Y11) in the word line direction, and is distributed and arranged in the chip in the longitudinal direction. This will be apparent from the block address allocation shown in FIG.

In the 64-bit simultaneous test mode as described later, the addresses Y2 and Y3 are further reduced. However, if the fuses corresponding to the addresses Y2 and Y3 are also eliminated, 16 redundant YS lines are simultaneously output in one block. That is, 64 × 16 (number of I / Os) redundant data lines are simultaneously repaired, and a large number of redundant data lines must be prepared, resulting in poor efficiency. Therefore, for the addresses Y2 and Y3, only the YS line corresponding to the complementary data line having the actual complementary data line failure is switched to the redundant YS line during the 64-bit simultaneous test, and the normal YS line is selected for the rest (address Y2). And multi-selection of 4YS lines by Y3 degeneration). This eliminates the need to prepare four times the number of redundant data lines despite the provision of the YS multi-selection 64-bit test mode.

Since the YS line extends over a plurality of blocks as described above, if a YS line failure occurs, a data line failure occurs in a plurality of blocks belonging to the same YS line. If a redundant decoder is allocated for each block in order to remedy this, the number of redundant decoders becomes large and the relief efficiency decreases. In order to prevent this, two fuses are provided for each of the block division addresses X8 to X11. When the lower fuse FUSE is cut, comparison of the corresponding X address is not performed. In this way, for example, the lower fuses FUSE of X8, X9, X11
Is cut, eight blocks belonging to one YS line are degenerated and can be repaired by one redundant decoder, thereby improving efficiency. Similarly, if the lower fuse FUSE of only X8 is cut off for the sense amplifier failure, the left and right data lines of the sense amplifier can be relieved by one redundant decoder.

In FIG. 46, the upper circuit corresponds to enable, and the lower circuit corresponds to addresses Y4 to Y9. In FIG. 47, the upper circuit is an address Y
2, Y3, and the lower circuit corresponds to addresses X8 to X11. The fuse FUSE is initialized through a MOSFET that is turned on by a one-shot pulse signal FUS, and is fixed at the ground potential by a MOSFET that is turned on by the output high level of the inverter circuit when the fuse FUSE is cut off. . If the fuse FUSE is not blown, the input of the inverter circuit is fixed at a high level.

At the time of repair, when the address programmed in the redundant decoder matches the input address, signal RDJ goes high, and when they do not match, signal RDJ rises.
Goes low. At the time of non-relief, the signal RDJ
Is fixed to the low level. At the time of the 64-bit simultaneous test, the signal YMB goes low, and the signals YFIJ, YFI
FIJB outputs the state of the fuse corresponding to addresses Y2 and Y3. The addresses Y2 and Y3 are not compared (reduced). When testing the redundant data lines, the addresses X8 to X11 are degenerated. Address Y2 and Y3
Corresponds to (0,0) (1,0) (0,1) (1,1), the redundancy decoders of J = 0,3,6,9 are in a rescue state, and four redundant YSs are provided. Corresponds to the line. This is the same configuration as the X redundant circuit.

In FIG. 48, signals RD0-RD2, R
D3 to RD5, RD6 to RD8, and RD9 to RD11 correspond to the redundant YS line selection signals YRD0B to Y, respectively.
RD3B is formed. When the signal YRD is set to the high level, the normal selection of the YS line is inhibited during the redundancy selection. However, during the 64-bit simultaneous test, the signal YMB
, The signal YRD is fixed at the low level, and the normal YS line is selected at the same time.

Signals RA0JB to RA3JB monitor the state of fuse FUSE corresponding to addresses Y2 and Y3. In the normal mode, the signal YMB is fixed at a high level by the high level. In the 64-bit simultaneous test, when the rescue address is selected, the state of the fuses of the addresses Y2 and Y3 is decoded by the high level of the signal RDJ, and one of the outputs is set to the low level (the defective addresses Y2 and Y3 of the defective address). Pre-decode signal).

Signals RY20B to RY23B have J = 0 to
Of the twelve sets of redundant decoders, Y2 and Y
When the addresses except for the addresses Y3 and Y3 match and the addresses different only in Y2 and Y3 have been rescued, the signals RY20B to RY23
An OR (OR) logic of J = 0 to 11 is adopted so that two or more of B can be set to a low level.
That is, for example, when two of the four YS lines degenerated at the addresses Y2 and Y3 have been rescued, the two are used to distribute the redundant YS lines and the remaining two to the normal YS lines. .

In order to check the redundant YS line, in other words, to select the redundant YS line in the test mode and perform a write / read test on a memory cell provided there, an address signal is selected. It is necessary that the redundant YS lines (YSR0 to YSR3) be selected for any of the addresses X8 to X11.
Two bits of address signals Y2 and Y3 are used for designating a redundant YS line. That is, the signal BI (I = 2,
STB (redundancy test signal) or VCC is supplied to 3) and A (corresponding to the redundancy decoders of L = 8, 9, 10, 11). Thereby, it is the same as equivalently cutting the fuse by the address signal in the test mode without cutting the fuse of the defective address, and the operation of selecting the redundant YS line specified by the address can be performed. It will be. This circuit is basically the same as the X-system redundant circuit, and a detailed description of each signal will be omitted.

The defect remedy method according to the present invention will be described from another viewpoint as follows. FIG. 91A is a conceptual diagram for explaining an example of defect remedy in the multi-bit simultaneous test mode by the Y-system multiple selection from another viewpoint. In the figure, the horizontal axis indicates the X address, and the vertical axis indicates the Y address. When a RAM having a storage capacity of about 16 Mbits is constructed as in this embodiment, X has 4096 addresses, and Y has 4096 addresses. In the conventional defect rescue technique, switching to a redundant circuit is performed for one defective address of X and Y.

Therefore, for example, if there is a defect in one Y-system address, access to a bit line to which 4096 memory cells provided there are coupled is prohibited, and
In this configuration, 96 memory cells are switched to redundant bit lines which are similarly coupled. In this case, since the scale of the redundant circuit becomes large, the X and Y addresses are divided into four by using the upper two bits of the X-system address and the upper two bits of the Y-system address in the embodiment of FIG.
6 memory blocks so that a data line can be specified for each block.

In the above-described multi-bit simultaneous test, or when the upper 2 bits of the Y-system address are degenerated into a × 4 bit configuration, the Y-system is multi-selected. Therefore, in the case where at least one defect exists, the conventional defect remedy method switches all the circuits to the redundant circuit.
Then, it is necessary to switch the bit line having no defect to the redundant bit line only for the Y-system multiple selection test or for the x4 bit configuration. Therefore, as shown by the dotted line in FIG. 3, when four addresses are simultaneously selected for the Y system, only the block in which the defective bit line or the YS selection line exists is switched to the redundant bit line RBL, and the remaining three bits selected simultaneously are selected.
The bit line corresponding to the address is a normal bit line NBL
Is to be selected. With the above-described block configuration, the bit lines are not selected in the other memory blocks divided by the X address.
With such a configuration, only those having a defect are switched to redundant bit lines, so that the number of redundant bit lines to be prepared can be significantly reduced.

FIG. 91B is a conceptual diagram for explaining another embodiment of the bit line defect remedy in the normal mode. In the example of FIG. 3B, of the four lines divided by the X address among the bit lines belonging to the same Y address, only the defective block is switched to the redundant bit line RBL, and the other blocks are Normal bit line NBL is selected. Such a defect remedy in block units can reduce the number of redundant bit lines or YS selection lines to be prepared.

FIG. 91 (C) is a conceptual diagram for explaining another embodiment of the word line defect relief in the normal mode. In the example of FIG. 10C, of the four blocks divided by the Y address among the word lines belonging to the same X address, only the defective block is switched to the redundant word line RWL, and the other blocks are replaced by the redundant word line RWL. Normal word line NWL is selected. By such a block-based defect remedy, the number of redundant word lines to be prepared can be reduced. However,
In a DRAM in which an X address signal is multiplexed and input prior to a Y address signal as in this embodiment, the above Y address signal is used.
The address signal cannot be used as it is. Therefore, a defect remedy method similar to the above can be realized by internally programming an address which can be called a block address equivalent to the Y address by using a fuse means similar to the above.

FIG. 49 is a circuit diagram showing one embodiment of a partial predecoder circuit of the Y system including a circuit for forming a selection signal for the main amplifier. Signal ASK (AS0-AS
In 3), a group of men amplifiers is selected (one pair of four pairs of I / O lines is selected). Signal AY20U / D to AY2
3U / D performs pre-decoding of addresses Y2 and Y3. It is divided into upper and lower mats by the address X10. At the time of a 64-bit simultaneous test, the Y
2 and Y3 are ignored, and the signal R in FIG.
Y20B to RY23B are output with the same logic.

Signals Y0UB to Y3UB, Y0DB to Y3
DB predecodes addresses Y4 and Y5, and outputs a signal Y
This is a predecode signal output according to P, which is a data line selection timing. The signal CE defines the reset timing. Signals Y0UB to Y3
UB, Y0DB to Y3DB become high level when the signal YRD is high level, and inhibit the selection of the normal YS line.

In the 64-bit simultaneous test, the address Y
If the 4YS line degenerated by 2 and Y3 is not repaired, the signal AY
Although four lines of 20U / D to AY23U / D become high level and four YS lines are selected, one to four of the corresponding AY20U / D to AY23U / D are not output when being rescued. Instead, one to four redundant YS lines are selected,
The redundant YS line and the normal YS line are simultaneously selected. AY6
0U / D to AY83U / D are predecode signals of addresses Y6 to Y9. Signals YR0U / DB to YR3U
/ DB selects the redundant YS line. This is the signal Y0U
/ DB to Y3U / DB.

FIG. 50 shows a unit circuit of the Y decoder and a redundant YS line selection circuit. The predecode signal as described above is decoded by a three-input NAND gate circuit. This decoded output and Y selection timing signal YK
UB (K = 0 to 3) are supplied to the NOR gate circuits, and the column selection signals YS0 to YS are output from the respective NOR gate circuits.
S3 is formed. From the signal formed by the redundancy decoder circuit, a column selection signal YSR0 to YSR for redundancy is used.
3 is formed.

FIG. 51 is a circuit diagram showing one embodiment of the nibble counter circuit. In the normal mode, an address signal NAK corresponding to the internal address signal BYI is output. In the nibble mode, the internal address signal BYI in the first cycle is counted up first. When memory access is performed in a × 4 bit configuration, the signal NAK is fixed at a high level (VCC) by the master slice shown in the form of a switch.

FIG. 52 is a circuit diagram showing one embodiment of a control circuit for forming a Y-system control signal. Signal MA is a main amplifier operation control signal. The signal DS is a signal for controlling data output of the main amplifier. The signal MA is generated with the generation of the signal AC1B (RYP). The signal R1 determines the reset timing of the main amplifier. The signal DS is generated by the signal MA. Signal C
1 and R1 perform the reset. That is, the control of the data output of the main amplifier is performed by using RASB and C
The reset is performed at both the high level and the ASB.

A signal WR is a read / write discrimination signal. The first stage is controlled by a signal R1 to reduce current consumption in a standby state. The signal DOE controls the data output buffer and is generated in the read mode. In the case of a × 1 bit configuration, the signals C1 and WR
It is generated by the logical product of In the case of a × 4 bit configuration, it is generated by a logical product of the output enable signals OE, C1, and WR. As a measure against the hold time t _OEH (signal OE hold time from the signal WE), the WE-related signal DL is used.
Thus, the control signal OEB is latched.

FIG. 53 is a circuit diagram of an embodiment of the operation mode determination circuit. Signal RN, RF and signal W
N and WF control the normal operation, the CBR operation, and the WCBR operation. The signals RN and RF are the signals CE and YE
, And the signals CRB and LFB control the test system circuit, specifically, set / reset the address at the time of WCBR.

FIG. 54 shows an embodiment of a part of the Y control circuit. The signal YL corresponds to FIG.
The address latch is performed for the Y address buffer as shown in FIG. As described above, the generation timing and the like differ depending on each operation mode. An example of the operation waveform is shown in FIG. In response to the high-speed page mode (normal mode), the Y address is latched in synchronization with the signal CASB. For the nibble mode, the Y address is latched during the RAS cycle.
The reason is that in the nibble mode, the address signal is generated in the nibble counter. In the static column mode, the Y address is latched only at the time of writing. CB
In the counter test mode at the time of R, the Y address is latched. In the WCBR mode, the Y address is latched during the RAS cycle.

Signal DL controls setup / hold of data in the data input buffer. In high-speed page mode or nibble mode, CASB is low level and W
EB is set at a low level and reset at a high level of CASB. In the static column mode, it is set by the low level of CASB or the low level of WEB, and reset at the end of the write operation. Signal O
LB is a signal for latching so that the written data is not output to DO. This corresponds to a read-modify-write operation. In the static column mode, it corresponds to t _WOH (output hold time from the signal WE).

FIGS. 55 and 56 show some embodiments of the WE control circuit. In FIG. 55, a WEB (write enable) signal is supplied to an input circuit composed of a CMOS inverter circuit. The CMOS inverter circuit for the input buffer is made to have a logic threshold voltage such as about 1.6 V as described above. The power supply voltage VCC for the peripheral circuits in the DRAM of this embodiment is set to 3.3 V, which is about twice the logic threshold voltage 1.6 V, and corresponds to a TTL level signal.

Signals W1 and W2 control the write operation. In the standby state, W1 and W2 are set to low level. During operation, the signal changes in synchronization with a change in the signal WEB. The signal W1 is based on the RAS / WE logic control (W
N / WF), and the signal W2 performs CAS / WE logic control. The write set is delayed to secure t _ASC (column address setup time). The signal W3B is a one-shot pulse formed by the signal W2, from which the signal W4B is formed.

Referring to FIG. 56, a signal WYP controls a write signal from the data input buffer to the input / output line I / O, and a signal WYPB controls a write signal from the input / output line I / O to the bit line. Control. The signal IOU precharges the input / output line I / O after the write operation. This is to cope with the next read cycle. The signal WL latches addresses and data in the static column mode. FIG.
FIG. 6 shows a timing chart of an example of the write operation.

FIG. 57 is a circuit diagram showing one embodiment of the data input buffer. The input circuit is constituted by a NAND gate circuit and has the same logic threshold voltage as the other input circuits. Control signal A of this gate
Is one of four input buffers in the × 1 bit configuration.
One is the signal R1, and the other three are the circuit ground potential VSS.
Is substantially nullified. ×
When used in a 4-bit configuration, signal A is signal R1 corresponding to all four input buffers. The reason why the NAND gate circuit is used for the input portion of the input buffer to be activated and the signal R1 is supplied thereto is to reduce the current consumption in the standby state as described above. The setup / hold of write data is controlled by the signal DL. The signal MKI is used for control of the write mask mode in a × 4 bit configuration. Signal RASB
Write / non-write control is performed by the data of the signals DQ1 to DQ4 at the time of setting. The signals DI (0 to 3) are
It is further divided into nibble address NAI units.

FIG. 58 is a circuit diagram of an embodiment of a main amplifier control circuit, and FIG. 59 is a circuit diagram of an embodiment of a main amplifier. Signal RMA is a timing signal for controlling the operation of the main amplifier. Signal WM
A controls signal transmission (write operation) from the data input buffer to the input / output line I / O. Signals ILAij to ILC
ij is for pulling up the input / output line I / O, and the signal IOU is a signal for shorting the input / output line I / O.

In the normal mode, 1 is set by the signal RMA.
Operate the main amplifiers. In one test mode, 16 main amplifiers are simultaneously activated by the signal TE, and a 16-bit batch comparison operation is performed. Further, in another test mode, the signals TE and YMB provide
A multi-selection of the YS line performs a 64-bit batch comparison operation.

FIG. 89 (A) is a circuit diagram illustrating the principle of a multi-bit test using a 4-bit parallel test by a pair of main amplifiers as an example. In other words, the 16 main amplifiers are divided into 8 pairs according to the example of FIG. 1, and two I / O line pairs corresponding to those pairs are each multiplied by four YS lines into two pairs of four bits. A total of 64 bits of multi-test is performed by transmitting read data consisting of a total of 8 bits in one I / O line pair in parallel to the eight pairs of main amplifiers.

Referring to FIG. 89 (A) as an example, one input of a pair of main amplifiers MA has complementary bit lines BL1 and BLB corresponding to a read signal of 4 bits.
1 to BL4 and BLB4 are Y switch MOSFETs
And I / O lines I / O and I / OB. A reference voltage VR is supplied to the other input of the pair of main amplifiers MA.

The reference voltage VR is set at an intermediate level between the high-level read signal and the signal when one bit does not match, as shown in the waveform diagram of FIG. That is, as shown in the figure, the complementary bits BL1 and BLB1 are at logic "0" (BL1 is low level "L" and BLB
1 is at a high level “H”), the level of the input / output line I / O is determined by setting the level of the Y switch MOSFET (M2) and the sense amplifier
As much as the FET (M3) is connected, the level is lowered according to the conductance ratio as shown by the dotted line in FIG.

Therefore, the reference voltage VR is connected to the pull-up MOSFET (M1) by the Y switch MOS.
Two FET (M2), MOSFET of sense amplifier
(M3) are connected in series, and are set at an intermediate level between the high level and the low level when one bit does not match. Therefore, in the embodiment shown in FIG. 89, all bit logic "1"
And the output signal of the main amplifier corresponding to the input / output line I / O of the pair of main amplifiers changes from the high level to the low level, and corresponds to the input / output line I / OB The output becomes the same low level as that of the output of the main amplifier, and an error is detected.

Contrary to the above case, when logic "0" is written in all four bits and read out, and when all bit logic "0" is read out, the input / output line I
When the / OB side becomes high level and even one bit does not match as described above, the level of the input / output line I / OB is lowered in the same manner as described above. The output signal of the main amplifier changes from the high level to the low level, becomes the same low level as the output of the main amplifier corresponding to the input / output line I / O, and detects an error. When all bits match, the outputs of the pair of main amplifiers are divided into a high level and a low level.

In such a multi-bit test,
For example, in the state shown in FIG. 89, the input / output line I / O
B tends to be set at a relatively low level by supplying the low levels of the outputs of the three sense amplifiers. As a result, the bit line BL having the defective read
The low level of the input / output I / OB is transmitted to B1, and there is a possibility that the sense amplifier is reversed and normal data is written to the defective read bit line. As a countermeasure, in the multi-bit test mode, the conductance of the pull-up MOSFET (M1) is increased. Specifically, in the multi-bit test mode, a pull-up MOSFET that is turned on by that signal
Is provided. Thereby, the input / output lines I / O and I
The above-mentioned erroneous writing can be prevented by lowering the low level drop of / OB.

Alternatively, in the case of the above-described multi-bit test, the operating voltage is switched from VCC to VCCE such as about 5 V or boosted voltage VCH by the switch MOSFET turned on by the control signal. In this configuration, since the level of the input / output line can be relatively increased by an amount corresponding to the voltage switching, erroneous writing due to the low level as described above can be prevented. Further, the threshold voltage of the pull-up MOSFET may be set to a low threshold voltage, and the pull-up level (bias level) of the input / output line may be increased by that amount. That is, in the case of operating at a low voltage VCC such as about 3.3 V as in this embodiment, if the threshold voltage of the pull-up MOSFET is large, the above-described pull-up level becomes low, and the low level for preventing erroneous writing. This is because the margin becomes smaller.

In the embodiment shown in FIG. 54, two I / O line pairs originally connected to the above two main amplifiers are connected to each other by Tru (True) and Bar (Bar). Is shared in the above-described embodiment. This prevents the number of May amps from doubling. 4 bits for each I / O line pair, total 8
The bits are compared by the above eight pairs of May amplifiers to realize a 64-bit simultaneous test. By adopting the multi-bit test as described above, it is possible to reduce the test time of a RAM having a large storage capacity such as about 16 Mbits. In the write mode, a signal from the data input buffer is applied to the input / output line I /
At the same time, the data is also written to the main amplifier by the signal RMA. This corresponds to the nibble mode and the high-speed page mode.

FIG. 60 is a circuit diagram of an embodiment of a data output control circuit of the main amplifier. Main amplifier output groups MAi0-MAi3, MAi0B-MAi
3B are main amplifier selection addresses AS0 to AS3.
AS3, and nibble address NAi
The output group selected by signal DS is output line MO by signal DS.
sent to iB, MOi. Thus, one main amplifier is selected from the 16 main amplifiers.
× When output in 4-bit units, nibble address NAi
Is fixed at a high level. The signal DS is reset by the RASB / CASB reset in the high-speed page mode. In the nibble mode, the signal DS remains at the high level because it is only necessary to input data to the four main amplifiers in the first cycle and to output the fetched data from the main amplifier from the second cycle. In the test mode in which the signal TE is formed, the data of the four main amplifiers is output to one output signal MO through a comparison circuit (a NAND gate).
Put together in i.

FIG. 61 is a circuit diagram showing one embodiment of the output control circuit of the main amplifier. Signal OLB controls data output to the data output buffer. Lead
Performs data latch by modify write. Signal T
E activates all 16 main amplifiers in the test mode and outputs their output signals MO0 to MO3 to MO0.
B to MO3B to output data. The comparison output method includes a binary value and a ternary value.

In the binary system, a high level / low level is output to the output DO / DOB when all logics are "1" or logic "0", and a low level / high level is output when fail occurs. In the ternary system, a high level / low level is output to the output DO / DOB when all logic is "1", a low level / high level is output when all logic is "0", and a low level / low level is output when fail. When the signal TW is at a high level, the above-mentioned binary output method is used. When the signal TW is at a low level, the above-mentioned ternary output method is used.

FIG. 62 is a circuit diagram showing one embodiment of the data output buffer. The data output buffer is provided with a level conversion circuit at its input. As described above, the internal circuit operates with the reduced voltage VCC. Therefore, the read data transmitted through the main amplifier is formed by the operating voltage VCC. Signal D
The data passed through the NAND gate circuit by the OE is level-converted to a latch-type NOR gate circuit operated by a power supply voltage VCCE supplied from the outside. By providing such a level conversion circuit and driving the push-pull output section composed of the N-channel MOSFET, the output level on the high level side can be increased, and the amplitude of the drive signal increases, so that the speed can be increased. .

The output section is provided with a MOSFET for controlling the gate of the output section MOSFET and a resistance element.
It is provided between the gate and the source of the output MOSFET on the power supply voltage VCCE side.
The threshold voltage of the MOSFET given SS is made lower than the threshold voltage of the output MOSFET. Thus, when the output terminal DOUT has a negative potential, the MOSFET having the low threshold voltage is turned on to short-circuit the gate and the source of the output MOSFET. This allows the output MOSFET to be driven by the negative voltage as described above.
Is never turned on.

An output circuit which operates at a relatively early timing through the output gate circuit is separately provided, whereby the rising and falling timings of the output signal are advanced. Then, the level is changed to a level specified by an output circuit that receives data passed through the level conversion circuit. By adopting such a configuration, it is possible to linearly change the output level for a relatively long time while increasing the speed, and noise generated on the power supply line and the ground line due to the change in the level of the output signal. The level can be reduced.

FIGS. 63 and 64 are circuit diagrams of one embodiment of the test circuit. A test function is set at the timing of WCBR. This WC
The BR outputs a test signal corresponding to the fetched address. A signal LFB is formed by the WCBR, and an external address signal can be captured. Signal FR
Resets all to logic "0" at power-on.

The reset of the test function is RAS
This is performed by resetting all the addresses to logic "0" by setting the signal FR to the high level during the precharge period of the RASB signal by the only refresh and CBR refresh cycles. The test mode includes four of AFI to AFL corresponding to address signals Y0 to Y3.
The following modes are prepared according to the signal FMNB formed from a combination of bits. (1) × 16-bit test, (2) × 64-bit test, (3) The internal voltage VCC is switched to the external voltage VCCE. (4) Internal voltage VCC monitor, (5) Internal voltage VDL monitor (6) 2
048 refresh (8192 bit operation), (7) redundant area test, and (8) high speed test.

FIG. 65 is a circuit diagram showing one embodiment of a control circuit for designating an operation mode. By selecting the high level / low level and high impedance for the bonding pads FP0 and FP1, the following modes are respectively selected from the combination according to the × 1 bit configuration and × 4 bit configuration specified by the aluminum master slice. Is set.

In a × 1 bit configuration, pads FP0 and F
When both P1 are at high impedance, the signals SC and NB are both at low level, and the high-speed page mode is designated. When the pad FP0 is set to low level and the pad FP1 is set to high impedance, the signal SC becomes high level, and the static column mode is designated. Pad FP
When 0 is set to high impedance and the pad FP1 is set to high level (VCCE), the signal NB is set to high level and the nibble mode is designated.

In the × 4 bit configuration, pads FP0 and F
When both P1 are at high impedance, the signals SC and NB are both at low level, and the high-speed page mode is designated. When the pad FP0 is set to low level and the pad FP1 is set to high impedance, the signal SC becomes high level, and the static column mode is designated. Pad FP
When 0 is set to high impedance and the pad FP1 is set to a high level (VCCE), a signal WB is formed, the write mask mode is set in the high-speed page mode, the pad FP0 is set to the low level, and the pad FP1 is set to the high level (VCC
In the case of E), the signal WB is formed in the same manner as described above, and the mode becomes the write mask mode in the static column. In the write mask mode, a pin to be written from the output terminal I / O can be set by setting the WE signal to a low level when the RAS signal falls.

FIG. 66 is a circuit diagram showing another embodiment of the control circuit. The signal WKB monitors the level of the substrate bias voltage VBB. When the substrate bias voltage VBB falls below about -0.7 V, the signal WKB goes low. If the substrate bias voltage VBB is shallow, MOS
Since the threshold voltage of the FET is lowered, a relatively large through current flows due to the circuit operation and latch-up easily occurs, so that the high level of the signal WKB inhibits the access to the RAM. The signal INT is the power supply voltage VCC.
Monitor the level of E. When the voltage VCCE> 3V, the signal INT is set to the low level. In other words, when the external power supply voltage is low, the internal initial state is set by the signal INT.

In this embodiment, a specific configuration of the delay circuit shown by a black box is shown. This circuit delays a signal from low level to high level. When the terminal SET is set to a high level (VCC), the delay amount can be reduced. These are widely used for RAS timing adjustment, CAS and WE pulse generation, and the like.

Output terminal Q / DQ4 is used as an internal voltage monitor terminal. With the data output buffer coupled to this terminal in the output high impedance state, the operating voltage VCC for the peripheral circuit is output via the MOSFET controlled by the signal VMCH, and the signal V
The operating voltage VDL for the sense amplifier is output via the MOSFET controlled by the MDH. Also,
The output terminal Q / DQ4 is also used as a signature terminal for determining the presence or absence of defect relief. In the chip in which the defect has been remedied, when SIGB becomes low level and a voltage approximately three times the threshold voltage Vth higher than VCCE is applied to the Q / DQ4 terminal, a current flows into the ground potential of the circuit, It is determined that the chip has been repaired.

FIG. 67 is a circuit diagram showing one embodiment of the substrate back bias voltage generating circuit. In this embodiment, a low voltage VCC for a peripheral circuit is used as an operating voltage. The reason why the substrate back bias voltage is formed by the internal voltage VCC in this manner is that the internal voltage VCC is stabilized as described later, so that the substrate bias voltage can be stabilized.

The substrate bias voltage VBB is formed by bias voltage generation circuits VBBA and VBBS. Substrate bias voltage generating circuit VBBA includes a case substrate level is the main generator is shallow, operates to compensate for the substrate currents I _BB by the circuit during operation. The substrate bias voltage generation circuit VBBS is a sub-generation circuit, and operates steadily so as to compensate for fluctuations in VBB caused by leak current and minute DC current.

Signal VBSB is a monitor output of the level of substrate voltage VBB. Thus, the operation of the oscillation circuit is controlled, and when the substrate level is shallow, the circuit VBBA
Is operated until VBB becomes about -2V. The terminal VBT is used to stop the operations of the circuits VBBA and VBBS, set a substrate voltage externally through a VBB pad, for example, and evaluate an operation margin.

FIG. 68 is a circuit diagram showing one embodiment of the internal boosted voltage generation circuit. The circuit VCHA is a main boosted voltage generating circuit, and is formed by the internal operating voltage VCC for the peripheral circuit and the oscillation circuit when the level is low by the monitor signal VHSB of the boosted voltage VCH or when the RAM is accessed by the signal R1B. Oscillation signal OS
The charge pump circuit that receives CH forms the boosted voltage VCH of about 5.3 V as described above. Circuit V
CHS is a sub boosted voltage generation circuit, which operates steadily to form the boosted voltage VCH. This circuit VCH
S has only a small current supply capability to compensate for the leak current of the word line.

For an acceleration test or the like described later, the internal voltage VCC is raised accordingly when the power supply voltage VCCE is raised above a certain level. Correspondingly, the boosted voltage VCH is also increased with a constant level in accordance with the rise of the VCC. The diode-type MOSFET provided in the output section is used for level clamping. The terminal VHT is for stopping the operations of the circuits VCHA and VCHS, setting a boosted voltage from the outside through a VCH pad, for example, and evaluating an operation margin. Although not shown, capacitors for lowering the power supply impedance of the boosted voltage VCH are provided separately for each unit of operating circuit, for example, for each memory mat.

FIG. 69 is a circuit diagram showing one embodiment of the internal voltage down converter. The reference voltage VREF is MOS
This is a high-precision reference voltage formed using the difference between the threshold voltages Vth of the FETs. The constant voltage VL is formed from this voltage, and it is DC-amplified by the operational amplifier circuit to generate the above-mentioned voltage VDL and VCC of about 3.3V. In order to reduce the operating current, the circuits that generate the voltages VCC and VDL respectively operate only when the signals LD and LC activate the DRAM. Besides, when the power supply voltage VCCE is higher than a certain level, the signal L
A circuit is provided to form a step-down voltage at the time of standby by constantly operating by S. Immediately after the power is turned on, the signal SB is formed by the signal INT until the external voltage VCCE reaches a constant voltage, and the signals LD, LC, and LS are forcibly formed in response to the signal SB, and all the circuits are simultaneously formed. It is in an operating state, and the internal circuit operating voltage rises at high speed.

In the figure, the circuit represented by a resistor and a capacitor is for increasing the phase margin for preventing oscillation. The fuses F1 to F4 enable adjustment of the reference voltage VL by selectively cutting them with a laser beam. In the test function, the operation of the operational amplifier circuit is stopped by setting the signals LD, LC and LS to low level by the signal VE, and the low level is applied to the gate of the P-channel output MOSFET of the operational amplifier circuit by the MOSFET turned on by the signal VHE. Supply and turn on. As a result, the external voltage VCCE turns on the P-channel M
Internal voltages VDL and VCC are connected to VCC via OSFET.
E can be switched. Further, when the external power supply voltage VCCE exceeds a certain level (for example, about 6.6 V), the reference voltage VL increases accordingly, and the internal voltages VCC and VDL also increase. This corresponds to an accelerated test such as aging.

FIG. 70 is a timing chart showing an example of the operation of the RAS system. FIG. 3 shows a schematic waveform diagram of a main timing signal from the start of memory access by the RASB signal to the selection of a word line WL and resetting of the word line.

FIG. 71 is a timing chart showing an example of the operation of the RAS system. This figure shows a timing chart for selecting a word line. In the second cycle, the redundant system timing is shown.

FIG. 72 is a timing chart showing an example of the operation of the RAS system. FIG. 1 shows a waveform diagram of a timing signal for activating a sense amplifier and a common source line driven by the timing signal.

FIG. 73 is a timing chart showing an example of the operation of the X address buffer. FIG.
The mutual timing between the ASB signal and the CASB signal is shown.

FIG. 74 is a timing chart showing an example of the operation of the CAS system. In the figure, read mode (READ), early write mode (EW), read modify write mode (RMW), RAS
Waveform diagrams of main signals are shown in the order of only refresh mode, CBR refresh mode, counter test mode, and test mode set (WCBR).

FIG. 75 is a timing chart showing one embodiment of the CAS address selection operation. In the figure,
A main timing signal for performing Y-system address selection is shown.

FIG. 76 is a timing chart showing an example of the write operation. FIG. 2 shows main timing signals of the WE system.

FIG. 77 is a timing chart showing an example of the operation of the Y address buffer. The drawing mainly illustrates a timing signal YL for controlling an address latch in the high-speed page mode (FP), the nibble mode (N) and the static column mode (SC).

FIG. 78 is a timing chart showing one embodiment of the operation in the test mode. FIG. 3 mainly illustrates an address fetch and a latch operation.

FIG. 79 is a timing chart showing an example of the operation of the CAS system. In the figure, the read mode (REA) is applied to the test mode signals.
D), early write mode (EW), read modify write mode (RMW), RAS only refresh mode, CBR refresh mode, counter test mode, and test mode set (WCBR)
The waveform diagram of each signal is exemplarily shown in this order.

FIG. 80 is a timing chart showing an example of the operation of the CAS system. In the figure, a read mode (READ),
The waveform diagram of each signal is illustratively shown in the order of Early Write Mode (EW), Read Modify Write Mode (RMW), RAS Only Refresh Mode, CBR Refresh Mode, Counter Test Mode, and Test Mode Set (WCBR). It is shown.

FIG. 81 is a timing chart showing an example of the operation of the CAS system. In the figure, the read mode (REA) is set for the write mask mode.
D), early write mode (EW), read modify write mode (RMW), RAS only refresh mode, CBR refresh mode, counter test mode, and test mode set (WCBR)
The waveform diagram of each signal is exemplarily shown in this order.

FIG. 82 is a block diagram showing another embodiment of the defect remedy method according to the present invention. One redundant word line is provided for a plurality of word lines selected by the X decoder (including a word line driving circuit).
The redundant word line is arranged so as to intersect with the plurality of word lines at a location corresponding to the X decoder, in other words, to be parallel to a column of output terminals of the X decoder. Although not particularly limited, the redundant word line crosses a plurality of word lines to be relieved by two wirings arranged in parallel. One end of the two wires arranged in parallel is supplied with a ground potential.

In this configuration, when there is no defect in the word line, a ground potential is applied to the redundant word line, so that the redundant word line is constantly in a non-selected state. If one of the word lines has a defect (for example, a disconnection) at a location indicated by a cross in the figure, the word line is cut at a location indicated by a triangle in the figure. Similarly, the redundant word line is cut off on the right side (redundant word line side) of the defective word line as indicated by a triangle in order to separate it from the ground potential. Then, the decode output for forming the selection signal for the defective word line is connected to the redundant word line at the intersection indicated by the circle. Similarly,
In order to set the defective word line to a non-selected state, the defective word line is connected to a wiring to which a ground potential is applied at the cross point indicated by the circle. The disconnection and connection of the wiring as described above are not particularly limited, but both are performed using a wiring processing technique by irradiating a laser beam.

In this configuration, a defective word line is cut off from the output terminal of the word line selection circuit and a redundant word line is connected instead. Therefore, a storage circuit for storing a defective address and an address comparison circuit are not required. Become. Thus, high integration and low power consumption of the semiconductor memory device can be achieved. Further, since the address comparison operation as described above is not required, the speed of memory access can be increased. In addition, when the redundant word line as described above is provided for each of a plurality of word lines, when the redundant word line is not used, the ground potential is constantly applied to the redundant word line, thereby suppressing the coupling between the word lines. It can have a shielding effect.

FIG. 83 is a block diagram showing another embodiment of the defect remedy method according to the present invention. One redundant column selection line is provided for a plurality of column selection lines formed by the Y decoder circuit. Each of these column selection lines is transmitted to the gate of a column switch MOSFET included in the sense amplifier in FIG.
The bit lines (data lines) shown in the figure are substantially selected and connected to the common input / output lines. The redundant column selection line is arranged so as to intersect with the plurality of column selection lines at a location corresponding to the Y decoder, in other words, to be parallel to the column of the output terminals of the Y decoder. Although not particularly limited, the redundant column selection line intersects a plurality of column selection lines to be relieved by two wirings arranged in parallel. One end of the two wires arranged in parallel is supplied with a ground potential.

In this configuration, when there is no defect in the bit line and the sense amplifier, the ground potential is applied to the redundant column select line, so that the redundant column select line is constantly in a non-selected state. When one bit line has a defect (for example, a disconnection) at a location indicated by a cross in the figure, the column selection line is cut at a location indicated by a triangle in the figure. Similarly, the redundant column selection line is disconnected above the column selection line corresponding to the defective bit line (redundant column selection line side) as indicated by △ in order to separate it from the ground potential. Then, the decode output for forming the selection signal for the defective bit line is set to ○.
Is connected to the redundant column selection line at the intersection indicated by. Similarly, in order to set the column selection line corresponding to the defective bit to the non-selection state, the column selection line is connected to the wiring to which the ground potential is applied at the intersection indicated by the circle. The disconnection and connection of the wiring as described above are not particularly limited, but both are performed by irradiation with a laser beam.

In this configuration, the column address line corresponding to the defective bit line is cut off from the output terminal of the Y decoder and connected to the column select line corresponding to the redundant bit line instead. This eliminates the need for a storage circuit and an address comparison circuit. Thus, high integration and low power consumption of the semiconductor memory device can be achieved. Also, since the address comparison operation as described above becomes unnecessary,
It is also possible to speed up memory access. Further, when the redundant column selection line as described above is provided for each of a plurality of column selection lines, when the redundant column selection line is not used, the ground potential is constantly applied to the redundant column selection line, so that the coupling between the column selection lines is prevented. The shield effect of suppressing the ring can be provided.

FIGS. 84A to 84C show a waveform diagram of an embodiment for explaining a word line test method and a circuit diagram corresponding thereto. In this embodiment, a control signal EM is newly provided. The signal EM is newly supplied as one test mode including a combination of address signals in the above-described test mode in addition to the signal supplied from the external terminal. FIG. 3A shows a timing chart of the word line selection operation in the normal mode. Thus, in the normal mode, R
According to the selection operation of the AS system, the input address designation A0
Through A3, the corresponding word lines are sequentially selected.

On the other hand, in the aging mode in which the signal EM is set to the high level (set as one of the test modes), even if the RASB signal is reset from the low level to the high level, the selected word line WL1 is set to the high level. Will be kept as is. Therefore, when the addresses A0 to A3 incremented by the RASB signal are input, the word lines WL1 to WL3 sequentially selected as described above
When the ASB signal is at a high level, the signal is not reset. Although not particularly limited, by setting the signal EM to the low level, the selected word lines WL1 to W1
L3 is reset.

FIG. 29C is a circuit diagram of an embodiment of the word line selection circuit. The level of the signal EM is converted by a level conversion circuit including a latch-type NOR gate circuit using the boosted voltage VCH as an operation voltage, and becomes low level in the aging mode. This allows P
The channel MOSFET is turned on, the P-channel MOSFET connected in series with the P-channel MOSFET receiving the signal WPHL changes the high level of the word line WL to the off-state, and the P-channel receives the word line reset signal WPHL. Disable MOSFET output. As a result, once the word line WL is set to the high level, the state is maintained.

When the word line WL is reset or in the normal mode, the level conversion output goes high (VCH) according to the low level of the signal EM. This turns off the P-channel MOSFET,
Both the P-channel MOSFET receiving the signal WPHL and the P-channel MOSFET connected in series are turned on, the input of the CMOS inverter circuit driving the word line WL is set to the high level, and the word line WL is reset from the high level to the low level. Let it.

The input of the CMOS inverter circuit for driving the word line is provided with a switch MOSFET controlled by the inverter circuit receiving the output signal. This prevents the high level of the unselected signal X0UB from being transmitted to the CMOS inverter circuit that should maintain the selected level during the multiple selection as described above.

At the time of aging, when the signal EM is set to the high level and the word lines are selected one by one, the word lines can be maintained in the selected state during that time. As a result, the high level time of the selected word line can be lengthened, so that the duty of stress increases, and efficient aging can be performed in a relatively single time.

FIGS. 85A to 85D show an embodiment of the signal margin test method. In this embodiment, a control signal SM is newly provided. This signal SM
Is newly added as one test mode including a combination of address signals in the test mode as described above, in addition to the one supplied from the external terminal. FIG. 2A exemplarily shows a sense amplifier, a precharge circuit, a column switch, and a shared switch circuit related to a pair of complementary bit lines as representatives.

(B) of FIG. 29 shows an operation waveform chart in the normal mode. In the normal mode, the signal SM is set to low level. In response, the selected word line (L) -side shared selection signal SHL is set to the high-level selection level, and the non-selected word line (R) -side shared selection signal SHL is set to the low-level non-selection. You. Therefore, the storage information from the selected memory cell is read to the complementary bit line BL.

FIG. (C) shows an operation waveform diagram in the signal amount test mode. In the signal amount test mode, the signal SM is set to a high level. In response, the shared selection signal SHL on the selected word line (L) side
At the same time, the shared selection signal SHR on the unselected word line (R) side is also set to the high level. Therefore, since the left and right bit lines BL are coupled to the input of the sense amplifier, the bit line capacitance is approximately doubled. Therefore, the read level of the stored information from the selected memory cell is reduced to about の of the normal mode. In response to this, a signal amount margin test as to whether or not the sense amplifier accurately performs an amplification operation can be performed.

FIG. (D) is a circuit diagram of an embodiment of the shared selection signal generating circuit. In the figure, a control signal SM is added and the validity / invalidity of the selection signals SL and SR is controlled through a NOR gate circuit. That is, when the signal SM is at the high level, both the signals SL / SR are forcibly set to the selection level, and the signals SHL and SHR are set to the high level selection level. Note that this selection level is the boosted voltage VCH as described above.

FIG. 86 shows another embodiment of the function mode. Binary numerical data is directly input from address terminals A0 to A3 according to a function set signal formed by WCBR or the like.
This numerical data is, for example, a voltage decoder (digital /
The voltage is changed to an analog voltage of S0V to S10V by an analog conversion circuit. The analog voltage SiV is supplied to an internal voltage generating circuit including an operational amplifier circuit having a voltage follower configuration, and the above-described internal voltage VCC or V
Form a DL. With this configuration, the internal operating voltage can be set arbitrarily. This simplifies a voltage margin test, an acceleration test during aging, and the like.

The binary numerical data directly from the address terminals A0 to A3 is input to a time decoder to form decode signals S0D to S10D,
Input to the iD delay circuit. This delay circuit provides the signal S0D
Through S10D, the delay time is made variable from 0 to 10 ns. Thereby, the signal SiD
, An arbitrary delay time can be obtained. This delay circuit is used, for example, as a delay circuit when forming a time-series timing signal of the RAS system and the CAS system.
By utilizing this, for example, a test of a time margin can be performed.

FIG. 87 shows another embodiment of the refresh address counter. In this embodiment, a control signal CS is newly provided. The signal CS is supplied from an external terminal, is newly added as one test mode including a combination of address signals in the above-described test mode, or is formed by a power-on detection signal or the like.

FIG. (A) shows an operation waveform chart in the normal mode. In the normal mode, the signal CS is set to low level. In response to this, at the time of CBR refresh, the counter circuit performs a counting operation using the RASB signal as a clock to generate a refresh address signal ARi.

(B) of FIG. 29 shows an operation waveform diagram of the counter set. When the counter is set, the signal CS is set to the high level. At this time, when CBR is performed, an address signal input in synchronization with the low level of the RASB signal is input as a counter initial value. When the signal CS goes low, the counter circuit increases its initial value by +1.
And hold.

FIG. (C) shows a circuit diagram thereof. To enable the external input as described above, the signal C
An external set input circuit controlled by S is added.

FIG. 88 shows another embodiment of the internal power supply monitoring method. FIG. 3A shows the block. Internal step-down power supply circuit VCC or VD
The voltage VCC or VDL formed by L is supplied to one input of the level comparison circuit. A reference voltage supplied via an external pin is supplied to the other input of the level comparison circuit. The level comparison circuit outputs the magnitude relationship between the two voltages to the external terminal DOUT as a binary signal.

[0284] FIG. 47B is a waveform chart for explaining the operation. The voltage supplied to the external pin is changed as indicated by the dotted line in FIG.
The voltage value of the voltage VDL can be indirectly known from the high / low level transition point of T. The input voltage supplied from the external pin may be supplied directly to the level comparison circuit in a one-to-one correspondence, or may be supplied by attenuating or increasing the level. Similarly, the voltage VCC or the voltage VD
L may be a level attenuated at a fixed rate. When the level is attenuated in this way, the level monitoring of the boosted voltage VCH as described above becomes possible. In a configuration in which a level comparison circuit is provided internally as in this embodiment,
Since the analog voltage is not affected by the level fluctuation in the output voltage path in the method of directly outputting the analog voltage to the outside, the level can be monitored with high accuracy.

FIG. 90 shows an N-channel type column switch MOSFET for performing Y selection with a memory cell portion, and a P-channel MOSFET used for another CMOS circuit.
1 is a schematic cross-sectional view of an element structure of one embodiment. FIG. 1 shows a schematic sectional view of the element structure in the bit line direction. The N-channel MOSFET forming the memory cell and the column switch is formed in a P-type well formed on a P-type substrate 41.

In the figure, bit line 5 made of polycide is used.
For 0, a pair of memory cells is provided. That is,
MOSFE for address selection constituting a pair of memory cells
A pad contact 47 made of conductive polysilicon is provided in a contact hole formed by a self-alignment technique for the source and drain 44 having a common T. Sources and drains 44 on the capacitor side are provided on the left and right sides of the common source and drain 44, respectively, and a gate electrode 46 is formed between both regions via a thin gate insulating film 53. This gate electrode 4
Reference numeral 6 is made of conductive polysilicon and constitutes a word line. This word line is subjected to word shunt by an aluminum layer 52 formed thereon. FIG. 3 exemplarily shows a word line 46 connected to the gate of the address selection MOSFET of another memory cell whose pitch is shifted in the vertical direction from that of FIG. This word line 46
Are formed on a relatively thick field insulating film.

The source and the drain on the capacitor side of the address selection MOSFET are connected to a conductive polysilicon 48 constituting a store node of the information storage capacitor. Polysilicon 49 constituting the plate electrode of the capacitor is provided. On the bit line 50, a tungsten layer 51 as a first layer metal layer forming a column selection line is provided. Although not particularly limited, the polycide 50 forming the bit line is not shown in the figure, but is connected to the tungsten layer 51 via a shared selection switch MOSFET to form one of the MOSFETs forming the column switch in the figure. Are connected to the source and drain 44 of the IGBT. The source / drain 44 on the I / O side of this MOSFET is connected to the second layer of aluminum via the first metal layer 51 via the pad contact 47 in the same manner as the address selection MOSFET of the memory cell as described above. 52 is connected to the input / output line I / O.
An example in which a P-channel MOSFET is provided is shown on the right side of FIG. This P-channel MOSFET
Used for sense amplifiers and other CMOS circuits. As described above, the P-channel MOSFET is formed in the N-type WELL 43 and includes the source, the drain 45, and the gate 46.

In this embodiment, the input / output line I
As an N-channel MOSFET constituting a column switch connected to / O, a source and a drain connected to the input / output line I / O are provided with a memory cell address selection MO.
A pad contact 47 similar to the SFET is used. With this configuration, a self-alignment technique can be used to make a hole for a contact formed in the oxide film on the surface of the source and the drain. As a result, the source and drain below the pad contact 47 do not need to be formed large in consideration of a mask shift for forming a contact hole, and thus can be formed as small as necessary as shown in FIG. As a result, high integration and a reduction in the parasitic capacitance value can be achieved. In particular, when the sources and drains of many column switch MOSFETs are connected like the input / output line I / O, the column switch MOSFETs
The parasitic capacitance value can be greatly reduced as the parasitic capacitance of the source and drain decreases. This allows
Since the wiring capacity of the input / output lines I / O can be greatly reduced, the signal transmission speed is increased, and the writing / reading operation can be accelerated.

M using pad contact as described above
As the OSFET, the column switch MO as described above is used.
In addition to SFET, MOSFET which constitutes a sense amplifier,
Bit line precharge MOSFET, bit line short MOSFET, shared sense amplifier selection MO
The present invention can be used for circuits that require miniaturization and reduction of parasitic capacitance, such as SFETs and MOSFETs for word line drivers.

FIG. 92 is a schematic circuit diagram showing another embodiment of the main amplifier selection circuit. In the embodiment shown in the figure, the main amplifier MA is commonly used for memory mats which are divided and arranged above and below the main amplifier MA. That is, for a pair of memory mats including the memory cell array M and the sense amplifier S, the main amplifier MA is arranged at the center. The input / output lines I / O and I / OB of the memory mat are switch MOSFETs controlled by mat select signals MSU and MSD.
, Is selectively connected to the input of the main amplifier MA. The layout relationship between the memory mats and the sense amplifiers is basically the same as the embodiment of FIG. 2, and the number of main amplifiers can be reduced.

To simply reduce the number of main amplifiers, the main amplifier MA can be arranged above the upper memory mat or below the lower memory mat. However, in this case, among the input / output lines connected to the input terminals of the main amplifier MA, the wiring corresponding to the memory mat on the opposite side becomes longer. On the other hand, in the configuration in which the main amplifier is arranged at the center of the divided memory mats as in the embodiment shown in FIG. 2 and FIG. 2, the input / output lines I / O arranged in both memory mats are arranged. And the length of the I / OB are shortened equally, so that the memory access can be speeded up.

FIG. 93 is a schematic circuit diagram showing still another embodiment of the main amplifier selection circuit. In the embodiment shown in the figure, the main amplifier MA is commonly used for memory mats which are divided and arranged above and below the main amplifier MA. The memory mat of this embodiment uses a shared sense amplifier in which a memory cell array is divided into two parts on the left and right around the sense amplifier S. In this configuration, the divided memory cell array is regarded as a memory mat, and input / output lines I / O and I / OB are respectively provided.
And selectively connected to the input of the main amplifier MA via a switch MOSFET controlled by the mat select signals MS0 to MS3. The layout relationship between the memory mats and the sense amplifiers is basically the same as in the embodiment of FIG. 2, so that the number of main amplifiers can be reduced and the length of the input / output lines can be substantially shortened.

In the configuration in which input / output lines I / O and I / OB are arranged for a pair of memory cell arrays M as in this embodiment, the column switches connected to the input / output lines I / O and I / OB are provided. The number of MOSFETs can be divided in half. Accordingly, the length of the input / output lines can be substantially reduced, and the wiring capacitance can be reduced, so that high-speed operation can be achieved.

FIG. 94 is a layout diagram showing another embodiment of the DRAM according to the present invention. In this embodiment, based on the layout of FIG. 2, the semiconductor chip is divided into two by a vertical center line, and the layout of FIG. 2 is arranged axially symmetrically with respect to the center line. In this configuration, a cross-shaped area consisting of the vertical central portion and the horizontal central portion is provided in each half of the memory chip. As shown in the figure, when the memory chip is divided by the vertical center line, the horizontal center part is arranged on a straight line. The memory array is divided into eight by the two cross-shaped areas as described above. Peripheral circuits and bonding pads are arranged in the cross-shaped area composed of the above two in the same manner as in the above embodiment, and bonding by LOC leads is performed for each.

When such a layout is applied to a dynamic RAM having a storage capacity of 16 Mbits, the word line length is reduced to half in the example shown in FIG. In addition, since the memory mat is smaller and subdivided, power consumption can be reduced accordingly. Further, the above-mentioned cross-shaped area and four areas divided by the cross-section are used as a basic configuration, and by providing two sets of the areas as described above, it is possible to further increase the storage capacity of the RAM.

As shown in the figure, the memory chip is divided into two parts by the vertical center line to provide the cross-shaped area as described above, and the memory chip is divided into two parts by the horizontal center line. A cross-shaped area formed by a method similar to the example may be provided. Furthermore, these may be combined and further divided.

FIG. 95 is a pattern diagram showing one embodiment of the memory cell array according to the present invention. Bit lines are crossed at regular intervals to reduce coupling noise between adjacent bit line pairs. When such a bit line crossing method is employed, there is a problem that the area at the bit line crossing portion increases. Therefore, in this embodiment, a wiring layer used as a column selection line is used as a cross wiring. That is, when the first metal layer is used as the column selection line as shown in FIG. 5, the first metal wiring formed on the bit line composed of the polycide layer to be replaced is formed above the bit line composed of the polycide layer. Is used. By employing such a configuration in which the first metal layer is used, it is possible to eliminate the need for a dedicated wiring layer in the bit line cross portion.

In order to equalize the parasitic capacitance between the bit line and the column selection line extending in parallel, the column selection line is bent at the bit line crossing portion so as to be shifted by one pitch of the bit line pair. is there. This allows
One column selection line can have the same parasitic capacitance for both bit line pairs in the two pairs of bit lines, and can be used as a bit line crossing portion by providing the bent portion. . As a result, a special area is not required as a bit line crossing portion, and the continuity of various wiring patterns can be prevented from being lost.

When the cross section of the bit line is formed by using the upper wiring layer, the uniformity of the capacitor constituting the underlying memory cell and the uniformity of the address selection MOSFET are not adversely affected. From the above, the continuity and uniformity of the devices (capacitors and MOSFETs) constituting the memory cell are maintained, and variations in the characteristic margin of individual bit lines can be reduced. Further, since the continuity of the pattern and the cross contact are separated by separating the bit line contact, no particular problem can be caused with respect to manufacturing conditions and processing conditions.

This can be easily understood from the sectional view shown in FIG. 96A and the schematic view shown in FIG. As shown in the cross-sectional view of FIG. 2A, at the cross portion of the bit line, the bit line pair composed of polycide under the bit line is separated from each other, and the position of the other bit line is kept while one bit line remains polycide. The other bit line is made to intersect with the one bit line and to be replaced with the position of one bit line by the first metal layer formed thereover.

FIGS. 97 to 99 show layout diagrams of an embodiment of a shared sense amplifier array and a memory cell array corresponding thereto. In FIG. 97,
Memory cell array and shared MO located on the right
Dummy layers 69 and 70 forming a step buffer region are provided between the SFET and the SFET, and are formed to extend in the vertical direction in FIG. When a stacked memory cell is used as in this embodiment, the step buffer region is about 1 μm higher in the memory cell array section than in other peripheral circuits. For this reason, the step between the memory cell array section and the peripheral circuit section becomes sharp, and it becomes difficult to process the wiring layer and the like and to open the contact hole near the step.

Therefore, as shown in the figure, the first-layer polysilicon 69 formed simultaneously with the gate electrode of the MOSFET is formed.
Then, the step buffer word line 70 is formed as a dummy layer. In this configuration, as is apparent from the cross-sectional view of FIG. 100, by providing the above-described dummy layer, a step between the memory cell array portion and the peripheral circuit portion can be reduced. Further, in this embodiment, an N ⁺ diffusion layer is formed in the portion utilizing this step buffer region, and the voltage V
By supplying the DL, a guard ring function of the memory cell array section is provided. Thus, it is possible to prevent the minority carriers generated by the operation of the peripheral circuit, for example, from reaching the memory cell array portion and being combined with the storage charges, thereby shortening the holding time.

FIG. 98 is a pattern diagram of a Y gate (column switch MOSFET) portion and a P-channel MOSFET constituting a sense amplifier disposed on the left side of FIG. 97. FIG. 99 shows a pattern diagram of the bit line precharge MOSFET, the N-channel MOSFET and the shared MOSFET constituting the sense amplifier, and the memory cell array section on the left side. Thus, a step buffer region similar to the above is provided between the left memory cell array section and the shared MOSFET.

In FIGS. 97 to 99, reference numeral 61 denotes a bit line made of polycide, which is arranged to extend in the horizontal direction as shown in FIG. Reference numeral 62 denotes a column selection line, which is formed of a first metal layer as in the above-described embodiment, and is arranged to extend in the horizontal direction in FIG. 63 is a word line made of a polysilicon layer,
The word shunt is performed by the second metal layer 68 provided thereon. These word lines are arranged to extend in the vertical direction in FIG. Reference numeral 64 denotes an address selection MOSFET constituting a memory cell.
In the figure, the storage capacitor is omitted because the pattern becomes complicated. Numeral 65 is a bit line contact, and a pad contact as in the above embodiment is provided here. 66 is a diffusion layer. Reference numeral 67 denotes an input / output line I / O, which is formed of a second metal layer like the word shunt, and is arranged to extend in the vertical direction in FIG. It should be noted that the shared MOS
A second metal layer is formed for shunting the polysilicon constituting the gate of the FET to substantially reduce the resistance value and increase the speed.

FIGS. 101 to 108 show pattern diagrams of an embodiment of the memory cell array portion in the word line direction and peripheral circuits corresponding thereto. In FIG. 101, the step buffer region as described above is provided on the left side of the memory cell array. A dummy polysilicon wiring 78 is provided for buffering the step. A guard ring diffusion layer of the memory cell array and a wiring layer for applying the bias voltage VDL are provided on the substrate surface below the step buffer region.

In the memory cell array portion, reference numeral 71 denotes a diffusion layer, and reference numeral 72 denotes a word line formed of a polysilicon layer. In the figure, the pattern of the capacitor is omitted. Reference numeral 73 denotes a bit line made of polycide as described above, and reference numeral 74 denotes a second metal layer for word shunt. Reference numeral 75 denotes a column selection line, which is constituted by a first metal layer. Reference numeral 76 denotes a bit line contact, which uses the pad contact.

[0307] A word driver is formed on the left side of the memory cell array portion with the step buffering region interposed therebetween. In this word driver, 79 is a word driver MO.
SFET gate, 80 is driver MOSFET
The first metal layer on the output side connected to the word line of FIG. 81 is a contact connected to the source and drain diffusion layers of the MOSFET. The word driver as a whole is shown in FIGS.
5 are arranged to extend to the left.

On the further left side of the word driver shown in FIG. 105, X decoders are arranged side by side so as to extend to the left as shown in FIGS. 106 and 107. FIG.
8 shows a pattern diagram of an embodiment of a word clear circuit provided on the right end side of the memory cell array section shown in FIG. 101, in other words, on the other end side of the word line to which the output of the word driver is connected. Have been.

In the same figure, a step buffer region similar to the above is provided between the right end of the memory cell array portion and the word clear circuit. There, a step buffer wiring (polysilicon) and guard ring shunt 99 are provided.
In the figure, reference numeral 91 denotes a word clear signal line, which is formed by a second metal layer. 92 is a ground line and 1
It is formed by the metal layer of the layer. Reference numeral 93 denotes a word clear gate, which is formed of a polysilicon layer. 94
Is a diffusion layer. Reference numeral 95 denotes a dummy polysilicon layer for buffering the step. 96 is a word line shunt layer,
The second metal layer is formed. Reference numeral 97 denotes a word line made of polysilicon. Numeral 100 is a bit line composed of a plurality of bits. Black squares indicate contact portions.

The operation and effect obtained from the above embodiment are as follows. Peripheral circuits are arranged in a cross-shaped area consisting of a vertical center portion and a horizontal center portion of a semiconductor chip, and memory arrays are arranged in four areas divided by the cross-shaped area. In this configuration, the maximum transmission path of a signal can be shortened to almost half of the chip size in accordance with the peripheral circuit being arranged at the center of the chip, so that the speed of the DRAM with a large storage capacity can be increased. The effect is obtained.
Also, by providing the cross-shaped area for both areas divided by the vertical center line of the semiconductor chip and adopting the same layout as above, it is possible to further increase the storage capacity or speed. Is obtained.

By arranging the X-decoder and the Y-decoder on the edge of the cross-shaped area in contact with the memory array, the signal transmission path to the address buffer and the pre-decoder provided in the cross-shaped area can be reduced. . As a result, an effect that rational layout and high speed can be achieved is obtained.

[0312] In the cross-shaped area, a region between the X decoders in the vertical center or the horizontal center is provided with at least one of a main amplifier, a common source switch circuit, a sense amplifier control signal generation circuit, and a mat selection control circuit. 1
Place one. Thus, among the peripheral circuits arranged in the cross-shaped area, the circuits corresponding to the X decoder, the sense amplifier, and the input / output line I / O are provided in the vicinity thereof, so that the memory cell selection circuit and the transmission path of the storage information are provided. Since the layout can be rationalized, the effect of high integration and high speed can be obtained.

In the cross-shaped area, at least one of an address buffer, a control logic circuit corresponding to a control signal, and a defect rescue circuit is arranged in a region sandwiched between Y-decoders in the vertical center or horizontal center. I do. With this configuration, it is possible to realize a rational layout according to the signal propagation path, and it is possible to obtain an effect that the speed can be increased accordingly.

At least a final driver circuit of a decoder input address signal generating circuit and at least one of a power supply generating circuit used inside are arranged in a central portion where a vertical central portion and a horizontal central portion overlap in the cross-shaped area. I do. As a result, the input signals are transmitted from the center of the chip to the X and Y decoders that perform the operation of selecting the word lines and the column selection lines in four directions corresponding to the respective chips. Thus, the load can be shortened, and the load can be divided and lightened, so that the speed can be increased.

By arranging a circuit among the above-mentioned peripheral circuits, which in principle has the possibility of injecting minority carriers into the substrate, on or near the two center lines of the cross-shaped area, the peripheral circuit is located at the center of the chip. The effect of minimizing the influence of the minority carrier on the memory cell array portion can be obtained while increasing the speed by the arrangement.

The memory array formed in the area divided into four by the cross-shaped area is constituted as an aggregate of a plurality of memory mats of the same size including the sense amplifier. With this configuration, the memory cell selection operation can be divided into two stages by adding the memory cell selection operation in the MAT to the MAT selection operation based on the upper address, and the decoder can be divided accordingly. The effect is obtained that the load is reduced and high-speed operation is achieved.

In the memory array divided into four by the cross-shaped area, at least one of an X decoder and a Y decoder is arranged so as to divide each memory array. This makes it possible to shorten the length of the word line or the column selection line in accordance with the fact that the word line or the column selection line is substantially divided by the decoder, so that it is possible to obtain the effect of enabling high-speed selection of memory cells.

The memory mat of the above unit is provided with a control circuit for generating various timing signals for a memory cell selecting operation based on the mat selecting signal. As a result, a time-series operation sequence can be performed at an optimized timing in the memory mat, so that in a DRAM having a large storage capacity which will be composed of a large number of memory blocks, a timing margin between different memory blocks can be reduced. Since it is not necessary to adopt this, it is possible to obtain an effect that a high-speed memory access and an operation margin can be improved. Further, it is easy to change the number of operating memory mats, and the effect of facilitating product type development (low power) can be obtained.

In the unit memory mat, a pair of adjacent memory mats is used as one sub-block, and a control circuit for controlling the memory mat is provided for each sub-block. In this configuration, since one memory mat can be selected in the sub-block, the control circuit can be used in common for a plurality of memory mats, and the effect of high integration and high speed can be obtained.

The memory mat of the above unit is constituted by a pair of sub-blocks having an axisymmetric relationship, so that the control circuit can be used in common for more memory mats, and high integration and high speed can be achieved. Is obtained.

By activating the control circuit by the mat select signal, the sub-block select signal or the block select signal, it is possible to suppress unnecessary current consumption in a non-selected mat or sub-block, thereby reducing power consumption. The effect of being achieved is obtained.

The control circuit includes precharge of complementary data lines, activation of sense amplifiers, control of shared sense amplifiers, activation of X decoders, activation of Y decoder circuits, activation of word drivers, common input / output lines Selection of,
At least one of the main amplifier selection and the activation of the main amplifier is controlled. This allows
The effect is obtained that the operation sequence control within the mat can be optimized.

A selection signal for selecting a word line and a complementary data line belonging to the memory mat is supplied to the memory mat. In this configuration, the selection signal is formed by the predecode circuit, and the effect that rational division of the decoder circuit becomes possible is obtained.

By providing a circuit for forming a selection signal for selecting a word line or a complementary data line belonging to the memory mat of the unit described above in common for a plurality of memory mats or sub-blocks, Since the extra routing of the control signal is eliminated, the effect that low power and high speed can be obtained is obtained.

An address signal for selecting the memory mat or the memory block is inputted using a dedicated address buffer. With this configuration, the address signal forming the mat select signal can be separated from a relatively large load capacity such as a large number of address comparison circuits provided in the redundant circuit, so that the speed can be increased. This makes it possible to perform a mat selection operation.

A part or all of the bonding pads are arranged in the cross-shaped area. As a result, it is possible to transmit and receive signals from the center of the chip, so that the signal transmission path is transmitted while spreading from the center of the chip to the periphery in almost four directions. Since the signal transmission path can be shortened irrespective of the increase in size, the effect of increasing the speed can be obtained.

The bonding pads are all arranged in a zigzag pattern in two rows in the center of the cross in the vertical cross section. As a result, there can be obtained an effect that a large number of bonding pads can be efficiently arranged and high integration can be achieved.

The bonding pads arranged side by side in the vertical center of the cross-shaped area are bonded to the LOC lead frame,
Since the lead frame can be regarded as a part of the wiring for the power supply pad or a bonding pad can be provided close to the input circuit, the effect of improving the level margin and increasing the speed can be obtained. .

Of the above-mentioned bonding pads, a plurality of pads for supplying the power supply voltage and the ground potential of the circuit are provided at appropriate intervals according to the circuit block requiring the same, and the pads for supplying the power supply voltage and the ground potential of the circuit are provided. By connecting each of them to the common LOC lead frame to be provided, the noise level accompanying the circuit operation can be suppressed to a low level, so that the effect of improving the operation margin can be obtained.

Of the above bonding pads, a plurality of pads for applying a ground potential are provided in accordance with the chip distribution of the activated sense amplifier array. As a result, a relatively large current due to the amplifying operation of the sense amplifier is supplied from the corresponding pad, so that the noise level generated in the ground potential of other circuits can be kept low, and the operation margin can be expanded. Is obtained.

A peripheral circuit and a bonding pad are arranged in a cross-shaped area consisting of a vertical center portion and a horizontal center portion of a semiconductor chip. A memory array is arranged in four areas divided by the cross-shaped area, and four corners of the semiconductor chip are arranged. Is provided with a step. Thus, an effect is obtained that stress from the mold resin can be prevented from being directly applied to the memory cell portion at the corner of the chip.

The steps provided at the four corners of the semiconductor chip are formed by stacking wiring layers formed in the same process as the manufacturing process of the memory array portion, so that the chip from the mold resin can be formed without adding a manufacturing process. The effect of being able to disperse the stress applied to is obtained.

[0333] Peripheral circuits are arranged in a cross-shaped area consisting of a vertical center part and a horizontal center part of a semiconductor chip, and a memory array is arranged in four areas divided by the cross-shaped area. A high-concentration diffusion layer of the same conductivity type as the substrate is arranged to supply a substrate back bias voltage, and a guard ring composed of a diffusion layer of the opposite conductivity type to the substrate is arranged inside the substrate and a power supply voltage is placed there. Supply. According to this configuration, an effect is obtained that unwanted noise can be prevented from entering the memory array section.

An internal step-down voltage generating circuit which operates by a power supply voltage supplied from an external terminal and forms an operating voltage of an internal circuit comprising an output buffer for impedance conversion receiving a reference voltage is incorporated. With this configuration, it is possible to obtain an effect that the operating voltage can be reduced in accordance with the decrease in the withstand voltage due to the miniaturization of the element, and that the power consumption can be reduced by reducing the operating voltage. Further, since the step-down voltage is formed by the reference constant voltage, it is not affected by the fluctuation of the external power supply voltage, so that the operation of the internal circuit can be stabilized.

By dividing the internal step-down voltage generating circuit into a memory array voltage and a peripheral circuit voltage,
The effect is obtained that the generation of noise due to the circuit operation can be prevented.

The step-down voltage generated by the internal step-down voltage generating circuit is set to a voltage which is about twice the logic threshold voltage of the input buffer circuit to which the step-down voltage is supplied.
As a result, it is possible to obtain an effect that the operating voltage can be effectively used and the input level margin can be expanded.

The output circuit of the output buffer for performing the impedance conversion operation has a CMOS structure, and has a function of selectively outputting a power supply voltage via a P-channel MOSFET on the power supply voltage side. As a result, there is obtained an effect that a function of switching an internal operating voltage to a power supply voltage supplied from the outside can be provided without adding a special circuit. This voltage switching function can be used, for example, for aging.

A signal to be output, which is formed by an internal circuit operating at the step-down voltage generated by the internal step-down voltage generating circuit, is converted into a level in accordance with a power supply voltage supplied from the outside through a level changing circuit, so as to be a source follower. Output M
Drive the OSFET. In this configuration, the level amplitude of the output signal can be made large and the amplitude of the drive signal becomes large, so that the effect of increasing the operation speed can be obtained.

The output MOSFET is provided in parallel with an output MOSFET driven by a signal having a relatively small signal amplitude formed by the internal circuit. As a result, the change of the output signal can be started at a relatively early timing, so that the change of the signal can be made linearly over a relatively long time, so that the operation speed of the output is sacrificed. Therefore, it is possible to reduce the noise level generated in the power supply line and the ground line when the output signal changes.

With the internal voltage generated by the internal step-down voltage generating circuit, the data output buffer is set to the output high impedance state in the test mode, and the switch is controlled by the signal of the bootstrap voltage or the external power supply voltage level from its output terminal. Switch MOSFET
And selectively output via. Thus, it is possible to monitor whether or not the internal power supply circuit is operating normally, and it is possible to obtain an effect that high reliability can be achieved.

As a selection signal for a word line or a shared sense amplifier, it is formed by a selection circuit that uses a high voltage formed by boosting the internal step-down voltage as an operation voltage. Thus, the boosted voltage can be stabilized without being affected by the external power supply, and the effect of increasing the speed of the operation of selecting a word line or the like can be obtained.

A memory cell array is arranged symmetrically with respect to the main amplifier, and the input / output lines of the memory cell array are selectively connected to the main amplifier via a switch MOSFET that is switch-controlled in response to a memory cell array selection signal. . With this configuration, the number of main amplifiers can be reduced, and the substantial wiring length of the input / output lines can be shortened, so that an effect of increasing the speed can be obtained.

As the memory cell array, shared sense amplifiers are employed, input / output lines corresponding to the left and right memory mats are provided, and a switch MOSFET controlled by a switch corresponding to the mat select signal is provided. To a common main amplifier.
In this configuration, the data line length by the shared sense amplifier method can be shortened, and the input / output lines are correspondingly divided, so that the wiring capacity of the input / output lines can be reduced by half, so that the effect of increasing the speed can be obtained.

By using the memory mat of the above-mentioned unit as the memory cell array, the number of main amplifiers can be reduced, and the length of input / output lines coupled thereto can be shortened, whereby high speed operation can be realized. can get.

A latch circuit for receiving and holding a word line selection signal by a control signal is provided, and a word line drive signal is formed by an output signal of the latch circuit. As a result, word lines can be sequentially multiplex-selected, so that aging and the like can be performed efficiently.

In the test mode, a mode is provided for connecting both left and right complementary data lines to the shared sense amplifier. As a result, the signal amount from the memory cell is relatively reduced to １ ／ as the capacity of the complementary data line is approximately doubled, so that a margin test of the signal amount can be easily performed. Can be

In the function setting mode, a function of inputting a digital signal composed of a plurality of bits corresponding to an address terminal composed of a plurality of bits and setting the state of an internal circuit to a voltage or a delay time corresponding to the digital signal is provided. . As a result, it is easy to change the internal operation voltage and the signal delay, and the effect that the internal test can be performed efficiently can be obtained.

A refresh address counter circuit provided with a reset or initial value setting function from the outside by a predetermined control signal is provided. As a result, an effect is obtained that the refresh operation can be used for multiple selection of the word lines and selection of addresses for various read / write tests.

An internal power supply voltage generating circuit for forming an operating voltage of the internal circuit is provided, and a voltage based on the internal voltage is compared with an externally applied voltage to output a binary signal as a result of the comparison. With this configuration, an effect that the internal operating voltage can be monitored with high accuracy can be obtained.

In a CMOS DRAM, a sense amplifier, a first stage circuit of an input buffer, a last stage circuit of an output buffer, a first stage circuit of a main amplifier, pull-up MOSFETs for input / output lines, short-circuit MOSFETs for complementary data lines and complementary input / output lines, and Among the diode-type MOSFETs constituting the charge pump circuit, the threshold voltage of the MOSFET used in at least one circuit is lower than the MOSFET used in the other circuits. As a result, there is an effect that the operation can be speeded up.

A column switch MOSFET, a MOSFET constituting a sense amplifier, a precharge MOSFE
T, short MOSFET, word line drive MOSFE
MOSFET for cutting T and shared sense amplifier
At least one type of MOSFET uses the same pad contact as the source / drain contact of the memory cell address selection MOSFET as the source / drain contact. As a result, the self-aligned technique can be used as the source and drain contacts in the same manner as the memory cell, and the source and drain regions can be formed to the required minimum. As a result, there is an effect that high speed can be achieved by high integration and small parasitic capacitance.

In the cross section in the bit line cross system,
By using the first metal layer used for forming the column selection line formed thereon, the wiring forming the cross portion becomes unnecessary, and the uniformity of the underlying capacitor and MOSFET is improved. The effect of being able to eliminate the adverse effect is obtained.

The column select lines correspond to two pairs of bit lines, and are specially bent and arranged so as to overlap one bit line pair with the other bit line pair in front of the bit line cross portion. The effect of eliminating the need for a cross wiring area and equalizing the parasitic capacitance between the column selection line and the bit line can be obtained.

By providing a step buffer region made up of a dummy wiring layer between the stacked memory cell array portion and its peripheral circuit portion, the effect of facilitating wiring processing can be obtained.

By arranging the guard ring below the step buffering region, the effect that the characteristics can be stabilized can be obtained.

It has a memory array composed of an aggregate of a plurality of memory mats of the same size including sense amplifiers, and a redundant word line and / or redundant data line is provided for each memory mat. In addition, the number of redundant word lines and / or data lines constituted by all the memory mats is smaller than the total number of redundant word lines and / or data lines provided in one memory mat. And the memory mat is used in common. As a result, the circuit scale required for defect relief can be reduced, so that there is an effect that high integration and low power consumption can be achieved.

The redundant circuit includes a defective address storage circuit and an address comparison circuit, and the corresponding X, Y
Provided near the address buffer. As a result, since the signal transmission path can be minimized, the operation can be speeded up and the degree of integration can be increased.

At the output of the word line or column selection circuit, a spare word line or spare column selection line having a wiring crossing a plurality of word lines or column selection lines is formed, and a defective word line or defective data line is formed. Occurs, the output line of the word line or the column selection circuit is cut off from the column selection line corresponding to the defective word line or the defective data line by irradiation with a laser beam, and is connected to the spare word line or the spare column selection line. Perform defect relief. In this configuration, since a storage circuit and a comparison circuit for a defective address are not required, an effect that high integration, high speed, and low power consumption can be achieved is obtained.

In the multi-bit simultaneous test mode by Y-system multiple selection, only the memory block or the YS line whose defect has been repaired is switched to the redundant data line or the redundant YS line. As a result, the number of redundant data lines or redundant YS lines to be prepared can be reduced while shortening the test time by the multi-bit simultaneous test function. (51) The data line is divided into a plurality of blocks by X, Y or internally formed block addresses, or a combination thereof, and only those blocks having a defect using these signals are used as redundant data lines or redundant YS.
By switching to the line, the effect of reducing the number of redundant data lines or redundant YS lines to be prepared can be obtained.

A word line is divided into a plurality of blocks by X or a block address formed inside, or a combination thereof, and only those blocks having a defect are switched to redundant word lines by using these signals. The effect of reducing the number of redundant word lines to be prepared can be obtained.

By using the same program means as the means for programming a defective address as the block address, the effect that the program can be simplified can be obtained.

The invention made by the inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. Needless to say. For example,
The storage capacity of the dynamic RAM may be 16 Mbits as described above, or a smaller capacity such as 4 Mbits or a larger capacity such as 64 Mbits. Further, a non-multi system in which an X address and a Y address are supplied from independent terminals as address inputs, and the storage capacity may be set to about 8 Mbits or 24 Mbits accordingly.

The present invention can be widely applied to semiconductor memory devices having a large storage capacity as described above and various semiconductor devices having a large circuit scale.

[0364]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a first region extending in a first direction along a center line crossing a short side of a substantially rectangular region of the semiconductor substrate main surface, and intersects the first region along a center line crossing a long side thereof. Providing a second region extending in a second direction, dividing the rectangular region into third, fourth, fifth, and sixth regions to provide first, second, third, and fourth memory arrays, respectively; First, second, third and fourth decoding circuits are arranged along respective tangents of the first region and the first to fourth memory arrays, and the second region and the first to fourth memory arrays are arranged. Fifth along each tangent to the memory array,
By arranging the sixth, seventh and eighth decoding circuits and providing a plurality of bonding pads provided in the second region, it is possible to achieve a large storage capacity or a large scale integration and a high speed.

[Brief description of the drawings]

FIG. 1 is a basic layout diagram showing an embodiment of a dynamic RAM to which the present invention is applied.

FIG. 2 is an overall layout diagram showing one embodiment of a DRAM according to the present invention.

FIG. 3 is a layout diagram showing a detailed arrangement of bonding pads of a dynamic RAM to which the present invention is applied;

FIG. 4 is a block diagram showing one embodiment of address assignment of a dynamic RAM to which the present invention is applied;

FIG. 5 is a block diagram showing an embodiment focusing on a control signal in the dynamic RAM according to the present invention.

FIG. 6 is a block diagram showing an embodiment focusing on the operation sequence of the dynamic RAM according to the present invention.

FIG. 7 is a layout diagram specifically illustrating a relationship between a power supply line of a dynamic RAM according to the present invention, and an internal power supply circuit and a pad associated therewith.

FIG. 8 is a layout diagram for specifically explaining a relationship between a ground line of a circuit in a dynamic RAM according to the present invention, an internal power supply circuit related thereto and a pad.

FIG. 9 is a specific layout and cross-sectional view showing one embodiment of the input protection circuit according to the present invention.

FIG. 10 is a specific layout diagram showing one embodiment of an input protection circuit provided on an external power supply voltage pad of the dynamic RAM according to the present invention.

FIG. 11 is a layout diagram showing one embodiment of a peripheral portion of a semiconductor chip according to the present invention.

FIG. 12 is a schematic sectional view of a corner portion of the semiconductor chip of FIG. 11;

FIG. 13 is a schematic sectional view of the outermost periphery of the semiconductor chip of FIG. 11;

FIG. 14 is a basic layout diagram showing another embodiment of the dynamic RAM according to the present invention.

FIG. 15 is a basic layout diagram showing another embodiment of the dynamic RAM according to the present invention.

FIG. 16 is a basic layout diagram showing still another embodiment of the dynamic RAM according to the present invention.

FIG. 17 is a configuration diagram showing another embodiment of the memory mat in the dynamic RAM according to the present invention and an embodiment of a memory block configured by combining the basic configuration.

FIG. 18 is a configuration diagram showing another embodiment of a memory mat in the dynamic RAM according to the present invention and an embodiment of a memory block configured by combining it.

FIG. 19 is a configuration diagram showing another embodiment of the memory mat in the dynamic RAM according to the present invention and an embodiment of a memory block configured by combining it.

FIG. 20 is a configuration diagram showing another embodiment of a memory mat in the dynamic RAM according to the present invention and an embodiment of a memory block configured by combining it;

FIG. 21 is a configuration diagram showing another embodiment of a basic configuration of a sub block and a memory block configured by combining the basic configuration in a dynamic RAM according to the present invention.

FIG. 22 is a plan view showing one embodiment of a lead frame used in a dynamic RAM according to the present invention.

FIG. 23 is a schematic side view showing an example of connection between a lead frame and a semiconductor chip used in a dynamic RAM according to the present invention.

FIG. 24 is an external view and an internal perspective view showing an embodiment of a dynamic RAM according to the present invention.

FIG. 25 is a pin layout diagram of external terminals showing one embodiment of the dynamic RAM according to the present invention.

FIG. 26 shows a dynamic RAM according to the present invention.
FIG. 4 is a pin layout diagram of an external terminal according to an embodiment when a P-type package is used.

FIG. 27 shows an SO dynamic RAM according to the present invention.
FIG. 5 is a pin layout diagram of an external terminal according to an embodiment when a J-type package is used.

FIG. 28 is a partial circuit diagram showing one embodiment of a RAS control circuit in the dynamic RAM according to the present invention.

FIG. 29 is another partial circuit diagram showing one embodiment of the control circuit in the dynamic RAM according to the present invention.

FIG. 30 is another partial circuit diagram showing one embodiment of the control circuit in the dynamic RAM according to the present invention.

FIG. 31 is a circuit diagram showing an embodiment of an X address buffer in the dynamic RAM according to the present invention.

FIG. 32 is a circuit diagram showing one embodiment of an address buffer circuit corresponding to X address signals A9 and A10 in the dynamic RAM according to the present invention.

FIG. 33 is a circuit diagram showing one embodiment of an address buffer corresponding to an X address signal A11 in the dynamic RAM according to the present invention.

FIG. 34 is a circuit diagram showing one embodiment of an address buffer corresponding to an X address signal A8 in the dynamic RAM according to the present invention.

FIG. 35 is a partial circuit diagram showing one embodiment of a row predecoder in the dynamic RAM according to the present invention.

FIG. 36 is a circuit diagram showing an embodiment of an X-system redundant circuit in the dynamic RAM according to the present invention.

FIG. 37 is a partial circuit diagram showing one embodiment of a decoder circuit for selecting a word line in the dynamic RAM according to the present invention.

FIG. 38 is a partial circuit diagram showing one embodiment of a decoder circuit for selecting a redundant word line in the dynamic RAM according to the present invention.

FIG. 39 is a circuit diagram showing one embodiment of a timing generation circuit for activating a sense amplifier in the dynamic RAM according to the present invention.

FIG. 40 is a partial circuit diagram showing one embodiment of a control circuit provided in a memory mat in the dynamic RAM according to the present invention.

FIG. 41 is a circuit diagram showing an embodiment of an X decoder, a word line drive circuit, and a shared control line drive circuit in the dynamic RAM according to the present invention.

FIG. 42 is a circuit diagram showing one embodiment of a memory cell array in a dynamic RAM according to the present invention.

FIG. 43 is a circuit diagram showing one embodiment of a refresh address counter circuit in the dynamic RAM according to the present invention.

FIG. 44 is a partial circuit diagram showing one embodiment of a CAS control circuit in the dynamic RAM according to the present invention.

FIG. 45 is a circuit diagram showing one embodiment of a Y address buffer in the dynamic RAM according to the present invention.

FIG. 46 is a partial circuit diagram showing one embodiment of a Y-system redundant circuit in the dynamic RAM according to the present invention.

FIG. 47 is another partial circuit diagram showing one embodiment of a Y-system redundant circuit in the dynamic RAM according to the present invention;

FIG. 48 is a partial circuit diagram showing one embodiment of a Y-system redundant circuit in the dynamic RAM according to the present invention.

FIG. 49 is a circuit diagram showing one embodiment of a pre-decoder circuit for a Y-system address signal in the dynamic RAM according to the present invention.

FIG. 50 is a circuit diagram showing one embodiment of a Y-system decoder for forming a column selection signal in the dynamic RAM according to the present invention.

FIG. 51 is a circuit diagram showing one embodiment of a nibble counter circuit in a dynamic RAM according to the present invention.

FIG. 52 is a partial circuit diagram showing one embodiment of a control circuit for forming a Y-system control signal in the dynamic RAM according to the present invention.

FIG. 53 is a circuit diagram showing one embodiment of an operation mode determination circuit in the dynamic RAM according to the present invention.

FIG. 54 is a partial circuit diagram showing one embodiment of a Y-system control circuit in the dynamic RAM according to the present invention.

FIG. 55 is a partial circuit diagram showing an embodiment of a WE control circuit in the dynamic RAM according to the present invention.

FIG. 56 is another partial circuit diagram showing one embodiment of a WE control circuit in the dynamic RAM according to the present invention.

FIG. 57 is a circuit diagram showing one embodiment of a data input buffer in the dynamic RAM according to the present invention.

FIG. 58 is a circuit diagram showing one embodiment of a main amplifier control circuit in a dynamic RAM according to the present invention.

FIG. 59 is a circuit diagram showing one embodiment of a main amplifier in a dynamic RAM according to the present invention.

FIG. 60 is a circuit diagram showing one embodiment of a data output control circuit of a main amplifier in a dynamic RAM according to the present invention.

FIG. 61 is a circuit diagram showing one embodiment of an output control circuit of a main amplifier in a dynamic RAM according to the present invention.

FIG. 62 is a circuit diagram showing one embodiment of a data output buffer in the dynamic RAM according to the present invention.

FIG. 63 is a partial circuit diagram showing one embodiment of a test circuit in the dynamic RAM according to the present invention.

FIG. 64 is another partial circuit diagram showing one embodiment of the test circuit in the dynamic RAM according to the present invention.

FIG. 65 is a circuit diagram showing one embodiment of a control circuit for designating an operation mode in the dynamic RAM according to the present invention.

FIG. 66 is a circuit diagram showing one embodiment of another control circuit in the dynamic RAM according to the present invention.

FIG. 67 is a circuit diagram showing one embodiment of a substrate back bias voltage generation circuit in a dynamic RAM according to the present invention.

FIG. 68 is a circuit diagram showing one embodiment of an internal boosted voltage generation circuit in the dynamic RAM according to the present invention.

FIG. 69 is a circuit diagram showing one embodiment of an internal step-down voltage generating circuit in the dynamic RAM according to the present invention.

FIG. 70 is a timing chart showing an example of the operation of the RAS system in the dynamic RAM according to the present invention.

FIG. 71 is a timing chart showing an example of the operation of the RAS system in the dynamic RAM according to the present invention.

FIG. 72 is a timing chart showing an example of the operation of the RAS system in the dynamic RAM according to the present invention.

FIG. 73 is a timing chart showing an example of the operation of the X address buffer in the dynamic RAM according to the present invention.

FIG. 74 is a timing chart showing an example of the operation of the CAS system in the dynamic RAM according to the present invention.

FIG. 75 is a timing chart showing an example of a CAS address selection operation in the dynamic RAM according to the present invention.

FIG. 76 is a timing chart showing an example of a write operation in the dynamic RAM according to the present invention.

FIG. 77 is a timing chart showing an example of the operation of the Y address buffer in the dynamic RAM according to the present invention.

FIG. 78 is a timing chart showing an example of the operation in the test mode in the dynamic RAM according to the present invention.

FIG. 79 is a timing chart showing an example of the operation of the CAS system in the dynamic RAM according to the present invention.

FIG. 80 is a timing chart showing an example of the operation of the CAS system in the dynamic RAM according to the present invention.

FIG. 81 is a timing chart showing an example of the operation of the CAS system in the dynamic RAM according to the present invention.

FIG. 82 is a block diagram showing another embodiment for explaining a defect remedy method according to the present invention.

FIG. 83 is a block diagram showing another embodiment for describing the defect remedy method according to the present invention.

FIG. 84 is a waveform diagram and a circuit diagram of an embodiment for describing a word line testing method in the dynamic RAM according to the present invention.

FIG. 85 is a circuit diagram and a waveform diagram showing one embodiment for explaining a signal amount margin test method in the dynamic RAM according to the present invention.

FIG. 86 is a block diagram showing another embodiment of the function set mode in the dynamic RAM according to the present invention.

FIG. 87 is a waveform diagram and a circuit diagram showing another embodiment of the refresh address counter in the dynamic RAM according to the present invention.

FIG. 88 is a block waveform diagram showing another embodiment of the internal power supply monitoring method in the dynamic RAM according to the present invention.

FIG. 89 is a circuit diagram and a waveform diagram for explaining the principle of the multi-bit test method in the dynamic RAM according to the present invention.

FIG. 90 is a sectional view of an element structure in a bit line direction in a dynamic RAM according to the present invention;

FIG. 91 is a conceptual diagram for explaining a defect remedy method according to the present invention.

FIG. 92 is a block diagram showing one embodiment of a layout of a main amplifier and a memory cell array in a dynamic RAM according to the present invention.

FIG. 93 is a block diagram showing another embodiment of the layout of the main amplifier and the memory cell array in the dynamic RAM according to the present invention;

FIG. 94 is a basic layout diagram showing another embodiment of the semiconductor chip according to the present invention.

FIG. 95 is a pattern diagram showing one embodiment of a memory cell array according to the present invention;

FIG. 96 is a cross-sectional view and a schematic diagram for explaining a bit line cross portion in the dynamic RAM according to the present invention.

FIG. 97 is a partial pattern diagram showing one embodiment of a shared sense amplifier array section in the bit line direction and a corresponding memory cell array section in the dynamic RAM according to the present invention.

FIG. 98 is a partial pattern diagram showing one embodiment of a shared sense amplifier array section in a bit line direction and a memory cell array section corresponding thereto in a dynamic RAM according to the present invention;

FIG. 99 is a partial pattern diagram showing one embodiment of a shared sense amplifier array section in the bit line direction and a memory cell array section corresponding to the shared sense amplifier array section in the dynamic RAM according to the present invention.

FIG. 100 is a sectional view of a step buffer region in the dynamic RAM according to the present invention;

FIG. 101 is a pattern diagram showing one embodiment of a memory cell array section in a word line direction and a corresponding word driver in a dynamic RAM according to the present invention.

FIG. 102 is a partial pattern diagram showing one embodiment of the word driver corresponding to FIG. 101.

FIG. 103 is a partial pattern diagram showing one embodiment of the word driver corresponding to FIG. 101.

FIG. 104 is a partial pattern diagram showing one embodiment of the word driver corresponding to FIG. 101.

FIG. 105 is a partial pattern diagram showing one embodiment of the word driver corresponding to FIG. 101.

FIG. 106 is a partial pattern diagram showing an embodiment of the X decoder corresponding to FIG. 101.

FIG. 107 is a partial pattern diagram showing one embodiment of the X decoder corresponding to FIG. 101;

FIG. 108 is a pattern diagram showing one embodiment of a memory cell array section and a word clear circuit in a word line direction in a dynamic RAM according to the present invention.

[Explanation of symbols]

DV1... Y address driver, DV2... X address driver, DV3... Mat selection driver, 1... External power supply pad VCCE, 2... External power supply pad VCCE, 3... Internal step-down power supply circuit (VCC), 4. (V
DL), 5: VCC wiring, 6: VDL wiring, 7: Power supply pad VCCE for data output buffer, 11: Word clear, pad for ground potential supply for word line latch, 12
... ground potential pad for common source of sense amplifier, 13
... data output buffer pad, 14 ... internal step-down power supply circuit, ground potential pad for address buffer, 15 ... ground potential pad for other circuits, 21 ... mold resin, 22
... lead frame, 23 ... chip, 24 ... film, 2
5 Gold wire, 26 Adhesive A, 27 Adhesive B, 28
... Insulator, 29 ... Adhesive C, 30 ... Adhesive D, 31 ... Mold resin, 32 ... Lead frame, 33 ... Chip, 3
4 Film, 35 Gold wire, 36 Bus bar lead, 37 Suspended lead, 38 Bonding pad, 3
9: Index, 41: P substrate, 42: P-type WEL
L, 43: N-type well, 44: N ⁺ diffusion layer, 45: P
⁺ Diffusion layer, 46 ... polysilicon (gate, word line),
47 ... polysilicon (pad contact), 48 ... polysilicon (capacitor store node), 49 ... polysilicon (capacitor plate), 50 ... polycide (bit line), 51 ... first layer metal (tungsten), 52
... second layer metal (aluminum), 5 ... first gate insulating film (MOSFET), 54 ... second gate insulating film (capacitor), 61 ... bit line (boricide), 62 ... column selection line (first layer metal) ), 63 ... word line (polysilicon), 64 ... MOSFET, 65 ... bit line contact, 66 ... diffusion layer, 67 ... input / output line, 68 ... word shunt, 69, 70 ... dummy wiring layer, 71 ... diffusion layer ,
72 word line (polysilicon), 73 bit line (polycide), 74 word line shunt (second metal layer), 75 column select line (first metal layer), 76
Bit line contact (using pad polysilicon), 77
... Diffusion layer for guard ring of memory cell array, 78 ... Step buffer wiring (polysilicon), 79 ... Gate of word driver, 80 ... Word line (output side wiring of driver MOSFET), 81 ... Diffusion layer contact, 91 ... Word Clear signal line (second metal layer), 92 ground line (first metal layer), 93 word clear gate (polysilicon), 94 diffusion layer, 95 step buffer wiring (polysilicon), 96 word line shunt layer (second metal layer), 97 word line (polysilicon), 98 diffusion layer for guard ring of memory cell array, 99 wiring for reducing step (polysilicon and guard ring shunt layer), 10
0: Bit line (polycide).

 ──────────────────────────────────────────────────の Continuing from the front page (72) Inventor Yasunori Yamaguchi 2326 Imai, Ome-shi, Tokyo Inside the Hitachi, Ltd.Device Development Center (72) Inventor Kazuyoshi Oshima 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd.Device Development Center, Ltd. (72) Inventor Takashi Yamazaki 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Eiji Miyamoto 5-2-1 Kamimihoncho, Kodaira-shi, Tokyo Musashi Factory, Hitachi, Ltd. (72) Inventor Yuji Sakai 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Jiro Sawada 2326 Imai, Ime-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Jun Eto 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Hitachi, Ltd. Central Research Laboratory (72) Inventor Masashi Horiguchi 1-280, Higashi-Koikekubo, Kokubunji-shi, Tokyo Hitachi, Ltd. Inside the Central Research Laboratory (72) Inventor Jun Kumada 3300 Hayano Mobara City, Chiba Prefecture Inside Mobara Plant, Hitachi, Ltd. (72) Inventor Manabu Kakuzaki 2326 Imai, Ome City, Tokyo Inside Device Development Center, Hitachi, Ltd. (72) Inventor Yasuhiro Kasama 5-20-1, Josuihoncho, Kodaira-shi, Tokyo Inside Musashi Factory, Hitachi, Ltd. (72) Inventor Shinji 5-2-1, Josuihoncho, Kodaira-shi, Tokyo S.I. Engineering Co., Ltd. (72) Inventor Hiroshi Yoshioka 5-20-1, Josuihonmachi, Kodaira-shi, Tokyo Nichi-Cha L.S.E. Engineering Co., Ltd. (72) Inventor Hiromi Saito Tokyo Miyako Kodaira 5-72-1, Jitsumizu-Honcho, Tokyo Nippon Cho LSI Engineering Co., Ltd. (72) Inventor Mitsuhiro Takano 5-20-1, Josuihoncho, Kodaira-shi, Tokyo I-Engineering Co., Ltd. (72) Inventor Makoto Morino 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Nichi-Cha-LSI Engineering Co., Ltd. (72) Inventor Shinichi Miyatake Kodaira, Tokyo 5-20-1, Kamizuhoncho Nippon Super SLS Engineering Co., Ltd. (72) Inventor Tetsuro Matsumoto 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Device Development Center, Hitachi, Ltd.

Claims (29)

[Claims] 1. A semiconductor device formed in a substantially rectangular area of a main surface of a semiconductor substrate, the first area extending in a first direction along a center line crossing a short side of the rectangular area; Along the center line crossing the long side of the rectangular area, the first
A second region extending in a second direction intersecting with the region; third, fourth, fifth, and sixth regions divided by the first region and the second region in the rectangular region; First, second, third, and fourth memory arrays provided in each of the fourth, fifth, and sixth regions; and a tangent to each of the first region and the first to fourth memory arrays. First, second, third, and fourth decode circuits provided along the first region, the fifth region, and the sixth region provided along respective tangent lines of the second region and the first to fourth memory arrays. , A seventh and an eighth decoding circuit, and a plurality of bonding pads provided in the second region. 2. The memory device according to claim 1, wherein each of the first to fourth memory arrays includes the first memory array.
A semiconductor device comprising: a plurality of word lines extending in a direction; and a plurality of data lines extending in the second direction. 3. The semiconductor device according to claim 1, wherein the first to fourth decoding circuits are Y decoders, and the fifth to eighth decoding circuits are X decoders. . 4. A semiconductor device formed in a substantially rectangular area of a main surface of a semiconductor substrate, the first area extending in a first direction along a center line crossing a short side of the rectangular area; Along the center line crossing the long side of the rectangular area, the first
A second region extending in a second direction intersecting with the region; third, fourth, fifth, and sixth regions divided by the first region and the second region in the rectangular region; In each of the sixth regions, the seventh, eighth, ninth, and first regions extending along a center line crossing the short side direction thereof.
Region 0, first and second memory arrays provided on both sides of the seventh region in the third region, and third and second memory arrays provided on both sides of the eighth region in the fourth region. A fourth memory array, fifth and sixth memory arrays provided on both sides of the ninth area in the fifth area, and fifth and sixth memory arrays provided on both sides of the tenth area in the sixth area. 7th and 8th memory arrays, 1st, 2nd, 3rd, and 4th decoding circuits provided in each of the 7th to 10th regions; the 2nd region; and the 1st to 8th memories Fifth, sixth, seventh, eighth, ninth, tenth, eleventh, and twelfth decode circuits provided along respective tangents to the array, and a plurality of bonding circuits provided in the second region And a pad. 5. The memory device according to claim 4, wherein each of the first to eighth memory arrays includes the first memory array.
A semiconductor device comprising: a plurality of word lines extending in a direction; and a plurality of data lines extending in the second direction. 6. The semiconductor device according to claim 4, wherein the first to fourth decoding circuits are Y decoders, and the fifth to twelfth decoding circuits are X decoders. . 7. The memory device according to claim 4, wherein each of the first to eighth memory arrays includes the first memory array.
A semiconductor device, comprising: a plurality of data lines extending in a direction; and a plurality of word lines extending in the second direction. 8. The semiconductor device according to claim 4, wherein the first to fourth decoding circuits are X decoders, and the fifth to twelfth decoding circuits are Y decoders. . 9. A semiconductor device formed in a substantially rectangular area of a main surface of a semiconductor substrate, the first area extending in a first direction along a center line crossing a short side of the rectangular area; Along the center line crossing the long side of the rectangular area, the first
A second region extending in a second direction intersecting with the region; third, fourth, fifth, and sixth regions divided by the first region and the second region in the rectangular region; Seventh, eighth, ninth, and tenth regions extending along a center line crossing each long side of the sixth region; and first and second regions provided on both sides of the seventh region in the third region. A second memory array; third and fourth memory arrays provided on both sides of the eighth area in the fourth area; and a third memory array provided on both sides of the ninth area in the fifth area. 5th and 6th memory arrays, 7th and 8th memory arrays provided on both sides of the 10th area in the 6th area, the 1st area, and the 1st to 8th memory arrays The first, second, third, Fourth, fifth, sixth, seventh and eighth decoding circuits, and ninth,
A semiconductor device comprising: tenth, eleventh, and twelfth decode circuits; and a plurality of bonding pads provided in the second region. 10. The memory device according to claim 9, wherein each of the first to eighth memory arrays includes the first memory array.
A semiconductor device comprising: a plurality of word lines extending in a direction; and a plurality of data lines extending in the second direction. 11. The semiconductor device according to claim 9, wherein the first to eighth decoding circuits are Y decoders, and the ninth to twelfth decoding circuits are X decoders. . 12. The memory device according to claim 9, wherein each of the first to eighth memory arrays includes the first memory array.
A semiconductor device, comprising: a plurality of data lines extending in a direction; and a plurality of word lines extending in the second direction. 13. The semiconductor device according to claim 9, wherein the first to eighth decoding circuits are X decoders, and the ninth to twelfth decoding circuits are Y decoders. . 14. A semiconductor device formed in a substantially rectangular area of a main surface of a semiconductor substrate, the first area extending in a first direction along a center line crossing a short side of the rectangular area; Along the center line crossing the long side of the rectangular area, the first
A second region extending in a second direction intersecting with the region; third, fourth, fifth, and sixth regions divided by the first region and the second region in the rectangular region; In each of the fourth, fifth and sixth regions, a seventh, eighth and ninth region extending along a center line crossing the short side thereof
And a tenth region, and in each of the third, fourth, fifth, and sixth regions, eleventh, twelfth,
Thirteenth and fourteenth regions, and first, second, and third regions provided in regions divided by the seventh region and the eleventh region in the third region.
And a fifth memory array provided in a region divided by the eighth region and the twelfth region in the fourth region.
A ninth, a tenth, an eleventh, and a twelfth memory array provided in a region divided by the ninth region and the thirteenth region in the fifth region; and a sixth region. Within the thirteenth and first regions provided in the region divided by the tenth region and the fourteenth region.
Fourth, fifteenth and sixteenth memory arrays, first, second, third and fourth decoding circuits provided corresponding to the seventh to tenth regions, and corresponding to the eleventh to fourteenth regions Fifth, provided
A semiconductor device comprising: sixth, seventh, and eighth decoding circuits; and a plurality of bonding pads provided in the second region. 15. The memory array according to claim 14, wherein each of the first to sixteenth memory arrays includes a plurality of word lines extending in the first direction and a plurality of data lines extending in the second direction. A semiconductor device comprising: 16. The semiconductor device according to claim 14, wherein the first to fourth decoding circuits are Y decoders, and the fifth to eighth decoding circuits are X decoders. . 17. The memory device according to claim 14, wherein each of the first to sixteenth memory arrays includes a plurality of data lines extending in the first direction, a plurality of word lines extending in the second direction, A semiconductor device comprising a plurality of memory cells provided at predetermined intersections of the plurality of data lines and the plurality of word lines. 18. The semiconductor device according to claim 14, wherein the first to fourth decoding circuits are X decoders, and the fifth to eighth decoding circuits are Y decoders. . 19. The method according to claim 1, wherein:
In the above, the third region and the fourth region face each other across the second region, the fifth region and the sixth region face each other across the second region, and the third region and the third region. A fifth region faces the first region, the fourth region and the sixth region face the first region, and a plurality of main amplifiers are arranged in the second region. A semiconductor device, comprising: 20. The main amplifier according to claim 19, wherein a main amplifier of the plurality of main amplifiers disposed between the third region and the fourth region is configured to access a memory array in the third region and to control the fourth region. A semiconductor device which is shared by being selectively switched for access to a memory array in a region. 21. A semiconductor device formed in a substantially rectangular area of a main surface of a semiconductor substrate, the first area extending in a first direction along a center line crossing a short side of the rectangular area; Along the center line crossing the long side of the rectangular area, the first
A second region extending in a second direction intersecting the region; third, fourth, fifth, and sixth regions divided by the first region and the second region in the rectangular region; A plurality of bonding pads provided in the third region, the third region and the fourth region are opposed to each other across the second region, and the fifth region and the sixth region are sandwiched between the second regions. The third region and the fifth region are opposed to each other with the first region interposed therebetween, and the fourth region and the sixth region are opposed to each other with the first region interposed therebetween. Each of the fourth, fifth and sixth regions includes a memory array including a plurality of dynamic memory cells provided at predetermined intersections of a plurality of word lines and a plurality of data lines, and a plurality of sense amplifiers, It is characterized in that multiple main amplifiers are arranged in two areas Semiconductor device. 22. The main amplifier according to claim 21, wherein, among the plurality of main amplifiers, a main amplifier disposed between the third region and the fourth region is configured to access a memory array in the third region and to control the fourth region. A semiconductor device which is shared by being selectively switched for access to a memory array in a region. 23. The main amplifier according to claim 21, wherein the main amplifier amplifies a signal read to the plurality of data lines by the corresponding sense amplifier, and then selects one of the plurality of data lines. A semiconductor circuit, which is a circuit for amplifying a signal from a data line to output to the outside. 24. The semiconductor device according to claim 21, wherein the semiconductor device comprises: a first region provided along a tangent to each of the first region and the first to fourth memory arrays. , Second, third, and fourth decoding circuits; fifth, sixth, seventh, and eighth decoding circuits provided along respective tangents to the second region and the first to fourth memory arrays. A semiconductor device having a circuit. 25. The semiconductor device according to claim 24, wherein the first to fourth decoding circuits are Y decoders, and the fifth to eighth decoding circuits are X decoders. 26. Any one of claims 1 to 25.
2. The semiconductor device according to claim 1, wherein the plurality of bonding pads are arranged along the second direction. 27. Any one of claims 1 to 26.
3. The semiconductor device according to claim 1, wherein peripheral circuits of a dynamic RAM are arranged in the first and second regions. 28. Any one of claims 1 to 27
2. The semiconductor device according to claim 1, wherein the semiconductor device is mounted on a package having a lead-on-chip (LOC) structure. 29. Any one of claims 1 to 28
3. The semiconductor device according to claim 1, wherein the semiconductor device is a dynamic RAM.