JPH10256302A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the bonding strength between input/output terminal electrodes and inner leads by forming an Au or Sn cover layer on these electrodes of a semiconductor chip and on the inner leads laid on a wiring substrate and forming their connections by the Au-Sn diffusion reaction. SOLUTION: On an insulative film 7 of a polyimide resin, etc., a lead pattern are formed. An Sn or Au plating is applied to inner leads 8a and Cu wiring 8a1. A semiconductor chip 4 has bumps 4a as input/output terminal electrodes made by forming an Ni plating 4a2 on deposited Al electrodes through a metal sputtered film and forming an Au or Sn plating 4a1 on the Ni plating. Connections of the inner leads 8a with bumps 4a are formed by the Au-Sn diffusion reaction to improve the connecting strength.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output terminal electrode of a semiconductor chip and a TA serving as a relay board (interposer).
The present invention relates to a semiconductor device for connecting an inner lead on a B (Tape Automated Bonding) tape or a wiring layer formed on a wiring substrate such as a motherboard with a gold-tin alloy and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 7 shows a TCP (Ta) as a first conventional example.
1 shows a semiconductor device having a pe carrier package) structure. The semiconductor device 1 has a structure in which a TCP 3 is mounted on a motherboard 2. The TCP 3 has a configuration in which a semiconductor chip 4 is mounted on a TAB tape 5 serving as a relay board, and the periphery thereof is packaged with a sealing resin 6. The TAB tape 5 includes an insulating film 7 made of a polyimide resin or the like in which a square device hole 7a is formed for mounting the semiconductor chip 4, and a lead 8 in which an inner lead 8a and an outer lead 8b are formed. ing. Then, the insulating film 7 and the lead 8 are bonded by an adhesive layer made of a thermosetting resin adhesive such as an epoxy resin, and the semiconductor chip 4 is connected to the inner lead 8a through the device hole 7a of the TAB tape 5, The outer leads 8b are connected to the wiring pattern 2a on the motherboard 2. Semiconductor device 1 having this TCP structure
The manufacturing method of the will be described below.

The semiconductor chip 4 usually has a size of 100 to 50.
An input / output terminal electrode having about 0 pins is provided, and a bump 4a having a protruding shape is formed on each input / output terminal electrode. This is for the purpose of facilitating connection with the inner lead 8a and improving the reliability of the connection. The bump 4a is usually made of gold
It is formed by electroplating with a thickness of about μm.

The leads 8 are formed by etching a copper foil adhered to the insulating film 7 in a predetermined pattern by a photochemical etching method, and then applying an electroless tin plating of 0.3 to 0.3 mm.
It is formed by applying a thickness of 0.5 μm.

Next, the tip of the inner lead 8a is connected to the gold bump 4a using a heating tool (joining tool) having a tool temperature (joining temperature) of 500 ° C. This is because the connection is made in a short time of about 2 seconds using the melting point of 285 ° C. of the eutectic composition of 90% by weight of gold (the remaining tin) in the equilibrium diagram of gold and tin. At a tool temperature of 450 to 500 ° C., a reaction layer having a eutectic composition of 90% by weight of gold (remaining tin) grows thickly at the bonding interface, and strong bonding is performed. For this reason, in this bonding system, a temperature of about 500 ° C. must be set, but this temperature is very low for the insulating film 7 having a glass transition point of about 230 ° C. (hereinafter, simply referred to as Tg). It is hot. However, since the inner leads 8a protrude into the device holes 7a and the bonding time is about 2 seconds, the insulating film 7 can withstand without burning.

[0006] The bonding method of the semiconductor chip 4 and the inner leads 8a includes a batch bonding method in which all pins of the input / output terminal electrodes are simultaneously bonded together in a short time of about 2 seconds, and a single bonding method of the inner leads 8a. There is a single point bonding method in which books are joined at about 0.2 seconds / lead. The single-point bonding method requires about 100 seconds for 500 pins and increases the bonding time, so that it is not used much in mass production.

The outer lead 8b is bent in the direction of the motherboard 2 and then connected to the wiring pattern 2a of the motherboard 2 by a reflow method of printing a 37Pb-63Sn eutectic solder paste. Thus, the semiconductor device 1 having the TCP structure is manufactured.

FIG. 8 shows a semiconductor device having a TAB structure as a second conventional example. In this semiconductor device 1, a semiconductor chip 4 is mounted on a TAB tape 5 serving as a relay board.
This is for a CD (liquid crystal display) panel. The TAB tape 5 cut for each chip is mounted on a motherboard for an LCD panel, outputs a signal from a semiconductor chip 4 as a driver IC, turns on and off a display element of the LCD panel, and transmits or blocks a backlight. Drive is performed. The TAB tape 5 is obtained by forming leads 8 including inner leads 8a and outer leads 8b on an insulating film 7 made of a polyimide resin or the like. The insulating film 7 includes a square device hole 7 a for connecting the semiconductor chip 4 and an outer lead hole 7 provided along the cutting line of the TAB tape 5.
b and feed holes 7c provided on both sides. Then, as described in FIG. 7, the insulating film 7 and the lead 8 are connected by an adhesive layer, and the tip of the inner lead 8a and the gold bump 4a are connected in the same manner as described in FIG. The connection is performed using a joining tool having a joining temperature of 450 to 500 ° C.

As a third conventional example, a bare chip (a non-packaged semiconductor chip) is mounted on a wiring board made of an organic material such as a glass epoxy resin without using a TCP.
Some semiconductor devices are directly mounted. In the case of this semiconductor device, the bonding tool is applied from the back surface of the wiring board to connect the bumps of the input / output terminal electrodes of the semiconductor chip and the inner leads formed on the wiring board. For this connection, eutectic solder (37Pb-63) is usually used in consideration of the heat resistance of the wiring board.
Sn) is often used, and the melting point of this eutectic composition is 180 ° C.
, The organic material such as glass epoxy resin is not damaged. However, the heat resistant temperature is 18
It is problematic that the temperature is as low as 0 ° C. In addition, 150 of solder
There is a problem of embrittlement due to coarsening of crystal grains at a temperature of 150 ° C. or more, and it cannot be used at a temperature of 150 ° C. or more from the viewpoint of reliability.

[0010]

However, according to the first conventional example, since the bonding temperature when connecting the inner lead 8a and the bump 4a provided on the input / output terminal electrode of the semiconductor chip 4 is high, the following is required. There are various problems.

(1) The device hole 7a is required, resulting in an increase in cost and a decrease in the strength of the insulating film 7. Since the bonding temperature between the semiconductor chip 4 and the inner lead 8a is high, it is necessary to project the inner lead 8a into the device hole 7a and connect it to the device hole 7a.
a has an absolutely necessary structure. If the device hole 7a is not formed, the bump 4a of the semiconductor chip 4 is directly connected to the inner lead 8a of the lead 8 on the insulating film 7.
In the case where the connection is performed by using a joining tool at 450 to 500 ° C., the insulating film 7 made of the polyimide resin is burned and carbonized, so that it is impossible to manufacture the TCP 3 with high reliability. This device hole 7a
The insulating film 7 with the adhesive is processed by a punching punching die. In addition to the expensiveness of the die, since the holes are formed in the film 7, the tensile strength and the bending strength of the film 7 are reduced. There's a problem.

(2) Strict control of joining temperature and joining time is required. As described above, since the temperature of the joining tool is high, even if the device hole 7a is provided and the inner lead 8a is formed, the inner lead 8a made of copper has good thermal conductivity. If the temperature is slightly higher than ℃ or the time is slightly increased, there is a problem that heat is conducted through the inner leads 8a and the insulating film 7 and the adhesive are burned and carbonized. The adhesive is usually an epoxy resin, but the Tg is about 170 ° C.
It is still inferior to polyimide resin in heat resistance, and still has a problem as an adhesive for high-temperature bonding. Further, if the bonding time is set short due to the problem of damage to the adhesive, there is also a problem that a predetermined bonding strength cannot be obtained due to poor bonding.

(3) A high flatness is required for the joining tool. The design of a joining tool at a tool temperature of 450 to 500 ° C. requires a very high level of technology. That is, in the batch bonding method, the flatness of the bonding tool is very important due to the problem of destruction of the semiconductor chip 4, but it is 450 to 500.
At ° C., the effect of thermal expansion is very large, and maintenance of flatness at this temperature requires considerable processing know-how. If the flatness of the tool is poor, uneven stress is applied to the semiconductor chip 4 and the chip 4 often breaks. Normally, a tool flatness of 1 μm or less is required, and heat is transmitted to the stage directly below the chip 4, so that it is necessary to adjust the flatness of the stage. In this case, the cost including the tool and the stage immediately below the chip 4 is also: Very expensive. Also,
Since the tool temperature is very high, the overall price of the joining machine is increased by designing the thickness of the machine parts to be large in order to maintain the mechanical accuracy in the periphery.

(4) Reliability decreases due to disconnection of wiring. When the device hole 7a is provided and the inner lead 8a is formed, since the film 7 is not provided directly below the inner lead 8a, the inner lead 8a has a protruding shape in which only one of the leads is supported. The tip of the lead 8a is very easy to bend. In addition to problems such as misalignment in alignment with the bumps 4a due to this, breakage of the leads 8a and peeling of the joints with the semiconductor chip 4 may occur at the time of handling during transportation until resin sealing after joining. However, there is a problem that the reliability is reduced.

(5) The reliability of the temperature cycle decreases. A normal semiconductor device performs a temperature cycle test at −55 to 150 ° C. to ensure reliability in a cold region. In the conventional structure, in the temperature cycle test, the protruding inner lead 8a receives tension due to thermal stress. That is, since the coefficient of thermal expansion of the semiconductor chip 4 is 3 PPM / ° C. and the coefficient of thermal expansion of the polyimide resin of the insulating film 7 is 20 PPM / ° C., the copper inner lead 8 a interposed therebetween is subjected to a temperature cycle test. At the point of stress concentration. Usually, in this temperature cycle test, reliability of about 1000 cycles is required, and for this purpose, a method of solidifying the periphery with the sealing resin 6 is used. However, the sealing resin 6 is also limited, and if the amount of the sealing resin 6 applied is small, the inner lead 8a is similarly broken.

(6) Multi-chip mounting is not possible.
In the conventional structure, the number of semiconductor chips 4 mounted on one TAB tape 5 is limited to one. The reason is that the device hole 7a is required. That is, when a plurality of device holes 7a are provided and a plurality of chips 4 are mounted, the film 7 becomes weak, and while the plurality of chips 4 are bonded, the inner lead 8a already bonded to the chip 4 is broken during handling. This is due to problems such as Further, when a plurality of chips 4 are mounted, there is a problem that the die for removing the device holes 7a becomes more expensive. Therefore, the mounting of one semiconductor chip 4 is the limit, and there is a problem that a high-density flexible wiring board such as a multi-chip module cannot be manufactured. Therefore, as shown in FIG. 7, the TCP 3 is mounted on the motherboard 2 in units of one. Therefore, when a multi-chip is used, a plurality of semiconductor chips 4 must be mounted on the motherboard 2 in this manner, and the system configuration price increases accordingly.

Also in the second conventional example, since the bonding temperature between the inner lead 8a and the bump 4a is high and the insulating film 7 has the device hole 7a, the same as described above is used. There's a problem.

Further, according to the third conventional example, there is a problem that it is difficult to mount a bare chip. That is, in the case of a semiconductor device directly mounted on a wiring substrate made of an organic material by a bare chip without using a TCP, the eutectic solder (3
Since the 7Pb-63Sn) connection is used, there is a problem in that the reliability in the above-described temperature cycle test and the high-temperature holding test at 150 ° C. decreases. In addition, when mixed with other components, the solder paste printing reflow mounting temperature 2
Since it cannot withstand 50 ° C., problems such as falling off of bare chips have occurred. These issues are summarized below. (i) Since the melting point of the eutectic solder is as low as 180 ° C., the connection is disconnected in a high temperature atmosphere. For this reason, after the connection, measures such as filling the bonding interface with resin are required. (ii) In a reliability test in a high-temperature atmosphere of 150 ° C. or more,
The eutectic structure of the solder is coarsened and oxidized, and the connection strength is reduced. (iii) When a flexible wiring board having a semiconductor chip connected to a film is further mounted on a motherboard, a solder reflow furnace at a temperature of usually 230 to 250 ° C. is used. (iv) In the eutectic solder (37Pb-63Sn) connection, since the flowability of the solder is good, short-circuiting between wirings easily occurs, and fine connection is difficult.

Further, according to the first to third conventional examples, there is a problem that flexibility is poor. That is, TAB tape 5
Has an adhesive layer, the thickness of which is generally about 20 μm, and the entire thickness of the TAB tape 5 is increased by this amount, and the adhesive layer is made of a thermosetting material such as epoxy resin having a high flexural modulus. Since it is made of a resin adhesive, it cannot be flexed freely and has poor flexibility. In recent years, there has been a growing demand for miniaturization of consumer electronic devices such as mobile phones, and there is a strong demand for flexible wiring boards and the like that can be freely bent. This problem is very important.

Accordingly, an object of the present invention is to obtain a high bonding strength of a connection portion between an input / output terminal electrode of a semiconductor chip and an inner lead formed on a wiring board, and to obtain a strength such as tension and bending of the wiring board. A semiconductor device capable of being mounted on a multi-chip, having environmental resistance that can be applied to cold regions and the like and reliability that does not cause a connection failure in a manufacturing process, and a method of manufacturing the same by improving flexibility. Is to provide.

[0021]

In order to achieve the above-mentioned object, the present invention provides a semiconductor device having an input / output terminal electrode and a wiring board such as a TAB tape, a rigid wiring board or a flexible wiring board having no device holes. In the semiconductor device connected to the formed inner lead, the input / output terminal electrode is provided with a coating layer of gold or tin, and the inner lead is provided with a coating layer of tin or gold. A connection part between the terminal electrode and the inner lead is provided by a diffusion reaction between the gold and the tin, and a semiconductor device is provided. In order to achieve the above object, the present invention provides a semiconductor device in which an input / output terminal electrode of a semiconductor chip is connected to a lead formed on a wiring board serving as a motherboard, wherein the input / output terminal electrode is made of gold or tin. That the lead is provided with a coating layer of tin or gold, and that a connection portion between the input / output terminal electrode and the lead is formed by a diffusion reaction between the gold and the tin. A semiconductor device is provided. In order to achieve the above object, the present invention provides an input / output terminal electrode of a semiconductor chip and an inner lead formed on a wiring board serving as an interposer such as a TAB tape, a rigid wiring board or a flexible wiring board without a device hole. And the input / output terminal electrodes are provided with a gold or tin coating layer in the semiconductor device in which the interposer is connected to the leads of the wiring board which are connected to the leads formed on the wiring board which is the motherboard. A coating layer of tin or gold is applied to the inner lead, and a connecting portion between the input / output terminal electrode and the lead is formed by a diffusion reaction between the gold and the tin;
A semiconductor device is provided, wherein the wiring board serving as the interposer and the motherboard has a configuration connected by a ball grid array. The present invention
In order to achieve the above object, in a semiconductor device in which an input / output terminal electrode of a semiconductor chip is connected to an inner lead formed on a flexible wiring board having no device hole, the input / output terminal electrode is made of gold. Alternatively, a tin coating layer is applied, the inner lead is provided with a tin or gold coating layer, and a connection portion between the input / output terminal electrode and the lead is formed by a diffusion reaction between the gold and the tin. A semiconductor device, wherein the flexible wiring board is connected to a liquid crystal substrate and the semiconductor chip is configured as a liquid crystal drive circuit. The present invention
In order to achieve the above object, in a semiconductor device in which an input / output terminal electrode of a semiconductor chip is connected to a lead formed on a wiring substrate such as a glass wiring substrate having no device hole, the input / output terminal electrode Is provided with a coating layer of gold or tin, the lead is provided with a coating layer of tin or gold, and a connecting portion between the input / output terminal electrode and the lead is formed by a diffusion reaction between the gold and the tin. A semiconductor device characterized by being formed is provided.

According to the present invention, in order to achieve the above object, the input / output terminal electrodes of a semiconductor chip are connected to inner leads formed on a TAB tape, a rigid wiring board or a flexible wiring board having no device hole. In the method for manufacturing a semiconductor device, a gold or tin coating layer is applied to the input / output terminal electrodes, a tin or gold coating layer is applied to the inner leads, and before the gold or tin coating layer is applied. A method for manufacturing a semiconductor device, characterized in that a write / output terminal electrode and the inner lead provided with the tin or gold coating layer are connected by a diffusion reaction between the gold and the tin.

[0023]

FIG. 1 shows a semiconductor device according to a first embodiment of the present invention. The semiconductor device 1 has a semiconductor chip 4 mounted on a TAB tape 5 serving as a relay board,
For example, a TAB structure for an LCD panel is used. The TAB tape 5 is provided with no device hole, and is provided with an insulating film 7 made of polyimide resin or the like having a thickness of 40 to 50 μm, as described with reference to FIG.
A lead 8 including an inner lead 8a and an outer lead 8b made of copper having a thickness of 8 to 25 μm is formed. The insulating film 7 includes an outer lead hole 7b provided at a cutting position of the TAB tape 5, and feed holes 7c provided on both sides. The lead 8 is formed on the insulating film 7 without an adhesive layer. The input / output terminal electrodes of the semiconductor chip 4 are arranged on the tip of the inner lead 8a on the insulating film 7 with the bump 4a facing down, and a heating / pressing tool (joining tool) is applied from the back surface of the insulating film 7. And connected.

Since the inner leads 8a and the bumps 4a can be connected by applying a bonding tool from the back surface of the insulating film 7, a bonding structure that can be connected at a tool temperature of 250 ° C. or less, that is, a tin composition ratio. A gold / tin connection structure was used in which the ratio of tin to 60 to 90% by weight (gold 10% to 40% by weight) was increased.

FIGS. 2A and 2B show a state immediately before the connection between the bump 4a of the semiconductor chip 4 and the inner lead 8a. Pattern of the lead 8 formed on the insulating film 7, and the inner leads 8a of the lead 8 is subjected to tin plating 8 _a2 of 0.75~1.5μm on the copper wiring 8 _a1.

The semiconductor chip 4 shown in FIG. 2A is formed by gold plating with a thickness of 10 to 20 μm on an aluminum deposition electrode (not shown) through a suitable metal sputtered film described later. The semiconductor chip 4 shown in FIG. 2 (b) has an inexpensive plating _4a2 made of nickel or the like applied on an aluminum deposition electrode (not shown) through a suitable metal sputtering film described later. over, shows a bump 4a formed by performing gold plating 4 _a1 of 0.3~1.5μm thickness.

With this connection structure, the melting point of tin is 232
℃, the connection is possible at a tool temperature of 250 ° C. or less. The time required for this connection is about 5 seconds or less, and even a chip 4 having 500 semiconductor input / output terminals can be connected in less than 5 seconds.

FIG. 3 shows bumps 4a and inner leads 8a.
This shows the state of the bonding interface with the substrate. The connecting portion 9 is a protruding portion (referred to as a “fillet”) 9 a of the reaction molten layer of gold and tin.
And a bonding interface 9b. As a result of investigating the connecting portion 9, the fillet 9a was found to have a first eutectic point (melting point 217).
5% by weight of gold centered on the composition of C)
It was found that the bonding interface 9b had a composition of 20 to 40% by weight of gold (remaining tin).
This is presumably because the gold-tin reaction composition having a low melting point was removed to the outside due to the effect of the joining tool to which a load was applied, and then gold was diffused and formed in the molten layer remaining at the joining interface 9b. Since the bonding interface 9b has a high concentration of gold,
It has a heat resistance temperature of ° C. Also, the outer fillet 9
a has a role of mechanically reinforcing the bonding strength at a temperature of 217 ° C. or lower because it covers the side surface.

The plating layer 4 _a2 of nickel FIG. 2 (b), a copper plating may be replaced by chromium plating. However, a minimum gold thickness is required for the gold-tin reaction. For example, the thickness of tin plating is 0.75 to 1.5 μm
In this case, the thickness of the gold is preferably about 1.0 μm.

According to the first embodiment, the following effects can be obtained due to the lowering of the bonding temperature. (1) Since there is no need to provide a device hole, a mold for the device hole is not required, cost can be reduced, and the tensile strength and bending strength of the insulating film 7 can be improved. (2) It is easy to control the joining temperature and joining time. (3) The flatness of the joining tool can be reduced. (4) Since the inner lead 8a does not have a protruding shape, the disconnection of the wiring due to the misalignment with the bump 4a hardly occurs. (5) The reliability of the temperature cycle is improved. That is, since the film 7 is located directly below the inner leads 8a, stress is not directly concentrated on the inner leads 8a, and the reliability of the temperature cycle is excellent. Further, since the bonding structure is made of gold and tin, the melting point is as high as 217 ° C. (40% by weight Pb—S).
n is sufficiently higher than 180 ° C.), and can sufficiently withstand the requirement of 1000 hours (the joint is not broken and the electrical connection is maintained) in a normal high-temperature holding test at 150 ° C. in the atmosphere. . (6) Multi-chip mounting becomes possible. That is, since the insulating film 7 has no device hole, it can be freely wired on the flat film 7, and the degree of freedom in mounting multi-chip wiring is high. Therefore, the wiring can be routed directly below the mounted chip 4, so that the wiring length is shortened, and the wiring layout area is large, so that the wiring board area can be reduced and the electronic device can be downsized. . (7) Bare chips can be mounted.

In addition to the above effects, since the adhesive layer is eliminated from the TAB tape 5, the thickness of the entire TAB tape 5 is reduced, and the flexibility can be improved.

FIG. 4 shows a semiconductor device according to a second embodiment of the present invention. FIG. 1 shows a state before the connection between the semiconductor chip 4 and the flexible wiring board 5.
The semiconductor device 1 has a chip size package (CSP; Chip S) whose package is the same size as the semiconductor chip 4.
ize Package). Here, a flexible wiring board 5 is used as a wiring board on which the semiconductor chip 4 is mounted. The flexible wiring board 5 is disposed directly below the chip 4, the inner lead 8 a is drawn into the inside of the bump 4 a of the chip 4, and the lower wiring is connected to the lower wiring via the via hole 51. The ball 54 is formed in the terminal of the lower wiring by conducting. The bump 4a and the inner lead 8a are connected in the same manner as in the first embodiment. In recent years, the practical use of this small package has rapidly advanced for use in portable electronic devices such as mobile phones.

The via hole 51 has a diameter of 0.05 to 50 μm by a carbon dioxide laser or the like on a film made of a thin insulating material such as a polyimide resin having a thickness of about 50 μm.
It is manufactured by forming a pattern after forming a hole of about 0.3 mm and then performing copper plating.

The ball 54 has a role as a terminal for mounting on a motherboard.
ray). The ball 54 usually has 37
A solder ball having a eutectic composition of Pb-63Sn is used.

According to the second embodiment, the following effects can be obtained. (1) Since the flexible wiring board 5 is very flexible,
When mounted on a motherboard, absorbs thermal stress caused by the difference in thermal expansion coefficient between chip 4 and motherboard,
The reliability can be improved with respect to a temperature cycle of (−55 to 150 ° C.) × 1000 cycles or more. (2) Since the structure is simple and the manufacturing process is simple, C
SP can be easily and inexpensively manufactured. (3) By setting the joining temperature to 250 ° C. or lower, it becomes possible to mount a bare chip on an organic material. (4) Since no device hole is required, flexibility is improved. (5) Conventionally, when a conductive paste is used, the limit is 1.3 mm pitch. However, a terminal can be led out by connecting a 0.06 mm pitch semiconductor electrode by gold-tin bonding.

[0036]

【Example】

(First Embodiment) This first embodiment corresponds to the first embodiment of FIG. 3 from FIG. 1, and the semiconductor chip 4 has a chip size of 13 mm square, At 125
A pin having input / output terminal electrodes of a total of 500 pins is used. The input / output terminal electrodes have a 0.08 mm square electrode shape and are arranged at a pitch of 0.1 mm. The manufacturing method of the first embodiment will be described below.

First, gold bumps 4a are formed on input / output terminal electrodes (FIG. 2A). Since aluminum is deposited on the input / output terminal electrodes in the semiconductor circuit formation process, gold plating cannot be performed directly thereon, so that Ti, Cr, C
After sequentially applying a sputtered film of u and Ni to a thickness of 50 angstroms, electroplating of gold was performed to a thickness of 20 μm to form a bump 4a.

On the other hand, a flexible wiring board 5 connected to the bumps 4a was prepared in the following procedure. Insulating film 7
Then, using a polyimide resin (upilex manufactured by Ube Industries, Ltd.) having a thickness of 40 μm and a width of 70 mm, an underlayer is formed on the entire surface of the insulating film 7 by sputtering of Ti (thickness of 50 angstroms). Copper deposition was applied to a thickness of 3 μm. The purity of the copper vapor deposition raw material used for vapor deposition is 99.9999%. The use of 6N (Six Nine) high-purity copper makes it easier to form a fine wiring having a pitch of 50 μm in the subsequent photochemical etching, as shown in Japanese Patent Application Laid-Open No. 2-10845. This is because the high purity of copper reduces the number of structural defects in copper, and when forming wiring by photochemical etching, the surface and side surfaces of the etched pattern are smooth and a pattern having a uniform width is formed over the entire length. This is because it is difficult for defects such as broken wires to occur. Also,
Since the pattern is smooth, it is considered that abnormal deposition hardly occurs in surface plating such as tin plating, and short-circuiting of the pattern hardly occurs.

Next, a lead 8 was formed using a 70-mm wide copper single-sided vapor deposition film 7 as a material by using a TAB tape production line. As shown in FIG. 1, 0. Inner leads 8a for extracting signals from the semiconductor chip 4 were formed at an equal pitch of 1 mm. The width of the wiring of the inner lead 8a is 0.06 mm, and the interval is 0.04 mm (total pitch of 0.1 mm). Finally, the inner lead 8a of the lead 8 and the entire lead 8 were plated with 1.0 μm of electric tin. Thus, the flexible wiring board 5 that can be connected to the input / output terminal electrodes of the semiconductor chip 4 is completed.

Next, the connection between the flexible wiring board 5 and the semiconductor chip 4 was performed as follows using a semiconductor chip mounter (referred to as a flip chip mounter, a device for mounting a bare chip while recognizing the position on the substrate). .
Flexible wiring board 5 for mounter stage
Were placed with the pattern facing upward, and the semiconductor chip 4 was mounted from above with the input / output terminal electrodes facing down, and connection was performed using a joining tool in this state. The joining tool has a function of moving the semiconductor chip 4 to the position coordinates where the semiconductor chip 4 is sucked up and aligned, and the temperature rises as it is so that the joining tool can be connected. The tool temperature was set to 250 ° C., the joining time was 5 seconds, and the pressing force of the tool was 25 kg / cm ² .

According to the first embodiment, under the above conditions, the insulating film 7 is connected without being thermally damaged.
As for the connection strength, a peel strength of 10 gf per bump was obtained. According to the analysis result of the composition of the joint portion 9 by EPA, the fillet 9a is 10% by weight gold (remaining tin),
The bonding interface 9b was 35.5% by weight gold (remaining tin). 10% by weight of gold has a substantially eutectic composition of gold-tin (melting point: 217)
° C) and the molten tin reaches this composition while interdiffusing with gold, and since this composition is in a sufficiently liquid phase with a heating and pressing tool at 250 ° C, it flows out to the outside by pressurization to form a fillet 9a. After that, the gold further diffuses into the remaining tin, and the concentration of gold rises, the melting point rises, and it can be seen that it solidified.

Further, tin plating is applied to 0.5, 0.75,.
As a result of comparing at a thickness of 0, 1.5, 2.0 μm,
The range of 0.75 to 1.5 μm was optimal. Also,
At 0.5 μm, the peel strength decreased to 6 gf. Observation of the cross section of the joint 9 revealed that a sufficient fillet 9a was not formed when the tin plating was thin. On the other hand, when the thickness is 2.0 μm, the thickness of tin is too large, so that the number of layers of the fillet 9a increases, which causes a problem of short-circuiting with an adjacent input / output terminal electrode.

The bonding temperatures are 220, 230, 240, 2
The experiment was carried out at 50 and 260 ° C. (the total time was 5 seconds).
At 0 ° C, no connection was made and 230 and 240 ° C were optimal. Further, even at 260 ° C., no damage of the insulating film 7 due to heat was observed. Copper diffused from the wiring pattern may be found in the bonding interface 9b in an amount of 1 to 10% by weight. This is observed when the bonding temperature is high or when the time is extended, but there is no difference in reliability.

(Second Embodiment) This second embodiment corresponds to the first embodiment shown in FIG. 3 from FIG.
The bump 4a was formed by combining nickel plating _4a2 and gold plating _4a1 (FIG. 2 (b)). That is, 20 μm of gold
Is expensive and the time required for plating is long, which is not appropriate in terms of price. For this reason, nickel plating was applied to a thickness of 19 μm to substantially form bump-shaped protrusions, and then gold electroplating was applied to 1.0 μm to obtain a gold bump 4a. Also in this case, the thickness of the tin plating is set to 0.
As a result of performing the comparison at thicknesses of 5, 0.75, 1.0, 1.5, and 2.0 μm, as in the first embodiment, 0.75 to 1.0
The range of 1.5 μm was optimal.

(Third Embodiment) This third embodiment corresponds to the first embodiment of FIG. 3 from FIG.
This is a modification of the bump 4a in FIG. That is, an 18 μm electrolytic copper plating is formed on an aluminum vapor-deposited electrode (not shown), an electric nickel is plated thereon as a diffusion barrier layer of copper to a thickness of 1.0 μm, and then an electric Gold plating was applied to a thickness of 1.0 μm. As a result, similarly to the first example, the thickness of the tin plating was 0.75 to 1.5 μm.
Was optimal.

(Fourth Embodiment) The fourth embodiment corresponds to the first embodiment shown in FIG. 3 from FIG.
The leads 8 of the flexible wiring board 5 were formed using rolled copper foil. That is, a polyamic acid dissolved in an NMP solvent (nonamethylpyrrolidone) is applied thereon using an OFC (Oxygen Free Copper, oxygen concentration of 0.3 PPM or less) copper foil having a thickness of 18 μm and a purity of 99.9999% by weight. Then, the solvent was removed by evaporation by drying, and a polyimide layer was formed on the copper foil by an imidation curing reaction.
Since the thickness of the polyimide film that can be formed at one time is limited to 15 μm from the viewpoint of generation of bubbles, coating, drying and imidization were repeated three times to complete an insulating film material with a copper foil. According to the fourth embodiment, since the manufacturing limit of the rolled copper foil is 18 μm, and the wiring pitch is limited to about 80 μm, it is impossible to form fine wiring smaller than this. There is an effect that no evaporation equipment is required.

(Fifth Embodiment) In the fifth embodiment,
1 corresponds to the first embodiment of FIG. 3, and the lead 8 of the flexible wiring board 5 is formed by depositing a copper film to a thickness of 50 angstroms and then plating the entire thickness by electrolytic copper plating. It was formed based on a copper layer having a thickness of 3 μm. According to the fifth embodiment, since the electroplating is wet electroplating, a copper thin film of 99.9999% by weight cannot be obtained as a whole. A plating layer is formed, and fine wiring with a pitch of about 60 μm can be formed.

(Sixth Embodiment) In the sixth embodiment,
Instead of the rolled copper foil of the fourth embodiment, an electrolytic copper foil having a purity of 99.99% by weight and a thickness of 12 μm was used. Although the purity is lower than that of the OFC copper foil, the thickness of the foil can be reduced, and fine wiring processing with a pitch of about 80 μm is possible as in the fourth embodiment.

(Seventh Embodiment) This seventh embodiment corresponds to the second embodiment shown in FIG. 4, and the semiconductor chip 4 is the same as that of the first embodiment. Used, and the insulating film 7 of the flexible wiring board 5
The insulating film 7 of the same material as that of the example was used. As the ball 54, a solder ball (diameter 0.3 mm) having a eutectic composition of 37Pb-63Sn was used.

FIG. 5 shows a manufacturing method according to the seventh embodiment.
First, as shown in FIG. 5A, a high-purity copper foil 50 is deposited on the upper surface of the insulating film 7 having a thickness of 50 μm. Next, as shown in FIG. 5B, a via hole 51 having a diameter of 0.05 mm is formed on the lower surface of the insulating film 7 by a carbon dioxide laser. Next, as shown in FIG. 5C, a photosensitive epoxy resin 52 is applied. Next, as shown in FIG. 5D, the via hole 51 is exposed to expose the back surface of the copper foil 50, and the back surface is subjected to electroless copper plating 53. If the electroless copper plating 53 is applied directly on the insulating film 7 made of polyimide resin, the adhesion is inferior. Therefore, the epoxy resin 52 having excellent adhesion is selected. Thereafter, as shown in FIG. 5E, wiring patterns 50A and 53A are formed on the front and back surfaces. Next, as shown in FIG. 5F, 37Pb-6 is applied to the ball pad portion of the wiring pattern 53A formed on the back surface.
Solder ball 54 having a diameter of 0.3 mm having a eutectic composition of 3Sn
Was used to form a ball terminal.

In the seventh embodiment, all the input / output terminal electrodes of 304 pins are arranged in a lattice pattern inside the chip 4 of 13 mm square. The pitch of the ball terminals is 0.65.
mm, and the number of balls 54 is 324 in an 18 × 18 grid arrangement. Therefore, it has 24 dummy balls 54 at the center. The portion of the copper foil 50 on the via hole 51 is a circular via pad and has a diameter of 0.2 mm.
Therefore, the space between the via pads (space) was set to 0.45 mm. In the meantime, it is necessary to pass one line for the second ball from the outermost circumference, and for the third ball, two lines
In the fourth, three lines must be passed. The sixth line in front of the innermost side (no wiring is necessary because the center 24 are dummy) passes five lines. In this part, five lines are densely arranged between 0.45 mm pads. The pitch becomes a fine pitch of 0.45 / 5.5 = 81.0 μm. The connection of the chip 4 was performed under the same setting of the gold and tin plating thickness and the bonding conditions as in the first embodiment.

According to the seventh embodiment, the following effects can be obtained. Usually, the thermal expansion coefficient of glass epoxy resin is 30.
PPM / ° C and that of silicon chips is 3PP
M / ° C. For this reason, stress is generated between the chip 4 and the flexible wiring board 5 by the temperature cycle test.
Conventionally, a method of filling the space between the chip 4 and the flexible wiring board 5 with a resin has been adopted in order to prevent the joint from being broken by the stress. In this method, the bumps 4a of the input / output terminal electrodes and the inner leads 8a can be prevented from being broken, but stress is concentrated on the solder balls 54 and the solder balls 54
There was a problem of destruction in about 0 cycles. In this structure, since the flexible wiring board 5 is very flexible, when mounted on a motherboard, it absorbs thermal stress caused by a difference in thermal expansion coefficient between the chip 4 and the motherboard, and has high reliability against temperature cycles. Become.

The semiconductor device 1 of the seventh embodiment is
It was mounted on a rigid wiring board (motherboard) made of a glass epoxy resin having a thickness of mm, and a temperature cycle test was performed. A pad was formed on the rigid wiring board at a position where the solder ball 54 was connected, and the solder ball 54 was connected to the pad by heating and melting. -55 ° C x 150
As a result of a temperature cycle test of 2000 cycles at ℃, no damage such as breakage of the joint 9 was observed. Further, since the heat-resistant temperature of the joint 9 was 300 ° C., heat resistance enough to withstand 1500 hours in a high-temperature storage test at 150 ° C. in the air was obtained.

(Eighth Embodiment) This eighth embodiment corresponds to the first embodiment shown in FIG. 3 from FIG.
50m with 0.5mm thickness as flexible wiring board 5
A rigid wiring substrate made of m-square glass epoxy resin was used, and the semiconductor chip 4 was directly mounted on the rigid wiring substrate by gold-tin bonding as in the first embodiment. That is, as in the first embodiment, a lead pattern was formed on the uppermost layer of the rigid wiring board, and electrotin plating was applied to a thickness of 1.0 μm. After performing the electroless copper plating on the entire surface of the lead,
It was formed by photochemical etching, and electrotin plating was applied to a thickness of 1.0 μm in the same manner as in the first embodiment. The bonding of the semiconductor chip 4 to the input / output terminal electrodes was performed under the same conditions as in the first embodiment.

As a result, the rigid wiring board made of the glass epoxy resin has a Tg of 170 ° C. and has a lower heat resistance than the polyimide resin, but the peeling of the wiring pattern by the heat transfer due to the contact of the joining tool at 250 ° C. No damage such as carbonization of the glass epoxy resin itself was observed. However, the thermal expansion coefficient of the semiconductor chip 4 is 3PP.
M / ° C., and that of a rigid wiring board made of glass epoxy resin is 15 PPM / ° C., so that the structure is such that stress is directly transmitted to the gold-tin bonding interface 9b.
In a temperature cycle test of 5 ° C. × 150 ° C., 10% of the connection portions were broken in 500 hours.

FIG. 6 shows a semiconductor device according to a third embodiment of the present invention. The same parts as those in FIG. 4 are denoted by the same reference numerals, and a duplicate description will be omitted. (Ninth Embodiment) This ninth embodiment corresponds to the third embodiment shown in FIG. 6. In the ninth embodiment, the flexible wiring board 5 is provided with a single-sided film made of an insulating film 7 in the seventh embodiment. Using a wiring board, a via hole 51 is formed in this insulating film 7 and its blind via (this is called because one direction is blocked instead of a through hole).
In this structure, the balls 54 are formed directly on the back surface of the single-sided copper foil of the lead 8. This structure does not require wiring on the back,
It is important that the solder ball of 40 Pb wt% -Sn is pressed into the blind via to form it. This structure is possible by selecting an appropriate diameter of the via hole 51 and the diameter of the ball 54 and using a ball mounting machine having a mechanism for pushing the ball 54. The diameter of the via hole 51 is 0.1
5 mm, or the diameter of the solder ball 54 was 0.3 mm as in the seventh embodiment. Since the thickness of the flexible wiring board 5 is as thin as 50 μm, a ball 54 of 0.3 m is required.
However, it can contact the copper foil back surface of the film hole and can be connected by solder. In the seventh and eighth embodiments, no reinforcing resin was injected between the semiconductor chip 4 and the wiring board.
This is because the flexible wiring board 5 is flexible, so that the stress between the mother board and the semiconductor chip 4 is absorbed by the flexible wiring board 5 and the stress is not transmitted to the gold-tin bonding surface.
As a result, similar to the seventh embodiment, a result satisfying the temperature cycle test was obtained. In the ninth embodiment, a CSP can be manufactured at low cost because a double-sided wiring board is not used.

(Tenth Embodiment) In the tenth embodiment, a wiring board made of glass epoxy resin having a thickness of 0.2 μm is used for the flexible wiring board 5 in the seventh embodiment. In this structure, the glass epoxy resin has the same coefficient of thermal expansion because it is the same material as the motherboard.
From this, the structure is such that substantially no stress is applied to the bonding interface, and the temperature cycle test was cleared as in the seventh embodiment. Further, by the bonding of gold and tin of the first embodiment, it was possible to sufficiently secure the reliability to withstand high-temperature storage at 150 ° C. × 1500 hours in the air.

(Eleventh Embodiment) In the eleventh embodiment, an alumina ceramic wiring board having a thickness of 1.0 mm was used for the flexible wiring board 5 in the seventh embodiment. The thermal expansion coefficient of alumina ceramic is 4.5 PPM /
° C, which is close to the semiconductor chip 4. For this reason, the thermal stress at the bonding interface with the semiconductor chip 4 was small, but the thermal stress with the glass epoxy resin motherboard was large. For this reason, in the temperature cycle test, a connection failure of 20% occurred between the solder ball and the motherboard in 500 cycles.

(Twelfth Embodiment) In the twelfth embodiment, a wiring board made of glass aramid resin having a thickness of 1.0 mm is used for the flexible wiring board 5 in the seventh embodiment. Aramid resin has Tg compared to epoxy resin.
Is as high as 190 ° C, heat resistance is high, and thermal expansion coefficient is 10P
PM / ° C and slightly smaller than glass epoxy. For this reason, since the semiconductor chip 4 has a thermal expansion coefficient just intermediate between that of the semiconductor chip 4 and the glass epoxy, the same reliability as that of the seventh embodiment was obtained.

(Thirteenth Embodiment) The thirteenth embodiment is different from the first embodiment in that the wiring pattern is 1.0 μm thick.
Is an alloy plating containing 5% by weight of lead in tin. This is to prevent generation of whiskers due to the internal stress of tin electroplating. Tin plating is 200
By heating at a temperature of several degrees Celsius for several seconds, the internal stress is eliminated and the generation of whiskers is eliminated. However, whiskers happened to occur during storage before joining,
When left at room temperature, it occurred in about 3 weeks. For this reason, when measures before the joining operation are also important, the addition of 1 to 5% by weight of lead was effective.

Note that the present invention is not limited to the above-described embodiment and examples, and various embodiments and examples are possible. For example, the input / output terminal electrodes of the semiconductor chip 4 may be plated with tin, and the inner leads 8a may be plated with gold. Further, the bump 4a may be provided with gold plating on chromium plating. The coating layers formed on the input / output terminal electrodes of the semiconductor chip 4 and the inner leads 8a may be formed by electroplating, electroless plating, vapor deposition, or sputtering. The input / output terminal electrode provided with the gold or tin coating layer and the inner lead 8a provided with the tin or gold coating layer may be connected by a laser beam, an ultrasonic bonding tool, or the like. Further, the gold or tin applied to the input / output terminal electrode may have a bump or layered form, and the tin or gold applied to the inner lead 8a may have a layered or bumped form. Further, the input / output terminal electrodes or the bumps of the inner leads 8a are formed by plating with gold or tin or by forming a projection using a metal other than gold or a heat-resistant organic material, and forming a projection on the projection. Alternatively, it may be formed by applying a tin coating layer. The bumps of the inner leads 8a are formed by etching copper wiring, electroplating copper, chromium, nickel, or the like.
Alternatively, it may be formed by electroless plating. Also,
The bonding interface 9b is composed of 10 to 40% by weight of gold and 60 to 9% of tin.
In addition to 0%, it may be configured to contain 1.0% by weight or less of lead as a trace additive element, and 10 to 40% by weight of gold and 6% of tin.
In addition to 0 to 90%, a configuration may be employed in which a diffusion-dissolved base metal element from the joint metal base material is included. Further, the joint 9 may be sealed with a resin. The wiring board is made of a copper wiring glass epoxy substrate, a copper wiring glass polyimide substrate, a copper wiring BT resin, a copper wiring fluororesin substrate, a copper wiring aramid substrate, a copper wiring ceramic substrate, a copper wiring or a titanium oxide (TIO) wiring glass. A substrate, a copper wiring polyimide film, or a copper wiring glass epoxy film may be used. The wiring board is formed by laminating an electrolytic copper foil, a rolled copper foil or the like on a base plate, forming a wiring by a photochemical etching method, and then plating a copper wiring plated with gold, tin or a metal containing a trace amount of lead in these. May be provided. Further, the wiring board may be formed by laminating an electrolytic copper foil, a rolled copper foil or the like on a base plate, forming a wiring by a photochemical etching method, applying a base plating of nickel or the like, and plating gold thereon. .

[0062]

As described above, according to the present invention, since the input / output terminal electrodes of the semiconductor chip and the inner leads are connected by the diffusion reaction of gold and tin, the strength of the connection is increased. . Further, since it is not necessary to provide a device hole in the wiring board on which the semiconductor chip is mounted, the strength of the wiring board such as tension and bending is increased, and the wiring board is excellent in flexibility. For this reason, environmental resistance that can be applied to cold regions and the like and reliability that does not cause a connection failure in a manufacturing process are obtained, and mounting of a multichip is possible. Further, since a mold for providing a device hole is not required, cost can be reduced.

[Brief description of the drawings]

1A is a plan view showing a semiconductor device according to a first embodiment of the present invention, and FIG. 1B is a cross-sectional view thereof.

FIG. 2 is a cross-sectional view illustrating a connection structure between a bump and an inner lead of the semiconductor chip according to the first embodiment.
(a) and (b) show two types of bumps.

FIG. 3 is a cross-sectional view showing a state of a bonding interface between a bump and an inner lead of the semiconductor chip according to the first embodiment.

FIG. 4 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a process chart showing a method for manufacturing a semiconductor device according to a seventh embodiment of the present invention.

FIG. 6 is a sectional view showing a semiconductor device according to a third embodiment of the present invention.

7A is a plan view showing a semiconductor device having a TCP structure as a first conventional example, and FIG. 7B is a sectional view thereof.

8A is a plan view showing a semiconductor device having a TAB structure as a second conventional example, and FIG. 8B is a cross-sectional view thereof.

[Explanation of symbols]

Reference Signs List 1 semiconductor device 2 mother board 2a wiring pattern 3 TCP 4 semiconductor chip 4a bump _4a1 gold plating _4a2 nickel plating 5 relay board 5 TAB tape, flexible wiring board 6 sealing resin 7 insulating film 7a device hole 7b outer lead hole 7c feed Hole 8 Wiring layer 8a Inner lead _8a1 Copper wiring _8a2 Tin plating 8b Outer lead 9 Joint 9a Fillet 9b Joining interface 50 Copper foil 50A, 53A Wiring pattern 51 Via hole 52 Epoxy resin 53 Electroless copper plating 54 Ball

Claims (24)

[Claims] 1. A semiconductor device comprising an input / output terminal electrode of a semiconductor chip and an inner lead formed on a wiring board such as a TAB tape, a rigid wiring board or a flexible wiring board having no device hole. The input / output terminal electrode is provided with a coating layer of gold or tin, the inner lead is provided with a coating layer of tin or gold, and a connection portion between the input / output terminal electrode and the inner lead is formed of a gold or tin coating. A semiconductor device formed by a diffusion reaction with the tin. 2. The semiconductor device according to claim 1, wherein said connection portion has a structure in which at least a bonding interface includes a base metal having a composition of 10 to 40% by weight of gold and 60 to 90% by weight of tin. 3. The gold or tin coating layer applied to the input / output terminal electrode is formed directly on the input / output terminal electrode or by electroplating or electroless plating of nickel, chromium, copper or the like. Electroplating on the bump,
2. The semiconductor device according to claim 1, wherein the semiconductor device is formed by electroless plating, vapor deposition, or sputtering. 4. The semiconductor device according to claim 1, wherein said tin or gold coating layer applied to said inner lead is formed by electroplating, electroless plating, vapor deposition or spargling. 5. The connection input / output terminal electrode provided with the gold or tin coating layer and the inner lead provided with the tin or gold coating layer are provided with a heating tool for connection and a laser beam. 2. The semiconductor device according to claim 1, wherein said semiconductor device is connected by an ultrasonic bonding tool. 6. The gold or tin applied to the input / output terminal electrode has a bump or layered form, and the tin or gold applied to the inner lead has a layered or bumped form. Claim 1 having a configuration having
13. The semiconductor device according to claim 1. 7. The input / output terminal electrode or the bump of the inner lead is formed by plating with gold or tin, or a projection is formed of a metal other than gold or a heat-resistant organic material. 7. The semiconductor device according to claim 6, wherein said semiconductor device is formed by applying said gold or tin coating layer thereon. 8. The semiconductor device according to claim 6, wherein said bumps on said inner lead side are formed by etching copper wiring, electroplating copper, chromium, nickel or the like, or electroless plating. 9. The bonding interface may include 10 to 40% by weight of gold, 60 to 90% by weight of tin, and 1.0% by weight of lead as an additional element.
3. The semiconductor device according to claim 2, wherein said semiconductor device has a composition containing not more than% by weight. 10. The bonding interface, wherein gold is 10 to 40% by weight,
The semiconductor device according to claim 2, further comprising a metal element diffused and dissolved from the joint metal base material in addition to the tin weight of 60 to 90%. 11. The semiconductor device according to claim 1, wherein said connecting portion is sealed with a resin. 12. The semiconductor device according to claim 1, wherein said wiring board has a structure in which said inner leads are directly formed without using an adhesive for a base material. 13. The wiring substrate may be a copper wiring glass epoxy substrate, a copper wiring glass polyimide substrate, a copper wiring BT resin, a copper wiring fluororesin substrate, a copper wiring aramid substrate, a copper wiring ceramic substrate, a copper wiring or a titanium oxide (TIO). 2. The semiconductor device according to claim 1, comprising a glass substrate for wiring, a copper wiring polyimide film, or a copper wiring glass epoxy film. 14. The wiring board is formed by laminating an electrolytic copper foil, a rolled copper foil or the like on a base plate, forming wiring by a photochemical etching method, and then plating gold, tin or a metal containing a trace amount of lead in these. 2. The semiconductor device according to claim 1, wherein said semiconductor device has a copper wiring. 15. The wiring board is formed by laminating an electrolytic copper foil, a rolled copper foil or the like on a base plate, forming a wiring by a photochemical etching method, applying a base plating of nickel or the like, and plating gold thereon. The semiconductor device according to claim 1 having a configuration. 16. A semiconductor device in which input / output terminal electrodes of a semiconductor chip are connected to leads formed on a wiring board serving as a motherboard, wherein the input / output terminal electrodes are provided with a coating layer of gold or tin, A semiconductor device, wherein the lead is provided with a coating layer of tin or gold, and a connection portion between the input / output terminal electrode and the lead is formed by a diffusion reaction between the gold and the tin. 17. The interposer according to claim 1, wherein the input / output terminal electrode of the semiconductor chip is connected to an inner lead formed on a wiring board serving as an interposer such as a TAB tape, a rigid wiring board, or a flexible wiring board without device holes. In a semiconductor device in which leads of a wiring board to be formed are connected to leads formed on a wiring board to be a motherboard, the input / output terminal electrodes are coated with gold or tin, and the inner leads are formed of tin or tin. A coating layer of gold is applied, a connection portion between the input / output terminal electrode and the lead is formed by a diffusion reaction between the gold and the tin, and a wiring board serving as the interposer and the mother boat is connected by a ball grid array. A semiconductor device having a configuration as described above. 18. A semiconductor device in which an input / output terminal electrode of a semiconductor chip is connected to an inner lead formed on a TAB tape or a flexible wiring board having no device hole, wherein the input / output terminal electrode is made of gold. Alternatively, a tin coating layer is applied, the inner lead is provided with a tin or gold coating layer, and a connecting portion between the input / output terminal electrode and the lead is formed by a diffusion reaction between the gold and the tin. A semiconductor device, wherein the TAB tape or the flexible wiring substrate having no device hole is connected to a liquid crystal substrate, and the semiconductor chip is configured as a liquid crystal driving circuit. 19. A semiconductor device in which an input / output terminal electrode of a semiconductor chip is connected to a lead formed on a glass wiring substrate having no device hole, wherein the input / output terminal electrode is coated with gold or tin. A layer is provided, the lead is provided with a coating layer of tin or gold, and a connection portion between the input / output terminal electrode and the lead is formed by a diffusion reaction between the gold and the tin. Semiconductor device. 20. Manufacture of a semiconductor device in which input / output terminal electrodes of a semiconductor chip are connected to inner leads formed on a wiring board such as a TAB tape, a rigid wiring board or a flexible wiring board having no device hole. In the method, the input / output terminal electrode is provided with a gold or tin coating layer, the inner lead is provided with a tin or gold coating layer, and the gold or tin coating layer is provided with the input / output terminal electrode. A method of manufacturing a semiconductor device, comprising: connecting the inner lead provided with the tin or gold coating layer by a diffusion reaction between the gold and the tin. 21. A connection between the input / output terminal electrode provided with the gold or tin coating layer and the inner lead provided with the tin or gold coating layer is at least a connection portion of the inner lead. 21. The method of manufacturing a semiconductor device according to claim 20, wherein the bonding interface includes a base metal having a composition of 10 to 40% by weight of gold and 60 to 90% by weight of tin. 22. The gold or tin coating layer applied to the input / output terminal electrode is directly applied to the input / output terminal electrode.
21. The method for manufacturing a semiconductor device according to claim 20, wherein the bump is formed by electroplating, electroless plating, electroless plating, vapor deposition, or sputtering of nickel, chromium, copper, or the like. 23. The tin or gold coating layer applied to the inner lead is formed by electroplating, electroless plating,
21. The method for manufacturing a semiconductor device according to claim 20, wherein the method is formed by vapor deposition or spargling. 24. The connection between the input / output terminal electrode provided with the gold or tin coating layer and the inner lead provided with the tin or gold coating layer is performed by using a heating tool for connection. 21. The method for manufacturing a semiconductor device according to claim 20, wherein the method is performed by using a laser beam and an ultrasonic bonding tool.