JPH10254590A - Integrated circuit and information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To actualize a highly reliable zero-volt suspending function by holding a logical state by a logical means even if an input/output power source means and a logical power source means are separated and no electric power is supplied to the input/output power source means. SOLUTION: When the system enters an idle state, it tries to enter a zero-volt suspended state so as to reduce the power consumption. For the purpose, a CPU 402 reads condition data out of itself and writes the data in a FLASH RAM 404. Then data in a necessary address space of a DRAM 403 are read out as well and written to the FLAH RAM 402. Then a suspending signal is enabled to protect the internal logic circuit state of a system controller 401 so that it does not change. After the logic circuit begins to be protected, the main power source 405 is turned off and placed in a floating state. In the suspended state, only an RTC built in the system controller 401 continues to clock the time and other logic circuits are placed in a stop state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a zero volt suspend (main power off,
The present invention relates to an improvement in a function of a power save mode capable of restarting the system except for a reset input.

[0002]

2. Description of the Related Art Conventionally, in an information processing apparatus having a suspend (power save mode in which the system can be restarted except for a reset input), a CPU 502 (central processing unit) and a DRAM 5 constituting the system as shown in FIG.
03 (main storage device), FLASH RAM 504 (secondary storage device), and system controller 501 (system control device) are operated by main power supply 505 (main power supply device). When the main power supply is disconnected or the voltage drops (power failure), the battery is switched to the backup battery 506 (auxiliary power supply) to back up the clock RTC (real-time clock) built in the system controller. Since the system is shut down when the main power supply is disconnected or the power fails, it is not necessary to restart the system.

However, in a battery-driven information processing apparatus, power consumption must be reduced as much as possible in order to extend the operation time. Therefore, when the system is idle (CPU
It is necessary to reduce the power consumption by turning off the main power supply of the system. In that case, the power applied to the LSI such as the CPU and the DRAM is lost (becomes zero volts), so that the data built in the CPU and the data of the DRAM are erased as it is. That is, the system cannot be restarted except by the reset input.

Therefore, in the conventional information processing apparatus, the CPU reads condition data, DRAM data, system controller configuration data, I / O data, and the like incorporated in the CPU before the zero volt suspend, and even if the power supply is cut off. The data has been saved to a non-volatile memory such as FLASH RAM (or a disk device such as HDD) from which data is not erased.

[0005]

However, in the above-mentioned conventional method, some of the circuits such as an interrupt circuit, a clock timer, and a DMA controller built in the system controller are not writable (reading is possible but writing is not possible). (Cannot) Due to the presence of I / O data, the data saved in the FLASH RAM when resuming from zero volt suspend (returning from suspend) could not be written to the system controller again. Therefore, the internal state of the system controller does not return to the state immediately before the suspension of the zero volt, and the system sometimes does not resume from the suspension of the zero volt.

An object of the present invention is to provide an integrated circuit capable of realizing a highly reliable zero volt suspend function and a low power consumption information processing apparatus using the integrated circuit.

[0007]

SUMMARY OF THE INVENTION The above object comprises input means for inputting a signal, output means for outputting a signal, logic means generated by the input means, and logic means for generating the output means. In the integrated circuit, input / output power supply means for driving the input means and output means and logic power supply means for driving the two logic means are separated from each other, and the logic means is provided even when power is not supplied to the input / output power supply means. Is achieved by maintaining a logic state.

The above object is also achieved by a power supply detecting means for detecting the presence or absence of a power supply of the input / output power supply means, an input permitting means for permitting an input from the input means based on an output result of the power supply detecting means, This is achieved by having output permitting means for permitting output to the logic means according to the output result of (1).

The object is also provided with the integrated circuit, a main storage device for storing information, at least a main power supply device for driving the integrated circuit and the main storage device, and an auxiliary power supply device for assisting the main power supply device. An information processing device, comprising a selection power supply device that switches to the auxiliary power supply device when the power supply of the main power supply device is lost, and an input / output power supply unit of the integrated circuit is connected to the main power supply device;
This is achieved by connecting the logic power supply means of the integrated circuit to the selected power supply device.

[0010]

According to the above-mentioned means, the logic circuit system power supply of the system controller which is the core of the apparatus is not turned off at the time of the zero volt suspend, so that the state of the logic circuit can be completely maintained and the resume from the zero volt suspend can be stably performed. it can.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be specifically described below with reference to the drawings.

FIG. 1 is a configuration diagram of an integrated circuit according to the present invention.
101 is an input / output buffer circuit, 102 is a logic circuit, 10
Reference numeral 3 denotes a power supply VCC for the input / output buffer circuit, and reference numeral 104 denotes a VLOGIC power supply for the logic circuit.

The integrated circuit of the present invention comprises an input buffer circuit section,
The power supply system (VCC) of the output buffer circuit section and the power supply system (VLOGIC) of the logic circuit section are completely separated from each other.

The transistors having different power supply systems can be easily separated from each other by forming them in different base wells.

FIG. 2 is a circuit diagram of the input circuit of the present invention.
201 is an input pad, 202 is an input buffer, 203 is a NOR gate, 204 is an inverter, 205 is VCC,
206 is a VLOGIC, 207 is a ground, and 208 is a suspend permission signal. In normal operation, VCC and VLO
Since the GIC has the same voltage, it operates without any problem without a level shift circuit. Further, since the suspend permission signal 208 is disabled (low level), the NOR gate 203 inverts the logic of the input signal and outputs the inverted signal to the inverter 204. When the suspend permission signal 208 is enabled (high level), the NOR gate 203 always outputs a low level. Therefore, even if the output signal of the input buffer 202 is in a floating (high impedance) state, the NOR gate 203 has a through current (short current). Does not flow.

FIG. 3 is a circuit diagram of an output circuit according to the present invention.
301 is an output pad, 302 is an output buffer, 303 is a clocked inverter, 304 is an inverter, 305 is VCC, 306 is VLOGIC, 307 is ground, 3
08 is a suspend permission signal. In a normal operation, VCC and VLOGIC are the same voltage as in the input circuit, so that a level shift circuit is not required. Since the suspend permission signal is disabled (low level), the clocked inverter 303 performs the same function as the inverter, and
The logic circuit inverts the logic of the input signal from 04 and outputs the inverted signal. When the suspend signal 308 is enabled (high level), the output of the clocked inverter 303 is set to high impedance.

As described above, when the suspend permission signal is enabled (high level), a through current does not flow through the NOR gate 203 even if the power supply of VCC becomes zero volt or floating. Since the output of the clocked inverter 303 is high impedance,
No current flows into or out of the power supply system.

As described above, by separating the input / output circuit power supply from the internal logic circuit power supply and controlling the input / output signals using the suspend permission signal, the logic state of the internal logic circuit is not increased without increasing the power consumption during suspend. Can be easily held. The NOR gate and the clocked inverter described in this embodiment are merely examples, and can be realized by other methods. As the suspend permission signal, other signals having the same function can be applied.

FIG. 4 is a system configuration diagram of the information processing apparatus according to the embodiment of the present invention. 401 is a system controller,
402, a CPU; 403, a DRAM; 404, data storage and data saving (backup) during suspending
RAM, 405 is a main power supply for operating the system, 406 is a backup battery for backing up the system, 407 and 408 are diodes constituting a backup power supply circuit, 409 is a VCC which is a main power supply, and 410 is a system controller. VLOGIC which is a logic circuit power supply, 411 is a backup power supply VBAK, 412 is a ground, 413 is a CPU bus connecting a CPU and a system controller, 414 is a memory bus 1 connecting a DRAM and a system controller, and 415 are FLASH RAM and a system The memory buses 2 and 416 connecting the controllers are suspend signals for requesting a suspend, and 417 is a resume signal for requesting a resume.

During normal operation of the system, the main power supply 405
Of the CPU 402, the DRAM 403, and the FLA
SH RAM 404 and system controller 401
Is applied to the input / output power supply. Further, since the voltage VCC of the main power supply is higher than the voltage VBAK of the backup battery, the logic circuit power supply VLOGIC of the system controller is set to V by the diodes 407 and 408.
Almost the same voltage as CC is input. Therefore, the system controllers are the CPU bus, the memory bus 1, the memory bus 2
Data can be exchanged via the.

When the system is idle, the system attempts to go to zero volt suspend to reduce power consumption. Therefore, the CPU reads the condition data contained in the CPU and writes the data into the FLASH RAM. Next, the data in the necessary address space of the DRAM is similarly read and written to the FLASH RAM.

Thereafter, the suspend signal is enabled to protect the state of the internal logic circuit of the system controller from being changed. After the protection of the logic circuit is started, the main power supply is turned off and the power supply is floated (zero volt). In the suspend state, only the RTC built in the system controller continues the clock operation, and the other logic circuits are stopped. Therefore, the system can operate sufficiently with the backup battery.

When the system is restarted, the resume signal is enabled (permitted), and first, the main power supply is turned on. Wait until the voltage of the main power supply stabilizes, and disable the suspend signal. As a result, the signals of the input / output circuit of the integrated circuit and the logic circuit are connected, and the CPU becomes operable.
After that, the data saved in FLASH RAM is
Return to the CPU and DRAM, and the system returns to the original state.

[0024]

As described above, by using the integrated circuit and the information processing apparatus of the present invention, a highly reliable zero volt suspend function can be realized in a computer or a handy terminal, and a battery-backup type of low power consumption can be realized. Powerful information processing devices can be made.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an integrated circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of an input circuit according to an embodiment of the present invention.

FIG. 3 is a circuit diagram of an output circuit according to an embodiment of the present invention.

FIG. 4 is a system configuration diagram of an information processing apparatus according to an embodiment of the present invention.

FIG. 5 is a system configuration diagram of a conventional information processing apparatus.

[Explanation of symbols]

 101 ... I / O buffer circuit 102 ... Logic circuit 103, 205, 305, 409, 509 ... VCC 104, 206, 306, 410 ... VLOGIC 411, 511 ... VBAK 510 ... RTC power supply 207, 307, 412, 512 ... ground 201 input pad 202 input buffer 203 NOR gates 204 and 304 inverters 208 and 308 suspend enable signal 416 suspend request signal 417 resume request signal 301 output pad 302 output buffer 303 clocked inverter 401 and 501 ··· System controllers 402 and 502 ··· CPUs 403 and 503 · · · DRAMs 404 and 504 · · · FLASH RAMs 405 and 505 ... Main power supplies 406 and 506 ... Backup batteries 407, 408 and 507 508 ... diodes 413,513 ... CPU bus 414, 514 ... memory bus 1 415,515 ... memory bus 2

Claims (3)

[Claims] 1. An integrated circuit comprising: input means for inputting a signal; output means for outputting a signal; logic means generated by said input means; and logic means for generating said output means. The input / output power supply means for driving the output means and the logic power supply means for driving the two logic means are separated from each other, and the logic means holds the logic state even when power is not supplied to the input / output power supply means. Integrated circuit characterized. 2. An integrated circuit according to claim 1, wherein said input / output power supply means detects the presence or absence of a power supply.
An integrated circuit, comprising: an input permitting means for permitting an input from the input means based on an output result of the power detecting means; and an output permitting means for permitting output to the logic means based on an output result of the power detecting means. . 3. An integrated circuit according to claim 1 or 2, a main storage device for storing information, a main power supply device for driving at least the integrated circuit and the main storage device, and an auxiliary for the main power supply device. An information processing apparatus having an auxiliary power supply device, comprising: a selection power supply device that switches to the auxiliary power supply device when the power supply of the main power supply device is lost; and an input / output power supply unit of the integrated circuit is connected to the main power supply device. And a logic power supply means of the integrated circuit is connected to the selected power supply device.