JPH10242079A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device having a silicide layer capable of reducing junction leakage. SOLUTION: A source/drain region 6 as a metal silicide forming region on a silicon substrate 1, and the surface of a polycrystalline silicon gate 4 are made amorphous and an amorphous layer 7 is formed, by implanting ions deeper than a semiconductor substrate to be consumed by metal silicide which is finally formed. A metal Co film 8 is deposited on the metal silicide forming region, and a cobalt silicide layer is formed by heat treatment. By this constitution, all silicon which is consumed by silicide reaction is made amorphous, and generation of unevenness in a silicide layer can be restrained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device having a high melting point metal silicide layer, and more particularly to a method for forming a high melting point metal silicide in a self-aligned manner.

[0002]

2. Description of the Related Art In recent years, it has become necessary to reduce the resistance of a source / drain region and a gate electrode in order to speed up the operation of a MOS type semiconductor device constituting a super LSI. One of the techniques for achieving this is to deposit a refractory metal film over the entire surface of a semiconductor device and then perform a heat treatment to react the refractory metal with silicon, thereby forming a refractory metal silicide into a source / drain region and a gate. There is a salicide technique of forming on an electrode. That is, this technology is
Refractory metal silicide is formed only on the drain region and the gate electrode in a self-aligned manner (for example, T.Ts).
Ukamoto et al. Ext. Abst. on SSDM,
pp 45, 1984).

However, in this method, there is unevenness in the formed silicide layer, and the position of the PN junction approaches due to the unevenness, so that the junction leakage current increases and becomes uneven compared to the case without the silicide layer. However, it has been pointed out that it is large. Therefore, in recent years, it has been reported that junction leakage current can be reduced by forming cobalt silicide after amorphizing a silicon substrate by Ge ion implantation before depositing cobalt (Fushida et al. 199).
6th Autumn Meeting of the Japan Society of Applied Physics, Performance No. 7p-N-15, Proceedings p. 589).

[0004] The following describes the conventional salicide technique described above with reference to the drawings.

FIGS. 4A to 4G are sectional views showing a conventional salicide process. First, as shown in FIG. 4A, a field oxide film 2, a gate oxide film 3, and a polycrystalline silicon gate 4 having a side wall 5 made of an insulating material on a side surface are sequentially formed on a silicon substrate 1.
Next, as shown in FIG. 4B, As ⁺ is applied to a region where an N ⁻ channel transistor is formed, and BF ₂ ⁺ is applied to a region where a P ⁻ channel transistor is formed.
Ion is implanted into the portion to be the drain region, and then 100
The source / drain region 6 is formed by performing a carrier activation heat treatment at 0 ° C. for 10 seconds. At this time, the source / drain region 6 is amorphous immediately after ion implantation, but is crystallized by performing a carrier activation heat treatment.

Next, as shown in FIG. 4C, Ge ions are implanted into the entire surface of the semiconductor device (source / source).
An amorphous layer 7 is formed on the surface of the drain region and the gate). Thereafter, as shown in FIG. 4D, a Co film 8 and a TiN film 9 which are materials for forming a silicide layer are formed on the entire surface of the semiconductor device by a sputtering method. Deposit sequentially. The TiN film 9 has a role of preventing the Co film 8 from being oxidized during a heat treatment performed later.

Further, as shown in FIG. 4E, a first heat treatment is performed at 450 ° C. for 30 seconds by a lamp annealing method. In this step, silicon and Co react only on the polycrystalline silicon gate 4 and the source / drain region 6 to form a CoSi or Co ₂ Si crystal 10. At this time, the sidewall 5 and the field oxide film 2 are formed. An unreacted Co film 8 remains on the upper surface.

[0008] Then, as shown in FIG. 4 (f), H ₂ S
The TiN film 9 and the unreacted Co film 8 are removed using a mixed solution of O ₄ : H ₂ O ₂ . Finally, as shown in FIG. 4G, a second heat treatment is performed at 825 ° C. for 30 seconds by a lamp annealing method. By this heat treatment, CoSi or C
The o ₂ Si crystal is replaced with a lower-resistance CoSi ₂ crystal 11 (16 μm).
Ωcm) to form a low-resistance CoSi on the polycrystalline silicon gate 4 and the source / drain region 6.
_Two crystals 11 are formed.

Through the above steps, a sheet resistance of 10 Ω / sq. Source /
Low resistance of the drain region and the gate electrode is achieved.

[0010]

The problem with the above-mentioned cobalt salicide process is that the junction leakage current is large. It is considered that this is because cobalt silicide does not grow uniformly and the unevenness of the film becomes large, resulting in a portion where the distance between the PN junction and the silicide film becomes small.

On the other hand, the technique shown in FIG. 4 shows that an amorphous layer is formed by Ge implantation and the junction leakage current is reduced, but the junction leakage current still exists. .

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device having a silicide layer capable of further reducing junction leakage, compared to the prior art shown in FIG.

[0013]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises: first, a metal silicide formation region on a semiconductor substrate is formed by a metal silicide to be finally formed; The structure includes a step of amorphizing deeper than the consumed semiconductor substrate and a step of forming a metal silicide by heat treatment after depositing a metal in a metal silicide formation region.

With the above structure, the thickness of the amorphous layer is made larger than that of the semiconductor (silicon) substrate consumed by the finally formed metal silicide, so that the silicon consumed at the time of forming the metal silicide can be reduced. It is characterized in that it is all amorphous silicon. Amorphous silicon has latent heat with respect to crystalline silicon and easily reacts with metal. Therefore, by making all of the silicon consumed during silicide formation amorphous, the silicidation reaction is facilitated, the density of nucleation is increased, and a silicide layer having a small grain size and a small number of irregularities can be formed. For this reason,
A semiconductor device with less junction leakage current can be obtained.

In the method of manufacturing a semiconductor device according to the present invention, secondly, an amorphous layer thicker than the semiconductor substrate consumed by the finally formed metal silicide is formed in the metal silicide formation region on the semiconductor substrate. The structure includes a forming step and a step of forming a metal silicide by heat treatment after depositing a metal in the metal silicide formation region.

According to this structure, since an amorphous semiconductor film is formed in the region where the metal silicide is to be formed, the amount of silicon consumed in the semiconductor substrate can be further reduced. Obtainable.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention focuses on the depth of implantation at the time of forming an amorphous layer, that is, the relationship between the depth of the amorphous layer and the junction leakage current. So in the following,
A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. Note that in this embodiment, a description will be given by taking a source / drain region and a polycrystalline silicon gate as regions where silicide is formed.

(Embodiment 1) First, Embodiment 1 of the present invention
FIG. 1 shows a semiconductor device and a method of manufacturing the same in FIG.
This will be described with reference to the process sectional views shown in FIGS.

First, as shown in FIG.
Field oxide film 2, gate oxide film 3 on plate 1, on side
Polycrystalline silicon having sidewalls 5 made of an insulating material
Recon gates 4 are sequentially formed. Next, as shown in FIG.
As you can see, N^-In the area where the channel transistor is formed
Is As⁺And P^-In the area where the channel transistor is formed
Is BF_Two ⁺To become the source / drain regions
Ion implantation and heat treatment for carrier activation
Form source / drain regions 6. At this time,
The source / drain region 6 becomes amorphous immediately after ion implantation.
However, the carrier activation heat treatment
Crystallize. In the present embodiment, N ^-Channel area
To form As⁺At a dose of 3E15, 30
Inject at keV and activate by heat treatment at 850 ° C for 30 minutes
It is possible to obtain a depth of about 0.1 μm ⁺/ P junction is formed
Was.

Next, as shown in FIG. 1C, As.sup. ⁺ Ions are implanted into the entire surface of the semiconductor device at a dose of 3E14 and an energy of 60 keV. This step is a step of amorphizing the source / drain regions and the vicinity of the surface of the polycrystalline silicon gate which react when a silicide layer is formed later, and it is not always necessary to perform ion implantation using As ⁺ . Ge or the like may be used. By the amorphization step shown in FIG. 1C, an amorphous layer is formed in the semiconductor substrate deeper than the semiconductor substrate consumed by the finally formed metal silicide. However, it goes without saying that amorphization is performed at a depth shallower than the PN junction.

Here, the present inventors have described the literature (M. Miyata).
ke et al. , J. et al. Electrochem. S
oc. 135, 2872) at 2E15 dose
Since it is stated that the formation depth of the crystalline layer formed when i ⁺ is implanted is 50 nm at 20 keV and 95 nm at 40 keV, the depth to be amorphized is:
Average value of range of Si ⁺⁺ standard deviation of the range × 1.
I thought it matched 2. On the other hand, also in the present invention, As ⁺ is changed at a dose of 3E14 by changing the implantation energy.
As a result of examining the change in the thickness of the amorphous layer 7 formed upon implantation into the i-substrate, 24.5 nm and 40 ke at 20 keV were obtained.
The amorphous layer is formed to a thickness of 46 nm at V, and the depth of the amorphous layer formed by ion implantation is substantially equal to the average value of the range of the implanted ions + the standard deviation of the range. 1.2
Degree (the average value of the range of the particle is 1.
(A value obtained by adding 2 times). From this, it is estimated that the depth of the amorphous layer formed when As ⁺ is ion-implanted at a dose of 3E14 at an energy of 60 keV is about 56 nm.

Thereafter, as shown in FIG. 1D, a Co film 8 is formed to a thickness of 13 nm, a TiN film 9 is formed to a thickness of 20 nm, and
The layers are sequentially deposited by a sputtering method. Then, as shown in FIG. 1E, a first heat treatment is performed at 500 ° C. for 60 seconds by a lamp annealing method. Through this step, silicon and Co react only on the gate electrode 4 and the source / drain region 6 to form a CoSi or Co ₂ Si crystal 10.
At this time, unreacted Co may remain on the sidewalls 5 and the field oxide film 2 in some cases.

Thereafter, as shown in FIG. 1 (f), H ₂ S
Using a mixed solution of O ₄ : H ₂ O ₂ , unreacted C
The o film 8 is removed, and finally, as shown in FIG. 1G, a second heat treatment is performed at 750 ° C. for 60 seconds by a lamp annealing method. By this heat treatment, the CoSi or Co ₂ Si crystal is transformed into a lower-resistance CoSi ₂ crystal 11 (16 μΩcm).
Phase transition. As a result, a sheet resistance of 10 Ω / sq. The resistance reduction of the source / drain region and the gate electrode is achieved below. According to the cross-sectional SEM observation, the thickness of the CoSi ₂ formed this time was about 46 nm.

FIG. 3 shows a histogram of the junction leak characteristics in the wafer plane. In this experiment, n ⁺
/ P junction area is 0.522 mm ² in 25 places 2.
The reverse current when 5 V was applied was measured. The horizontal axis shows the junction leak current value, and the vertical axis shows how many of the above 25 locations correspond. In FIG. 3, (a) shows A
s without the amorphization treatment by s.
s is implanted with an energy of 20 KeV to perform an amorphization process, (c) is a case where As is implanted with an energy of 40 KeV and an amorphization process is performed, and (d) is a case where As is implanted with 60 KeV. The results are shown for the case of performing an amorphization process by implanting with energy.

As is apparent from the results shown in FIG.
When the implantation energy is 40 keV or more, the junction leakage distribution is extremely reduced, and the tendency is found to be stable. FIG. 3 (c)
It is considered that the reason why the junction leak distribution was extremely reduced as shown in FIG. 3D and (d) is that the amorphous layer was formed by the thickness of Si necessary for forming CoSi ₂ . As described above, when an amorphized layer is formed by the thickness of Si necessary for forming CoSi ₂ , this amorphous silicon has latent heat with respect to crystalline silicon and easily reacts with a metal. Many nuclei of the silicidation reaction are uniformly formed in the formation region, and as a result, a silicide layer having a small particle size and uniformity with less unevenness can be formed.

In the case where the amorphized layer is formed by ion implantation as in this embodiment, as described above, the depth of the amorphous layer formed by ion implantation is substantially Since the average value of the range of the ion + the standard deviation of the range x 1.2, the formation of the amorphous layer is determined by the average value of the range + the standard deviation of the range x 1.2. Alternatively, the ion implantation may be performed with an implantation energy that is larger than the thickness of the semiconductor consumed by the formation of the metal silicide layer.

Embodiment 2 Next, a method of manufacturing a semiconductor device according to Embodiment 2 of the present invention will be described with reference to FIGS.
This will be described with reference to the process sectional view shown in FIG.

First, FIGS. 2 (a) and 2 (b) are the same as those in the above-described first embodiment, and will not be described.

Next, as shown in FIG. 2C, in this embodiment, the polysilicon gate 4, the source / drain 6
Amorphous Si12 is formed only on top. As a method of forming the amorphized Si 12, crystalline Si is selectively grown on the polycrystalline silicon gate 4 and the source / drain 6, and then a layer selectively grown by implanting As ⁺ and a source if necessary. / Amorphize up to the inside of the drain. At this time, the thickness of the amorphized Si needs to be equal to or greater than the thickness of Si necessary for forming CoSi ₂ for the same reason as described in the first embodiment.

Next, FIGS. 1 (d) to 1 (g) are the same as those in the first embodiment, and will not be described. Also in the case of the present embodiment, the junction leak can be suppressed by forming the amorphized Si 12 to have a thickness greater than the thickness of Si necessary for forming CoSi ₂ .

In the present embodiment, an amorphous semiconductor film is formed in a region where a metal silicide is to be formed, so that silicon in a semiconductor substrate is consumed by the metal silicide formation in the case of the first embodiment. Can be even less. Therefore, the distance between the junction and the silicide can be further increased, so that a semiconductor device with less junction leakage current can be obtained.

Although the present invention has been described in conjunction with the embodiments, in the embodiments of the present invention, CoSi ₂ is used as the finally formed metal silicide.
Another silicide such as NiSi, TiSi ₂ , WSi ₂ or the like may be formed. Although Si was used as the substrate,
A substrate containing another element such as Ge or C therein may be used. Further, although the ion implantation method is used as a method of forming the amorphized layer, the amorphized layer may be formed by another method. For example, a method such as exposure to nitrogen plasma may be used.

[0033]

As described above, according to the present invention, all of the Si necessary for forming the silicide layer is made amorphous, whereby the silicidation reaction is facilitated, and a silicide layer having a small particle size, uniformity and small irregularities can be formed. As a result, a semiconductor device with less junction leakage current can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a sectional view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 3 is a diagram showing junction leakage current characteristics of the semiconductor device according to the embodiment of the present invention;

FIG. 4 is a cross-sectional view of a manufacturing process of a conventional semiconductor device.

[Explanation of symbols]

1 silicon substrate 2 field oxide film 3 gate oxide film 4 polycrystalline silicon gate 5 side wall 6 source / drain 7 amorphized layer 8 Co film 9 TiN film 10 Co ₂ Si or CoSi 11 CoSi ₂ 12 amorphization Si film

Claims (4)

[Claims] A step of amorphizing a metal silicide formation region on a semiconductor substrate deeper than a semiconductor substrate consumed by the metal silicide to be finally formed; and depositing a metal in the metal silicide formation region. Forming the metal silicide by heat treatment after the heat treatment. 2. A step of forming an amorphous layer in a metal silicide formation region on a semiconductor substrate which is thicker than a semiconductor substrate consumed by the metal silicide to be finally formed; After depositing
Forming a metal silicide by heat treatment. 3. An implantation energy such that a value obtained by adding 1.2 times the standard deviation of the range to the average value of the range of the particles is larger than the film thickness of the semiconductor consumed by forming the metal silicide layer. 2. The method according to claim 1, wherein the metal silicide formation region on the semiconductor substrate is made amorphous by performing ion implantation. 4. The method according to claim 1, wherein the metal silicide film is a cobalt silicide film.