JPH10223778A - Manufacture of semiconductor device and semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which is possessed of polysilicon films that are easily connected together, can be lessened in the number of manufacturing processes, shortened in production time, made compact enough in structure so as to be manufactured at a low cost, and enhanced in reliability. SOLUTION: A usual process where a first polysilicon film used for gate electrodes 32, 33, 321, and 331 and a second polysilicon film 7 formed on the first polysilicon film through the intermediary of an insulating film 5 are connected together and another process where impurities are injected into the second polysilicon film 7 are dispensed with, and a following process is carried out in place of the above processes as follows. Wirings 12 to 14 formed on a semiconductor substrate 1 and impurity diffusion regions 41 to 43, the first and second polysilicon film are electrically connected together through connection wirings 15 to 19 filled in contact holes provided to interlayer insulating films 5 and 9 at the same time when the contact holes are bored.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a contact hole of a semiconductor device and ion implantation of impurities.
Particularly, a polysilicon film such as an SRAM is used in a method for manufacturing a semiconductor device having two or more layers.

[0002]

2. Description of the Related Art A conventional method of manufacturing a semiconductor device such as an SRAM memory cell will be described with reference to FIGS. Each of the figures is a cross-sectional view showing a manufacturing process of a conventional semiconductor device. A transistor for a memory cell is formed on a semiconductor substrate 1. For example, a gate oxide film (SiO ₂ ) 2 as a first insulating film is formed on a p-type silicon semiconductor substrate 1.
Is formed by thermal oxidation. On the gate oxide film 2, a gate electrode 3 patterned from a first-layer polysilicon film having a thickness of about 100 nm is formed. On the semiconductor substrate 1, a field oxide film 21 thicker than the gate oxide film 2 is formed in the element isolation region by the LOCOS method.
The gate electrode 3 extends on the field oxide film 21 and forms an extension 31 thereof. Using the gate electrode 3 as a mask, n-type impurity diffusion regions 4 of source / drain regions are formed in the surface region of the semiconductor substrate 1 by ion implantation (FIG. 1A).

[0003] On the semiconductor substrate 1 which has been treated in this way, for example, the second insulating film 5 made of SiO ₂ CVD
(Chemical Vapor Deposition) or the like (FIG. 1B). The second insulating film 5 is formed by photolithography (PE
A part of the gate electrode extending portion 31 is removed by P (Photo Engraving Process), and a contact hole 6 is formed there. As described above, the gate electrode 3 is partially exposed by partially removing the second insulating film 5 by etching (FIG. 8A). Next, a second-layer polysilicon film 7 having a thickness of about 50 nm is deposited on the semiconductor substrate 1 by a CVD method or the like (FIG. 8B). The second-layer polysilicon film 7 is patterned by photolithography into a predetermined shape while being electrically connected to the gate electrode 3. An impurity 8 such as phosphorus (P) is ion-implanted into a part of the patterned polysilicon film 7 for the purpose of lowering the resistance (FIG. 9A). After that, C
A third insulating film 9 made of VDSiO ₂ or the like is deposited,
The second insulating film 5, the second polysilicon film 7 and the like are covered (FIG. 9B).

Next, the third insulating film 9, the second insulating film 5, and the first insulating film (gate oxide film) 2 are etched using anisotropic etching such as RIE to form an impurity diffusion region. A contact hole 10 for exposing the gate electrode 4 and the gate electrode extension 31 is formed. And contact hole 1
The impurity diffusion region 4 is ion-implanted with the impurity 11 such as As through the impurity diffusion region 4 through the impurity diffusion region 0 (FIG. 1).
0 (a)). Next, a buried metal such as tungsten (W) is grown on the impurity diffusion region 4 inside the contact hole 10 and the extension 31 of the gate electrode to form the connection wiring 1.
5, 16, and 17 are formed. The surface of the third insulating film 9 is flattened, and the surface of the third insulating film 9 is made of metal wiring 1 such as Al.
2, 13, and 14 are patterned. These metal wirings 12, 13, 14 are connected to connection wirings 15, 1 respectively.
6 and 17 (FIG. 10B).

[0005]

As described above, the prior art has a large number of times of photolithography and a number of times of impurity implantation, and has problems in terms of cost and delivery time. In addition, since the polysilicon film of the second layer is patterned in a region having a large step, there is a problem in reliability. According to the present invention, a method for manufacturing a highly reliable semiconductor device having a structure that allows easy connection between polysilicon films, shortens a process, shortens a manufacturing period, and can be manufactured at low cost, and using the method. Provided is a semiconductor memory device such as a formed SRAM.

[0006]

According to the present invention, there is provided a second-layer polysilicon film formed on a first-layer polysilicon film via an insulating film and a first-layer polysilicon film used for a gate electrode. And a step of implanting impurities into the polysilicon film of the second layer are omitted. These steps include an electrical connection between a wiring formed on the semiconductor substrate and an impurity diffusion region of the semiconductor substrate, and a semiconductor device. Electrical connection between the wiring formed on the substrate and the polysilicon films of the first and second layers is made via connection wiring embedded in the contact hole formed in the interlayer insulating film, and together with the opening of the contact hole. The process is simplified by performing the above steps. Further, the process is simplified by simultaneously implanting ions into the polysilicon film and the impurity diffusion region after opening the contact hole. Further, the semiconductor memory device of the present invention
The electrical connection between the first-layer polysilicon film serving as a gate electrode and the second-layer polysilicon film serving as a resistance element is made via connection wiring embedded in a contact hole formed in an insulating film. I do. Since the area of the connection region is reduced, the density of the semiconductor memory device is improved.

That is, a method of manufacturing a semiconductor device according to the present invention comprises:
Forming a gate electrode made of a first-layer polysilicon film on a first insulating film of a semiconductor substrate; and diffusing impurities into source / drain regions in a surface region of the semiconductor substrate using the gate electrode as a mask. Forming a region, forming a second-layer polysilicon film via a second insulating film covering the gate electrode, and patterning the second-layer polysilicon film to form at least a part of the gate electrode. Forming a polysilicon electrode disposed on the semiconductor substrate; forming a third insulating film on the semiconductor substrate so as to cover the gate electrode and the polysilicon electrode; The first insulating film, the second insulating film, and the third insulating film are etched to form a contact hole exposing the impurity diffusion region, and the contact hole is formed by anisotropic etching. Etching the third insulating film, the second insulating film and the polysilicon electrode to form contact holes exposing the polysilicon electrode and the gate electrode, respectively; and forming the semiconductor via the contact hole. Implanting impurities into the substrate to lower the resistance of the exposed portions of the polysilicon electrode and the gate electrode and re-diffusing the impurity diffusion region; and depositing a buried metal serving as a connection wiring in the contact hole. Through the connection wiring on the third insulating film,
Forming a wiring for electrically connecting the impurity diffusion region and a wiring for electrically connecting the gate electrode and the polysilicon electrode.

In the semiconductor substrate, a field oxide film is formed in an element isolation region, and the gate electrode formed in the element region has an extending portion extending over the field oxide film. You may do so. The extending portion may be covered with the second insulating film, and the polysilicon electrode may be arranged and formed on the second insulating film immediately above the extending portion. . The polysilicon electrode is covered with the third insulating film, and a wiring for electrically connecting the gate electrode and the polysilicon electrode is formed immediately above the polysilicon electrode. good. The wiring for electrically connecting the impurity diffusion region may be arranged and formed immediately above the impurity diffusion region. The wiring for electrically connecting the gate electrode and the polysilicon electrode, and the connection wiring for connecting the polysilicon wiring and the gate electrode may be formed on the extending portion.

Further, in the semiconductor memory device of the present invention, a semiconductor substrate, a first MOS transistor and a second MOS transistor formed on the semiconductor substrate, one of which is connected to a high-potential-side power supply voltage and the other is connected to Is the first MOS tiger. A first resistor connected to one of the source / drain regions of the transistor, and a second resistor connected to one of the source / drain regions of the second MOS transistor while the other is connected to the high potential side power supply voltage. One of a resistor and a source / drain region is connected to a first bit line, and the other of the source / drain region is connected to the first resistor and the first MOS.
A third MOS transistor connected to a connection point with the transistor and having a gate connected to the word line; one of a source / drain region connected to the second bit line and a source / drain
The other of the drain region is the second resistor and the second MO
A fourth MOS transistor connected to a connection point with the S transistor and having a gate connected to the word line, wherein the gate of the first MOS transistor has the second resistance and the second MOS transistor And the other of the source / drain regions is connected to GND (substrate potential), and the gate of the second MOS transistor is connected between the first resistor and the first MOS transistor. SRAM connected to a connection point and the other of the source / drain regions connected to GND (substrate potential)
A gate of the first MOS transistor extends over a field oxide film formed on the semiconductor substrate, and the first MOS transistor has a first gate directly above the extending portion.
The second resistor made of polysilicon formed with an interlayer insulating film between the first resistor and a first wiring formed immediately above the second resistor with a second interlayer insulating film between the second resistor and the second resistor. And a first connection wiring embedded in a first contact hole penetrating the first and second interlayer insulating films, and a gate of the second MOS transistor is connected to the semiconductor substrate. The first resistor and the first resistor made of polysilicon formed over the formed field oxide film and formed via the first interlayer insulating film immediately above the extending portion. A second wiring formed directly above the first resistor and via the second interlayer insulating film in a second contact hole penetrating through the first resistor and the first and second interlayer insulating films; Electrically connected by the embedded second connection wiring And wherein the door. The first and second
In the contact hole, the diameter of the portion of the first interlayer insulating film may be smaller than the diameter of the second interlayer insulating film.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. First, referring to FIG. 1 to FIG.
An example will be described. 1 to 4 are cross-sectional views illustrating the steps of manufacturing a semiconductor device. FIG. 4B is a sectional view of a transistor formed by this method. The transistor includes an n-type source / drain region (impurity diffusion region) 4 formed on a semiconductor substrate 1, a gate oxide film 2 formed between the source / drain regions, and a gate oxide film 2
And a polysilicon gate electrode 3 formed thereon. On the semiconductor substrate 1, a field oxide film 21 thicker than the gate oxide film 2 is formed in the element isolation region by the LOCOS method. The gate electrode 3 extends on the field oxide film 21, and the extension 31
Is composed. The source / drain region 4 and the gate electrode 3 on the surface of the semiconductor substrate 1 are covered with an interlayer insulating film 5 such as CVD SiO ₂ . The gate oxide film 2 is used as a first insulating film, and the interlayer insulating film 5 is used as a second insulating film. A patterned polysilicon film 7 is formed on the interlayer insulating film 5 on the extension 31 of the gate electrode 3. The polysilicon film 7 is used for, for example, a resistance element.

A third insulating film C is formed on the surface of the semiconductor substrate 1 so that the interlayer insulating film 5 and the polysilicon film 7 are covered.
An interlayer insulating film 9 made of VDSiO ₂ or the like is formed. The surface of the interlayer insulating film 9 is flattened, and metal wirings 12, 13, 1
4 is patterned. The metal wiring 12 and the n-type source / drain region 4 of the transistor are electrically connected by a connection wiring 15 such as W embedded in a contact hole formed through the interlayer insulating films 5 and 9 and the first insulating film 2. Connected. Further, the metal wiring 13 and the polysilicon film 7 and the gate electrode 3 are electrically connected by the connection wiring 16 such as W embedded in a contact hole formed through the interlayer insulating films 5 and 9 and the polysilicon film 7. It is connected to the. Metal wiring 14 and n-type source of transistor /
The drain region 4 is electrically connected to a connection wiring 17 such as W embedded in a contact hole formed through the interlayer insulating films 5 and 9 and the first insulating film 2.

Next, a method for forming the transistor on a semiconductor substrate will be described with reference to the drawings. First, a transistor is formed on the semiconductor substrate 1. For example, a gate oxide film (SiO ₂ ) 2 as a first insulating film is formed on a p-type silicon semiconductor substrate 1 by thermal oxidation. Further, a field oxide film 21 formed by the LOCOS method or the like is formed in the element isolation region of the semiconductor substrate 1. On the gate oxide film 2, a gate electrode 3 patterned from a first-layer polysilicon film having a thickness of about 100 nm is formed. The gate electrode 3 extends on the field oxide film 21, and the extension 31 is arranged. Using the gate electrode 3 as a mask, an n-type impurity diffusion region 4 of a source / drain region is formed by ion implantation (FIG. 1A). Next, an interlayer insulating film 5 as a second insulating film made of, for example, SiO ₂ is formed on the semiconductor substrate 1 by a CVD method or the like so as to cover the gate electrode 3 (FIG. 1B). Next, a second-layer polysilicon film 7 having a thickness of about 50 nm is deposited on the semiconductor substrate 1 by a CVD method or the like (FIG. 2A). The second-layer polysilicon film 7 is formed into a predetermined shape in a state where it is electrically connected to the gate electrode 3 by photolithography.
The extension 31 of the upper gate electrode is patterned (FIG. 2B).

Next, a third insulating film 9 made of CVD SiO ₂ or the like is deposited on the semiconductor substrate 1 to cover the second insulating film 5, the second-layer polysilicon film 7, and the like. Then R
The third insulating film 9, the second insulating film 5, and the polysilicon film 7 on the extension 31 of the gate electrode are etched by anisotropic etching such as IE, and the impurity diffusion region 4, the polysilicon of the second layer are etched. A contact hole 10 exposing the film 7 and the extension 31 is formed. The contact hole 10 exposing the impurity diffusion region 4 of the semiconductor substrate 1 has a uniform hole diameter. However, the contact hole 10 exposing the extension 31 of the gate electrode is formed in the second insulating film 5 near the bottom.
Are small in diameter, and the portion composed of the third insulating film near the surface is large in diameter. The difference is 2
This occurs because the etching rate of the second-layer polysilicon film 7 sandwiched between two insulating films is lower than the etching rates of these insulating films. As described above, if the diameter of the contact hole 10 is large at the entrance, the area of the exposed portion of the polysilicon film 7 of the second layer becomes large, so that the contact area between the polysilicon film 7 and the embedded connection metal becomes large. And the contact resistance becomes good (see FIG. 3).
(A)).

Next, impurities such as As are ion-implanted into the polysilicon film 7 of the second layer and the impurity diffusion region 4 through the contact hole 10 to reduce the resistance of the polysilicon film 7 and the gate electrode 3. At the same time, the impurity diffusion region 4 is re-diffused (FIG. 3B). Next, the impurity diffusion region 4 inside the contact hole 10 and the polysilicon film 7 of the second layer are formed.
A buried metal such as tungsten (W) is grown thereon to form connection wirings 15, 16 and 17. The surface of the third insulating film 9 is flattened, and metal wirings 12, 13, and 14 of Al or the like are patterned on the surface. These metal wiring, impurity diffusion region and gate electrode,
The second-layer polysilicon film is electrically connected by these connection electrodes (see FIG. 4). As described above, the polysilicon film 7 of the second layer used for the resistance element and the like
It is patterned on the field oxide film 21. Then, the extended portion 31 of the gate electrode, the second polysilicon film, and the metal wiring are electrically connected by a buried connection wiring formed in the contact hole. This is because if a process such as patterning or forming a contact hole is performed on the gate oxide film 2, the thin gate oxide film is likely to be broken.

However, according to the present invention, a second polysilicon film is formed on a gate in an element region, and the gate, the second polysilicon film and a metal wiring formed thereon are formed in a contact hole. It is also possible to connect with embedded connection wiring. Next, a second embodiment will be described with reference to FIGS. FIG. 5 is a circuit diagram of the SRAM, and FIG.
FIG. 6 is a sectional view of a semiconductor substrate on which the SRAM shown in FIG. 5 is formed. The silicon semiconductor substrate 1 has a p-well 22
And an n-well 23 are formed, and a field oxide film 21 of an element isolation region is formed in a surface region. This semiconductor substrate 1 is heat-treated to form a gate oxide film (SiO
₂ ) Form 2. Thereafter, a first-layer polysilicon film is deposited on the semiconductor substrate 1 and patterned to form gate electrodes 32, 3 on the SRAM memory cell portion in the element region.
Form 3 Gate electrodes 32 and 33 also extend on field oxide film 21, and gate electrode 3
The two extending portions 321 and the extending portion 331 of the gate electrode 33 are formed. In p well 22, an impurity diffusion region serving as a source / drain region is formed. Gate electrode 32 has n-type impurity diffusion regions 4 formed on both sides thereof.
MOS with source / drain regions 1 and 42
The transistor Q1 is constituted, and the gate electrode 33 is connected to the source / drain region formed of n-type impurity diffusion regions 42 and 43 formed on both sides thereof, and is connected to the MOS transistor Q2.
Is configured.

The semiconductor substrate 1 covers the gate oxide film 2, the field oxide film 21, and the gate electrodes 32 and 33.
An interlayer insulating film 5 is formed thereon. This interlayer insulating film 5
A resistor element R made of a second-layer polysilicon film 7
1, R2 are formed. Extension 3 of gate electrode 32
A resistance element R2 is formed on the interlayer insulating film 5 above the gate electrode 33, and the interlayer insulating film 5 on the extension 331 of the gate electrode 33 is formed.
A resistance element R1 is formed thereon. On interlayer insulating film 5, an interlayer insulating film 9 is formed so as to cover resistance elements R1 and R2. The surface of the interlayer insulating film 9 is flattened, and metal wirings 12, 13, and 14 made of aluminum or the like, which are electrically separated from each other, are patterned on this surface. These metal wirings are formed by an interlayer insulating film 5,
The semiconductor device 1 is electrically connected to an impurity diffusion region, a gate electrode, a resistance element, and the like of the semiconductor substrate 1 through a connection wiring made of tungsten or the like embedded in a contact hole such as 9. Metal wiring 12 is electrically connected to n-type impurity diffusion region 42 via connection wiring 15 embedded in a contact hole formed through interlayer insulating films 5 and 9 and gate oxide film 2. The metal wiring 13 is connected to an n-type impurity diffusion region 41 via a connection wiring 19 embedded in a contact hole formed through the interlayer insulating films 5 and 9 and the gate oxide film 2.
And the extension 331 of the resistance element R2 and the gate electrode 33 via the connection wiring 16 embedded in the contact hole formed through the interlayer insulation films 5 and 9 and the resistance element R1. Is electrically connected to

The metal wiring 14 is connected to the n-type impurity diffusion region 43 through the connection wiring 17 embedded in a contact hole formed through the interlayer insulating films 5 and 9 and the gate oxide film 2.
And the extension portion 321 of the resistance element R2 and the gate electrode 32 via the connection wiring 18 embedded in a contact hole formed through the interlayer insulation films 5, 9 and the resistance element R2. Is electrically connected to Through the subsequent steps, the SRAM is formed. The step of implanting impurities to lower the resistance of the connection portion of the resistance element to the connection wiring and the step of implanting impurities into the impurity diffusion region of the semiconductor substrate through the contact hole of the interlayer insulating film are performed in the same step.
The connection between the polysilicon resistor / gate electrode and the connection between the metal wiring / gate electrode are performed by the connection wiring buried in the contact hole of the interlayer insulating film, so that the area of the connection portion is reduced, and it has been conventionally performed. The step of connecting the gate electrode (first layer polysilicon film) and the resistance element (second layer polysilicon film) is omitted, and this step is the same as the step of connecting the metal wiring and the impurity diffusion region of the semiconductor substrate. It can be performed in a process. The transistors Q1, Q2 and the polysilicon resistor R1, formed on the semiconductor substrate shown in FIG.
R2 constitutes the memory cell of the SRAM shown in FIG.

Next, the SRAM cell of FIG. 5 will be described. This memory cell has four n-channel MOS transistors and two high resistances. That is, the memory cell
A first MOS transistor Q1 and a second MOS transistor Q2, one of which is connected to the high potential side power supply voltage and the other of which is connected to one of the source / drain regions of the first MOS transistor Q1 R1 and a second one connected to one of the source / drain regions of the second MOS transistor Q2, one of which is connected to the high potential side power supply voltage
And one of the source / drain regions is connected to the first bit line BL, the other of the source / drain regions is connected to the connection point between the first resistor R1 and the first MOS transistor Q1, and the gate Is connected to the word line WL, and one of the source / drain regions is connected to the second bit line / BL (“/” indicates an inverted signal), and the other of the source / drain regions Is connected to a connection point between the second resistor R2 and the second MOS transistor Q2, and the fourth gate is connected to the word line WL.
MOS transistor Q4, and the gate of the first MOS transistor Q1 is connected to the second resistor R2 and the second MOS transistor Q1.
The other of the source / drain regions is connected to GND (substrate potential), and the gate of the second MOS transistor Q2 is connected to the first resistor R1 and the first MOS transistor. The other of the source / drain regions (for example, the source) is connected to GND (substrate potential).

As described above, in the embodiments, aluminum is used for the wiring connecting the impurity diffusion region and the polysilicon film. However, the present invention is not limited to this, and Cu, silicide of a high melting point metal, and a polysilicon film are used. And a polycide film which is a composite film of a silicide film and a silicide film. Further, the buried connection wiring is not limited to tungsten, and other high melting point metals such as molybdenum, titanium, and tantalum can be used.

[0020]

According to the present invention, the step of connecting the first polysilicon film serving as the gate electrode and the second polysilicon film used for the resistance element and the like is performed in the same step as the step of connecting the metal wiring and the semiconductor substrate. Thus, the former step can be omitted. Further, the former impurity implantation step is omitted by making the impurity implantation for lowering the resistance of the portion of the second polysilicon film connected to the metal wiring the same as the step of implanting the impurity into the semiconductor substrate through the contact hole. it can. As described above, it is possible to reduce the number of steps by two and to manufacture a highly reliable semiconductor device that can be accurately implanted because impurities are implanted into a flat portion when the second polysilicon film is implanted. Can provide a way to

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 5 is a circuit diagram of an SRAM according to a second embodiment of the present invention.

FIG. 6 is a partial cross-sectional view of a semiconductor substrate on which the SRAM of FIG. 5 is formed.

FIG. 7 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the first conventional example.

FIG. 8 is a cross-sectional view of a manufacturing process of the semiconductor device according to the first conventional example.

FIG. 9 is a cross-sectional view illustrating a manufacturing process of a conventional semiconductor device.

FIG. 10 is a sectional view showing a manufacturing process of a conventional semiconductor device.

DESCRIPTION OF SYMBOLS 1 ... semiconductor substrate, 2 ... first insulating film (gate oxide film), 3, 32, 33 ... first polysilicon film (gate electrode), 4, 41, 42, 43: impurity diffusion region (source / drain region), 5: second insulating film (interlayer insulating film), 6, 10: contact hole, 7: polysilicon of second layer Membranes, 8, 11, 14
... Ion implantation for lowering resistance, 9 ... Third insulating film (interlayer insulating film), 12, 13, 14 ... Metal wiring, 15, 16, 17, 18, 19 ... Connection wiring, 2
1 ... field oxide film, 22 ... p well,
23 ... n-well, 31, 321, 331 ...
The extension of the gate electrode.

Claims (8)

[Claims] 1. A step of forming a gate electrode made of a first-layer polysilicon film on a first insulating film of a semiconductor substrate, and using a source / drain of an impurity in a surface region of the semiconductor substrate using the gate electrode as a mask. Forming an impurity diffusion region serving as a region; forming a second-layer polysilicon film via a second insulating film covering the gate electrode; and patterning the second-layer polysilicon film to form at least one layer. The step of forming a polysilicon electrode disposed on the gate electrode; and forming a third insulating film on the semiconductor substrate so as to cover the gate electrode and the polysilicon electrode. The first insulating film, the second insulating film, and the third insulating film are etched by anisotropic etching to form a contact hole exposing the impurity diffusion region. Etching the third insulating film, the second insulating film, and the polysilicon electrode by etching to form contact holes exposing the polysilicon electrode and the gate electrode, respectively; Implanting impurities into the semiconductor substrate, lowering the resistance of the exposed portions of the polysilicon electrode and the gate electrode, and re-diffusing the impurity diffusion region; depositing a buried metal serving as a connection wiring in the contact hole Forming a wire for electrically connecting the impurity diffusion region and a wire for electrically connecting the gate electrode and the polysilicon electrode on the third insulating film via the connection wire. A method for manufacturing a semiconductor device, comprising: 2. The semiconductor substrate according to claim 1, wherein a field oxide film is formed in a device isolation region, and said gate electrode formed in said device region has an extending portion extending over said field oxide film. 2. The method for manufacturing a semiconductor device according to claim 1, wherein 3. The extension portion is covered by the second insulating film, and the polysilicon electrode is disposed and formed on the second insulation film immediately above the extension portion. 3. The method for manufacturing a semiconductor device according to claim 2, wherein: 4. The method according to claim 1, wherein the polysilicon electrode is covered with the third insulating film, and a wiring for electrically connecting the gate electrode and the polysilicon electrode is formed immediately above the polysilicon electrode. The method for manufacturing a semiconductor device according to claim 3, wherein 5. The method according to claim 4, wherein a wiring for electrically connecting the impurity diffusion region is formed immediately above the impurity diffusion region. 6. The wiring which electrically connects the gate electrode and the polysilicon electrode, and the connection wiring which connects the polysilicon wiring and the gate electrode are formed on the extending portion. A method for manufacturing a semiconductor device according to claim 2. 7. A semiconductor substrate, a first MOS transistor and a second MOS transistor formed on the semiconductor substrate, one of which is connected to a high-potential-side power supply voltage, and the other of which is connected to the first MOS transistor. A first resistor connected to one of the source / drain regions, one connected to the high-potential-side power supply voltage, and the other connected to the second resistor.
A second resistor connected to one of the source / drain regions of the MOS transistor, one of the source / drain regions is connected to the first bit line, and the other of the source / drain region is connected to the first resistor and the first resistor. A third MOS transistor connected to a connection point with the first MOS transistor and a gate connected to a word line; one of a source / drain region connected to a second bit line and the other of the source / drain region Is connected to a connection point between the second resistor and the second MOS transistor, and a fourth MOS transistor having a gate connected to the word line is provided.
The gate of the MOS transistor is connected to a connection point between the second resistor and the second MOS transistor, and the other of the source / drain regions is connected to GND (substrate potential). A gate of the transistor is connected to a connection point between the first resistor and the first MOS transistor, and the other of the source / drain regions is connected to a gate of the transistor.
An SRAM cell connected to ND (substrate potential), wherein the gate of the first MOS transistor extends over a field oxide film formed on the semiconductor substrate, and The second resistor made of polysilicon formed immediately above the portion having the first interlayer insulating film interposed therebetween, and the second resistor formed directly above the second resistor with the second interlayer insulating film interposed therebetween. A first connection wiring buried in a first contact hole penetrating the second resistor and the first and second interlayer insulating films to the first wiring; A gate of the transistor extends over a field oxide film formed on the semiconductor substrate, and is formed of polysilicon formed directly above the extending portion via the first interlayer insulating film. Said first resistor and said first resistor A second wiring formed directly above the resistor via the second interlayer insulating film is embedded in a second contact hole penetrating the first resistor and the first and second interlayer insulating films. A semiconductor memory device electrically connected by the second connection wiring. 8. The device according to claim 7, wherein the first and second contact holes have a diameter of a portion of the first interlayer insulating film smaller than a diameter of the second interlayer insulating film. Semiconductor storage device.