JPH1022374A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To chemically and mechanically polish the surface of a semiconductor device flat, without using a block resist pattern and without being affected by the dependence of the polishing rate on the pattern density. SOLUTION: After depositing a polishing stopper film on the surface of a semiconductor substrate 1, the substrate is etched to form grooves 4 of element isolating regions. An insulation film 5 is deposited on the substrate 1 and burying it in the grooves 4, an S film 6 is deposited on the insulation film 5 and polished by the chemical-mechanical polishing to remove the Si film 6 on element regions 3, the film 6 remaining in the grooves 4 is thermally oxidized into a silicon dioxide film 7, and the insulation film 5 and dioxide film 7 are polished by the chemical-mechanical polishing at once to planarize them.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a chemical mechanical polishing (CM) method.
P: Chemical Mechanical Pol
The present invention relates to an improvement in a method of flattening an insulating film for element isolation in which a buried oxide film is formed by flattening a surface by ising.

[0002]

2. Description of the Related Art Conventionally, as a device isolation method of a semiconductor device, a local oxidation method (LOCOS method) using a silicon nitride film as an oxidation resistant mask, that is, a selective oxidation method has been widely used. In a selective oxidation method, there is a problem that a bird's beak is entangled in an oxide film, and the oxide film is oxidized to the upper portion of the element region.

When the element regions are close to each other, the thickness of the buried oxide film between the element regions becomes small, so that there is a problem that sufficient element isolation cannot be achieved. There have been problems such as generation of defects in the semiconductor substrate due to stress.

In order to solve such problems, a so-called shallow trench isolation method has been proposed in which a trench is provided between element regions, a CVD-SiO ₂ film is deposited, and the trench is filled with the CVD-SiO ₂ film. However, since unevenness occurs on the surface, a flattening step is required to eliminate the unevenness.

Conventionally, as such a surface flattening method, a block resist pattern is provided in a large area concave portion on the surface of a CVD-SiO ₂ film covering a trench, and then a flattening resist is applied, and a resist etch back is performed. To etch the CVD-SiO ₂ film together with the resist to flatten its surface (if necessary, use IEDM Tech. D
ig. 1987, p. 732) has been proposed.

As another surface flattening method, a method of forming a buried oxide film by flattening the surface by a chemical mechanical polishing method (if necessary, using Applied Physics)
Letters, vol. 61, 1992, p. 13
44) has also been proposed.

Further, as another surface flattening method, a method combining a resist etch back method and a chemical mechanical polishing method (if necessary, IEDM Tech. Dig., 19
89, p. 61) has been proposed.

[0008]

However, when the resist etch-back method is used, it is difficult to arrange a block resist pattern, that is, how large a trench resist or a concave should be when arranging a block resist pattern. Is difficult to determine, and a photolithography process requiring alignment is required.

When the chemical mechanical polishing method is used,
There is a problem that the polishing characteristics depend on the density of the pattern, and the effective polishing pressure is reduced in a large-area mesa or a region where fine patterns are densely packed like a memory cell portion, and the polishing rate is reduced.

Here, the problems of the conventional CMP method are illustrated.
This will be described with reference to FIG. See FIGS. 5A and 5B. Silicon serving as a polishing stopper film on a silicon substrate 31
After forming the nitride film 32, to form an element isolation region
Is formed, and CVD-SiO _TwoMembrane 34
To form a trench 33 by CVD-SiO.
_TwoIt is embedded with the film 34.

Next, when the CVD-SiO ₂ film 34 is flattened by using a chemical mechanical polishing method (CMP method), the CVD-SiO ₂ film 3 deposited on the mesa 35 having an isolated small area is formed.
Since 4 is easily polished, a depression 38 is generated by excessive polishing, while insufficient polishing occurs on the mesa 36 having a large area.

When the CVD-SiO ₂ film 34 deposited on the large-area mesa 36 is to be completely removed,
Since the silicon nitride film 32 provided on the surface of the isolated small-area mesa 35 does not function as a polishing stopper film, there is a problem that the isolated small-area mesa 35 itself is polished and the buried oxide film becomes thin. .

Referring to FIG. 5C, this depends on the surface shape of the silicon substrate 31.
This is because the polishing rate varies depending on the size of the projections 37 formed on the SiO ₂ film 34.
Assuming that the step formed on the _second film 34 is 0.7 μm, when the pattern size of the convex portion 37 is 0.5 mm × 0.5 mm, the polishing rate is about 7,000 ° (0.7 μm) / min. On the other hand, in the case of 4 mm × 4 mm, the polishing rate is about 1000 ° (0.1 μm) / min, which is about 1/7.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to perform chemical mechanical polishing of a surface flat without using a block resist pattern and without being affected by the dependence of the polishing rate on the pattern density.

[0015]

FIG. 1 is an explanatory view of the principle configuration of the present invention. Referring to FIG. 1, means for solving the problems in the present invention will be described. 1 (a) to 1 (c) (1) In the method of manufacturing a semiconductor device, a step of depositing a film serving as a polishing stopper film 2 on a surface of a semiconductor substrate 1 is performed. Forming a trench 4 to be an isolation region; depositing an insulating film 5 on the semiconductor substrate 1 to fill the trench 4; depositing a silicon film 6 on the insulating film 5; Polishing, removing the silicon film 6 on the element region 3, thermally oxidizing the silicon film 6 remaining on the trench 4 to convert it to a silicon dioxide film 7, and insulating the insulating film 5 and the silicon dioxide film 7. Are simultaneously polished by a chemical mechanical polishing method, and the step of flattening is sequentially performed.

When the silicon film 6, ie, the polycrystalline silicon film or the amorphous silicon film is thermally oxidized, the deposition expands about twice, so that the silicon film pattern is thermally oxidized and converted into the silicon dioxide film 7, By polishing after reducing the surface irregularities, a flat buried insulating film 8 can be formed without being affected by the dependence of the polishing rate on the pattern density.

Further, in the patterning step and the surface flattening step of the silicon film 6, only a chemical mechanical polishing method is used without using a photolithography step, so that an alignment step becomes unnecessary and the steps can be simplified. Can be.

(2) Further, according to the present invention, in a method of manufacturing a semiconductor device, a step of depositing a film serving as a polishing stopper film 2 on a surface of a semiconductor substrate 1 and a step of etching the semiconductor substrate 1 to form a groove serving as an element isolation region. 4, a step of depositing an insulating film 5 on the semiconductor substrate 1 to fill the groove 4, a step of depositing a silicon film 6 on the insulating film 5,
The silicon film 6 on the element region 3 is removed by polishing the silicon film 6 by a chemical mechanical polishing method.
Converting the insulating film 5 and the silicon dioxide film 7 to a halfway, thermally polishing the insulating film 5 and the silicon dioxide film 7 halfway, and simultaneously polishing and flattening the insulating film 5 and the silicon dioxide film 7 by the chemical mechanical polishing method. Is characterized in that the steps of converting are sequentially performed.

As described above, by performing the surface flattening step in two steps of the etch-back step and the chemical mechanical polishing step, the thickness of the film removed by the chemical mechanical polishing step is reduced, and the buried insulating film 8 is formed. Can be more uniformly and highly accurately performed.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A manufacturing process according to a first embodiment of the present invention will be described with reference to FIGS. 2A, the surface of the silicon substrate 11 is first thermally oxidized to a thickness of 5 to 2 mm.
After forming a pad oxide film 12 having a thickness of 0 nm, for example, 10 nm, a silicon nitride film 13 serving as a polishing stopper film at the time of chemical mechanical polishing with a thickness of 50 to 200 nm, for example, 100 nm is deposited by a CVD method. The silicon nitride film 13, the pad oxide film 12, and the silicon substrate 11 are sequentially etched by dry etching using a pattern (not shown) as a mask, thereby forming trenches 14 and 15 having a depth of 200 to 600 nm, for example, 400 nm. To form

The trench 14 is a wide groove for separating a peripheral circuit formation region on the left side of the drawing from an element formation region of a memory or the like on the right side of the drawing, and the trench 15 separates each element formation region. It is a narrow groove.

Next, after removing the resist pattern, the surface of the exposed trenches 14 and 15 is thermally oxidized to a thickness of 5 nm.
A sacrificial oxide film (not shown) having a thickness of, for example, 30 nm, for example, 30 nm, is formed.
100-800 nm, for example, 500 nm CVD-Si
An O ₂ film 16 is deposited.

Prior to the formation of the sacrificial oxide film,
The channel is formed in the surface of the trenches 14 and 15 exposed according to
A cut region (not shown) may be formed,
When the cut region is formed, the surface region of the silicon substrate 11 is formed.
Is n-type, As or the like is obliquely ion-implanted and n⁺Type
A region is formed, and in the case of a p-type region, B and the like are oblique ions.
Inject and p⁺Mold region and sacrificial oxidation
The film is CVD-SiO _TwoThe deposition process of the film 16 or the
In the subsequent steps, the surface of the silicon substrate 11 is contaminated.
Or to prevent moisture from entering,
To remove the damaged layer during silicon etching
It is provided.

Next, in a dry oxygen atmosphere, 1000
By performing heat treatment at 25 ° C. for 25 minutes, CVD-S
The iO ₂ film 16 is densified. By this heat treatment, CV
The D-SiO ₂ film 16 becomes dense enough to function as a buried oxide film, and has a polishing rate similar to that of a thermal oxide film in a subsequent chemical mechanical polishing step.

Next, as shown in FIG. 2C, the entire surface is formed to a thickness of 200 to 400 by the CVD method.
A polycrystalline silicon film 17 having a thickness of, for example, 300 nm is deposited.

Next, as shown in FIG. 3D, the polycrystalline silicon film 17 is polished by chemical mechanical polishing using a foamed polyurethane polishing cloth as a polishing cloth and a corodyl silica polishing agent as a polishing agent. The polycrystalline silicon film 17 deposited on the formation region and the element formation region is removed.

In this case, the remaining polycrystalline silicon film 18 deposited on the wide trench 14 is also polished by polishing.
For example, since the thickness is reduced by about 100 nm, the thickness of the polycrystalline silicon film 17 at the time of deposition needs to be determined in consideration of the reduction due to polishing of the remaining film 18 of the polycrystalline silicon film deposited on the wide trench 14. is there.

Referring to FIG. 3E, when the remaining film 18 of the polycrystalline silicon film is 200 nm, the polycrystalline silicon film on the wide trench 14 is heat-treated at 1000 ° C. for 125 minutes in a wet oxygen atmosphere. Is thermally oxidized to be converted into a silicon dioxide film, that is, a thermal oxide film 19.

Since the thickness of the remaining film 18 of the polycrystalline silicon film is approximately doubled by this thermal oxidation, that is, the thickness 200
The remaining film 18 of a polycrystalline silicon film having a thickness of about 400 nm
m, the depth of the CVD-SiO ₂ film 16 formed on the trench 14 is 400 nm.
The concave portion of the degree is buried almost flat, and the global step is eliminated.

Next, as shown in FIG. 3 (f), the convex portion of the silicon substrate 11, ie, the surface of the peripheral circuit forming region and the element forming region, is formed by a polishing cloth made of polyurethane foam and a chemical mechanical polishing using a colloidal silica abrasive. Polishing is performed until the silicon nitride film 13 provided on the substrate is exposed, so that the thermal oxide film 19 and the CVD are removed.
-SiO ₂ unnecessary portion is removed in the film 16, the surface fill the trench 14 and 15 by the buried oxide film 20 made of a thermal oxide film 19 and the CVD-SiO ₂ film 16 having a planarized.

Next, although not shown, the silicon nitride film 13 and the pad oxide film 12 are removed by etching to complete an element isolation structure buried by the buried oxide film 20.

As described above, in the first embodiment of the present invention, the recess formed in the CVD-SiO ₂ film 16 is
Polishing is performed after the surface is flattened by embedding the remaining film 18 of the polycrystalline silicon film with a thermally oxidized film 19 converted by thermal oxidation, so that the pattern at the time of polishing does not depend on the density of the silicon substrate. Since the polishing stopper film made of the silicon nitride film 13 is provided on the top surface of the peripheral circuit formation region and the device formation region, the polishing surface is automatically stopped by the polishing stopper film even if the polishing time is long, resulting in excessive polishing. No dishing occurs due to the above.

Next, referring to FIG. 4, a second embodiment of the present invention in which the polishing step is performed in two stages of an etch-back step and a chemical mechanical polishing step will be described. Referring to FIG. 4A, first, similarly to the first embodiment, the surface of the silicon substrate 11 is thermally oxidized to a thickness of 5 to 20 nm, for example, 10 nm.
After the pad oxide film 12 is formed, a silicon nitride film 13 serving as a polishing stopper film at the time of chemical mechanical polishing (CMP) with a thickness of 50 to 200 nm, for example, 100 nm is deposited by a CVD method, and then a resist pattern ( The silicon nitride film 13, the pad oxide film 12, and the silicon substrate 11 are sequentially etched by dry etching using a
ト レ ン チ 600 nm, for example, 400 nm trenches 14,1
5 is formed.

Next, after removing the resist pattern, a sacrificial oxide film (not shown) having a thickness of 5 nm to 30 nm, for example, 30 nm is formed on the exposed surfaces of the trenches 14 and 15 by thermal oxidation. A CVD-SiO ₂ film 16 having a thickness of 300 to 800 nm, for example, 500 nm is deposited on the entire surface by a method.

Next, in a dry oxygen atmosphere, 1000
By performing heat treatment at 25 ° C. for 25 minutes, CVD-S
After the iO ₂ film 16 is densified, a polycrystalline silicon film having a thickness of 200 to 600 nm, for example, 300 nm is deposited on the entire surface by CVD.

Next, the polycrystalline silicon film is polished by chemical mechanical polishing using a foamed polyurethane polishing cloth as a polishing cloth and a corodyl / silica polishing agent as a polishing agent. After removing the polycrystalline silicon film deposited on the substrate, if the remaining polycrystalline silicon film has a thickness of 200 nm, in a wet oxygen atmosphere,
By performing heat treatment at 1000 ° C. for 125 minutes, the remaining polycrystalline silicon film on the wide trench 14 is thermally oxidized and converted into a silicon dioxide film, that is, a thermal oxide film 19.

Next, the thickness of the CVD-SiO ₂ film 16 on the peripheral circuit formation region and the element formation region is reduced to 20 to 20 by dry etching using CF ₄ or CHF ₃ as a reaction gas.
Etch back is performed to a thickness of about 200 nm, for example, about 100 nm, to reduce the thickness.

4C, the convex portions of the silicon substrate 11, ie, the surface of the peripheral circuit formation region and the element formation region, are formed by a polishing machine made of foamed polyurethane and chemical mechanical polishing using a colloidal silica abrasive. Polishing is performed until the silicon nitride film 13 provided on the silicon oxide film 13 is exposed.
And CVD-SiO ₂ unnecessary portion is removed in the film 16, a thermal oxide film surface is flattened 19 and CVD-SiO ₂ film 16
The trenches 14 and 15 are buried with a buried oxide film 20 made of.

Next, although not shown, the silicon nitride film 13 and the pad oxide film 12 are removed by etching to complete an element isolation structure buried by the buried oxide film 20.

As described above, in the second embodiment of the present invention, the CVD-SiO ₂ film 16 and the thermal oxide film 19 are thinned in advance by etch-back. It becomes shorter and the polishing accuracy is improved.

In the second embodiment,
Although the etchback is performed by dry etching, wet etching using diluted hydrofluoric acid, buffered hydrofluoric acid, or the like as an etchant may be used.

Also in the second embodiment,
Prior to the formation of the sacrificial oxide film, a channel cut region may be formed on the exposed surfaces of the trenches 14 and 15 by oblique ion implantation of impurities using a resist pattern as a mask.

In the description of each of the above embodiments, a polycrystalline silicon film is used to change into a thermal oxide film. However, the present invention is not limited to a polycrystalline silicon film.
An amorphous silicon film may be used.

[0044]

According to the present invention, it is possible to form a buried oxide film for element isolation using a chemical mechanical polishing method (CMP method) without using a step of exposing a dummy pattern such as a block resist. The polycrystalline silicon film remaining in the concave portion by polishing is thermally oxidized to be converted into a silicon dioxide film and
After the surface of the O ₂ film is flattened, polishing for flattening is performed, so that there is no dependency on pattern density and no dishing occurs, and a flat and fine element isolation structure can be realized. .

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a basic configuration of the present invention.

FIG. 2 is an explanatory diagram of a manufacturing process partway through the first embodiment of the present invention.

FIG. 3 is an explanatory view of a manufacturing process of the first embodiment of the present invention after FIG. 2;

FIG. 4 is an explanatory diagram of a manufacturing process according to a second embodiment of the present invention.

FIG. 5 is an explanatory diagram of a problem of a conventional CMP method.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate 2 polishing stopper film 3 element region 4 groove 5 insulating film 6 silicon film 7 silicon dioxide film 8 buried insulating film 11 silicon substrate 12 pad oxide film 13 silicon nitride film 14 trench 15 trench 16 CVD-SiO ₂ film 17 many Crystalline silicon film 18 polycrystalline silicon film remaining film 19 thermal oxide film 20 buried oxide film 31 silicon substrate 32 silicon nitride film 33 trench 34 CVD-SiO ₂ film 35 isolated small area mesa 36 large area mesa 37 convex part 38 hollow

Claims (2)

[Claims] A step of depositing a film serving as a polishing stopper film on a surface of a semiconductor substrate; a step of forming a groove serving as an element isolation region by etching the semiconductor substrate; and a step of depositing an insulating film on the semiconductor substrate. Filling the groove, depositing a silicon film on the insulating film, polishing the silicon film by a chemical mechanical polishing method, removing the silicon film on the element region, removing the silicon film remaining on the groove. Converting it to a silicon dioxide film by thermal oxidation, and
A method of manufacturing a semiconductor device, wherein the steps of simultaneously polishing and planarizing the insulating film and the silicon dioxide film by a chemical mechanical polishing method are sequentially performed. A step of depositing a film serving as a polishing stopper film on a surface of the semiconductor substrate; a step of forming a groove serving as an element isolation region by etching the semiconductor substrate; and a step of depositing an insulating film on the semiconductor substrate. Filling the groove, depositing a silicon film on the insulating film, polishing the silicon film by a chemical mechanical polishing method, removing the silicon film on the element region, removing the silicon film remaining on the groove. Thermally oxidizing into a silicon dioxide film, etching back the insulating film and the silicon dioxide film halfway, and simultaneously polishing and flattening the insulating film and the silicon dioxide film by a chemical mechanical polishing method A method for manufacturing a semiconductor device, wherein the steps are sequentially performed.