JPH10223679A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH10223679A JPH10223679A JP9025014A JP2501497A JPH10223679A JP H10223679 A JPH10223679 A JP H10223679A JP 9025014 A JP9025014 A JP 9025014A JP 2501497 A JP2501497 A JP 2501497A JP H10223679 A JPH10223679 A JP H10223679A
- Authority
- JP
- Japan
- Prior art keywords
- pad
- semiconductor device
- bonding
- circuit
- pad patterns
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05551—Shape comprising apertures or cavities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4845—Details of ball bonds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、半導体装置(半導
体デバイス)及びその製造方法に関する。The present invention relates to a semiconductor device (semiconductor device) and a method for manufacturing the same.
【0002】[0002]
【従来の技術】半導体チップの製造の際には製造された
半導体チップが適切に動作するか否かを確認するために
テストを行なう必要がある。そのテストのために半導体
チップにはテスト回路が組み込まれている場合がある。
テストが終了した後の製品として半導体装置ではそのテ
スト回路は必要ないので、ユーザが誤ってテスト回路を
使用すると甚大な被害を被る恐れがある場合には、ユー
ザに対してその製品の規格書においてテスト回路部分の
使用禁止を明記することが一般的である。2. Description of the Related Art When manufacturing a semiconductor chip, it is necessary to conduct a test to confirm whether the manufactured semiconductor chip operates properly. In some cases, a test circuit is incorporated in a semiconductor chip for the test.
Since a test circuit is not necessary for a semiconductor device as a product after the test is completed, if the user accidentally uses the test circuit and serious damage may be caused, the user is required to comply with the product specification. It is common to specify that use of the test circuit is prohibited.
【0003】[0003]
【発明が解決しようとする課題】しかしながら、規格書
上での禁止の明記では不十分なことが多いので、ハード
ウエアにて強制的に使用不可能にすることが必要な場合
がある。例えば、テスト終了後、予め備えられたヒュー
ズを熔断させてテスト回路機能を不活性状態にしたり、
特定の機能が動作しないようにモールドでパッケージ化
する前にレーザトリミングを行なうことがある。ところ
が、このようなハードウエアにて強制的に使用不可能に
することは製造コストを増加させるという問題点があっ
た。However, since it is often insufficient to specify the prohibition in the standard, it is sometimes necessary to forcibly disable the use of hardware. For example, after the test is completed, a fuse provided in advance is blown to make the test circuit function inactive,
In some cases, laser trimming is performed before packaging with a mold so that a specific function does not operate. However, forcibly disabling the use of such hardware has a problem of increasing the manufacturing cost.
【0004】このことは、半導体チップの単にテスト回
路に拘らず、製造完了後、製品として出荷するときには
例えば、ユーザが必要な動作機能だけ残して電力消費を
抑えるために不必要な動作機能を失わせたい場合にも同
様である。そこで、本発明の目的は、製造コストをほと
んど増加させることなく、特定の動作機能を変更させる
ことができる半導体装置及び製造方法を提供することで
ある。[0004] This means that, regardless of the test circuit of the semiconductor chip, when the product is shipped as a product after completion of manufacture, for example, the user loses unnecessary operation functions in order to reduce power consumption while leaving only necessary operation functions. The same applies to the case where the user wants to make it. Therefore, an object of the present invention is to provide a semiconductor device and a manufacturing method capable of changing a specific operation function without substantially increasing the manufacturing cost.
【0005】[0005]
【課題を解決するための手段】本発明の半導体装置は、
ワイヤボンディングにより電気的に短絡されるようにチ
ップ上に隣接形成された少なくとも2つのパッドパター
ンと、その少なくとも2つのパッドパターン間の短絡を
検知する検知手段と、検知手段による短絡の検知に応じ
て動作機能を変更する回路とを備えたことを特徴として
いる。According to the present invention, there is provided a semiconductor device comprising:
At least two pad patterns formed adjacently on the chip so as to be electrically short-circuited by wire bonding, detecting means for detecting a short circuit between the at least two pad patterns, and detecting the short circuit by the detecting means. And a circuit for changing an operation function.
【0006】本発明の半導体装置の製造方法は、チップ
上に隣接して少なくとも2つのパッドパターンを形成
し、その少なくとも2つのパッドパターンをボンディン
グワイヤにより電気的に短絡するワイヤボンディングを
行なうことを特徴としている。A method of manufacturing a semiconductor device according to the present invention is characterized in that at least two pad patterns are formed adjacently on a chip, and wire bonding for electrically shorting the at least two pad patterns with bonding wires is performed. And
【0007】[0007]
【発明の実施の形態】以下、本発明の実施例を図面を参
照しつつ詳細に説明する。図1は半導体チップの表面を
示しており、導体パターン1がチップ2表面に形成され
ている。導体パターン1は共通ラインであり、プローブ
用パッド3とボンディングパッド4とを備えている。プ
ローブ用パッド3は半導体チップ製造過程のウエハプロ
セス後のプローブテストにおいてプローブ(図示せず)
の先端が当てられる部分である。そのテストの際にテス
ト回路5が利用されるのである。ボンディングパッド4
はパッケージの外部端子との接続のためにボンディング
ワイヤ6が接続される電極部分である。ボンディングパ
ッド4は図示のように四角形の環状でその一部が切断さ
れた外形であり、外部と連通する空間部4aを中央部分
に有する。空間部4aには導体部材からなるメタルパッ
ド7がボンディングパッド4と電気的に非接触状態で形
成されている。メタルパッド7はリードパターン8と一
体にチップ2表面に形成され、リードパターン8は環状
切断部を介してボンディングパッド4外に延びている。Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows the surface of a semiconductor chip, in which a conductor pattern 1 is formed on the surface of a chip 2. The conductor pattern 1 is a common line, and includes a probe pad 3 and a bonding pad 4. The probe pad 3 serves as a probe (not shown) in a probe test after a wafer process in a semiconductor chip manufacturing process.
Is the part to which the tip of is applied. The test circuit 5 is used for the test. Bonding pad 4
Is an electrode portion to which the bonding wire 6 is connected for connection with an external terminal of the package. As shown in the figure, the bonding pad 4 has a quadrangular ring shape and a partially cut outer shape, and has a space portion 4a communicating with the outside in a central portion. A metal pad 7 made of a conductor member is formed in the space 4a in a state of being electrically non-contact with the bonding pad 4. The metal pad 7 is formed integrally with the lead pattern 8 on the surface of the chip 2, and the lead pattern 8 extends outside the bonding pad 4 via an annular cut portion.
【0008】リードパターン8はレベル検出回路11に
接続されている。レベル検出回路11は短絡検知手段で
あり、抵抗12とインバータ13とからなる。それら抵
抗12及びインバータ13は実際には回路パターンとし
てチップ2に形成されているが、ここでは分かり易くす
るために回路記号として示している。抵抗12の一端に
は電圧Vddが印加され、その他端がリードパターン8及
びインバータ13の入力に接続されている。インバータ
13は入力レベルをレベル反転して出力するものであ
る。インバータ13の出力信号が上記のテスト回路5に
供給されるようになっている。テスト回路5はインバー
タ13の出力レベルが低レベルであるときテスト動作を
行なうことができる活性状態となり、インバータ13の
出力レベルが高レベルであるときテスト動作を行なうこ
とができない不活性状態となる。[0008] The lead pattern 8 is connected to a level detection circuit 11. The level detection circuit 11 is short-circuit detection means, and includes a resistor 12 and an inverter 13. The resistor 12 and the inverter 13 are actually formed on the chip 2 as a circuit pattern, but are shown here as circuit symbols for easy understanding. The voltage Vdd is applied to one end of the resistor 12, and the other end is connected to the lead pattern 8 and the input of the inverter 13. The inverter 13 inverts the input level and outputs the result. The output signal of the inverter 13 is supplied to the test circuit 5 described above. Test circuit 5 is in an active state where the test operation can be performed when the output level of inverter 13 is low, and in an inactive state where the test operation cannot be performed when the output level of inverter 13 is high.
【0009】半導体チップのテストは、ワイヤボンディ
ングが行なわれる前に行なわれ、そのテストの際にはテ
スト回路5が用いられる。外部の測定装置によってその
半導体チップの動作データを抽出するためにプローブが
プローブ用パッド3に当てられる。このテストにおいて
は、電圧Vddが抵抗12を介してインバータ13の入力
に供給されるので、その入力レベルは高レベルであり、
インバータ13の出力レベルは低レベルとなる。この低
レベルによってテスト回路5は活性状態となる。A test of a semiconductor chip is performed before wire bonding is performed, and a test circuit 5 is used in the test. A probe is applied to the probe pad 3 to extract operation data of the semiconductor chip by an external measuring device. In this test, since the voltage Vdd is supplied to the input of the inverter 13 via the resistor 12, the input level is high,
The output level of the inverter 13 becomes low. The test circuit 5 is activated by this low level.
【0010】半導体チップのテストの終了後、ワイヤボ
ンディングが行なわれ、ボンディングパッド4とメタル
パッド7とが電気的に接続される。すなわち、ワイヤボ
ンディングは導体パターン1と外部のアース又は回路と
の電気的接続をパッケージの外部端子(図示せず)を介
して得るようにするために行われ、そのワイヤボンディ
ングの際には、図のように、例えば、金からなるボンデ
ィングワイヤ6の先端はボンディングボール16となっ
ており、そのボンディングボール16がボールボンディ
ング法等の熱圧着法によりメタルパッド7を含むボンデ
ィングパッド4に接着される。この結果、ボンディング
パッド4とメタルパッド7とは熱圧着されたボンディン
グボール16によって電気的に短絡されるのである。ボ
ンディングワイヤ6の他端はパッケージの外部端子に接
続される。After the test of the semiconductor chip is completed, wire bonding is performed, and the bonding pad 4 and the metal pad 7 are electrically connected. That is, wire bonding is performed to obtain electrical connection between the conductor pattern 1 and an external ground or circuit via an external terminal (not shown) of the package. As described above, for example, the tip of the bonding wire 6 made of gold is a bonding ball 16, and the bonding ball 16 is bonded to the bonding pad 4 including the metal pad 7 by a thermocompression bonding method such as a ball bonding method. As a result, the bonding pad 4 and the metal pad 7 are electrically short-circuited by the bonding ball 16 which is thermocompression-bonded. The other end of the bonding wire 6 is connected to an external terminal of the package.
【0011】このような半導体チップに対するワイヤボ
ンディングが行なわれた後、パッケージングが行なわれ
る。ユーザがこのようなパッケージングされた製品とし
ての半導体装置を使用する場合においては、上記のパッ
ケージの外部端子がアース接続され、これによりメタル
パッド7及びボンディングパッド4を含む導体パターン
1の電位はアース電位に等しくなる。よって、電圧Vdd
が他の外部端子(図示せず)を介して抵抗12に印加さ
れても、インバータ13の入力はアース電位、すなわち
低レベルであるので、インバータ13からテスト回路5
への出力レベルは高レベルとなる。これにより、テスト
回路5は不活性状態となり、ユーザが半導体装置を使用
する状態ではテスト回路5が動作することはない。After wire bonding to such a semiconductor chip is performed, packaging is performed. When the user uses the semiconductor device as such a packaged product, the external terminals of the package are grounded, whereby the potential of the conductor pattern 1 including the metal pad 7 and the bonding pad 4 is grounded. It is equal to the potential. Therefore, the voltage Vdd
Is applied to the resistor 12 via another external terminal (not shown), the input of the inverter 13 is at the ground potential, that is, low level.
Output level is high. As a result, the test circuit 5 becomes inactive, and the test circuit 5 does not operate when the user uses the semiconductor device.
【0012】なお、上記した実施例においては、テスト
回路をワイヤボンディング後には活性状態から動作しな
い不活性状態に変化させているが、単に動作機能を変更
させるだけでも良い。すなわち、例えば、テスト回路の
全ての動作を禁止させるのではなく、一部の動作はワイ
ヤボンディング後も機能するようにすることもできる。
また、テスト回路でなく、他の回路についても回路機能
を変更させたい場合に有効である。In the above-described embodiment, the test circuit is changed from the active state to the inactive state in which the test circuit does not operate after the wire bonding. However, the operation function may be simply changed. That is, for example, instead of prohibiting all the operations of the test circuit, some of the operations may be performed after wire bonding.
It is also effective when it is desired to change the circuit function of not only the test circuit but also other circuits.
【0013】更に、上記した実施例においては、ボンデ
ィングパッド4に囲まれるようにメタルパッド7が形成
されているが、ワイヤボンディングの際にボンディング
ボール16でボンディングパッド4とメタルパッド7と
を短絡できればそれらボンディングパッド4及びメタル
パッド7はどのような形状のパターンであっても良い。
例えば、メタルパッド7に囲まれるようにボンディング
パッド4が形成されても良し、或いは矩形状のランドが
並置されたような形状であっても良い。また、ワイヤボ
ンディングによって短絡されるパッドパターンは2つに
限らず、3つ以上のパッドパターンでも良い。Further, in the above embodiment, the metal pad 7 is formed so as to be surrounded by the bonding pad 4. However, if the bonding pad 4 and the metal pad 7 can be short-circuited by the bonding ball 16 during wire bonding. The bonding pad 4 and the metal pad 7 may have any shape pattern.
For example, the bonding pads 4 may be formed so as to be surrounded by the metal pads 7, or the bonding pads 4 may have a shape in which rectangular lands are juxtaposed. Further, the number of pad patterns short-circuited by wire bonding is not limited to two, and three or more pad patterns may be used.
【0014】[0014]
【発明の効果】以上の如く、本発明によれば、製造コス
トをほとんど増加させることなく、特定の回路機能を変
更させることができる。As described above, according to the present invention, a specific circuit function can be changed with almost no increase in manufacturing cost.
【図1】本発明の実施例を示す図である。FIG. 1 is a diagram showing an embodiment of the present invention.
1 導体パターン 2 チップ 3 プローブ用パッド 4 ボンディングパッド 5 テスト回路 6 ボンディングワイヤ 7 メタルパッド 8 リードパターン 11 レベル検出回路 DESCRIPTION OF SYMBOLS 1 Conductor pattern 2 Chip 3 Probe pad 4 Bonding pad 5 Test circuit 6 Bonding wire 7 Metal pad 8 Lead pattern 11 Level detection circuit
Claims (6)
されるようにチップ上に隣接形成された少なくとも2つ
のパッドパターンと、 前記少なくとも2つのパッドパターン間の短絡を検知す
る検知手段と、 前記検知手段による短絡の検知に応じて動作機能を変更
する回路と、を備えたことを特徴とする半導体装置。1. At least two pad patterns formed adjacently on a chip so as to be electrically short-circuited by wire bonding, detecting means for detecting a short circuit between the at least two pad patterns, and the detecting means A circuit for changing an operation function in response to detection of a short circuit.
一方はアース電位となるべき共通ラインの一部であり、
前記2つのパッドパターンの他方は前記検知手段の入力
に連結されていることを特徴とする請求項1記載の半導
体装置。2. One of the at least two pad patterns is a part of a common line to be at a ground potential,
2. The semiconductor device according to claim 1, wherein the other of said two pad patterns is connected to an input of said detecting means.
された環状に形成され、その環状の内部に前記他方のパ
ッドパターンが位置し、前記一方のパッドパターンの環
状切断部を介して前記他方のパッドパターンに連結した
リードパターンが前記一方のパッドパターンの外部に伸
張していることを特徴とする請求項2記載の半導体装
置。3. The one pad pattern is formed in a partially cut annular shape, and the other pad pattern is located inside the annular shape, and the other pad pattern is positioned through an annular cut portion of the one pad pattern. 3. The semiconductor device according to claim 2, wherein a lead pattern connected to the pad pattern extends outside the one pad pattern.
半導体チップの動作を試験するためのテスト回路である
ことを特徴とする請求項1記載の半導体装置。4. The semiconductor device according to claim 1, wherein the circuit for changing the operation function is a test circuit for testing an operation of a semiconductor chip in the device.
ィングワイヤの先端は前記少なくとも2つのパッドパタ
ーンを覆う程度のボール状になっていることを特徴とす
る請求項1記載の半導体装置。5. The semiconductor device according to claim 1, wherein the tip of the bonding wire for the wire bonding has a ball shape enough to cover the at least two pad patterns.
ーンを隣接形成し、前記少なくとも2つのパッドパター
ンをボンディングワイヤにより電気的に短絡するワイヤ
ボンディングを行なうことを特徴とする半導体装置の製
造方法。6. A method of manufacturing a semiconductor device, comprising: forming at least two pad patterns adjacent to each other on a chip; and performing wire bonding for electrically short-circuiting the at least two pad patterns with bonding wires.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9025014A JPH10223679A (en) | 1997-02-07 | 1997-02-07 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9025014A JPH10223679A (en) | 1997-02-07 | 1997-02-07 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH10223679A true JPH10223679A (en) | 1998-08-21 |
Family
ID=12154070
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9025014A Pending JPH10223679A (en) | 1997-02-07 | 1997-02-07 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH10223679A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002313847A (en) * | 2001-03-30 | 2002-10-25 | Samsung Electronics Co Ltd | Chip-on-film package having test pad for electrical characteristic evaluation and method for forming the same |
CN103000601A (en) * | 2011-09-12 | 2013-03-27 | 瑞萨电子株式会社 | Semiconductor chip |
EP3285294A1 (en) * | 2016-08-17 | 2018-02-21 | EM Microelectronic-Marin SA | Integrated circuit die having a split solder pad |
-
1997
- 1997-02-07 JP JP9025014A patent/JPH10223679A/en active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002313847A (en) * | 2001-03-30 | 2002-10-25 | Samsung Electronics Co Ltd | Chip-on-film package having test pad for electrical characteristic evaluation and method for forming the same |
JP4611600B2 (en) * | 2001-03-30 | 2011-01-12 | 三星電子株式会社 | Chip-on-film package having test pads for electrical property evaluation and chip-on-film package forming method |
CN103000601A (en) * | 2011-09-12 | 2013-03-27 | 瑞萨电子株式会社 | Semiconductor chip |
JP2013062289A (en) * | 2011-09-12 | 2013-04-04 | Renesas Electronics Corp | Semiconductor chip |
EP3285294A1 (en) * | 2016-08-17 | 2018-02-21 | EM Microelectronic-Marin SA | Integrated circuit die having a split solder pad |
US10096561B2 (en) | 2016-08-17 | 2018-10-09 | Em Microelectronic-Marin Sa | Integrated circuit die having a split solder pad |
US10192798B2 (en) | 2016-08-17 | 2019-01-29 | Em Microelectronic-Marin Sa | Integrated circuit die having a split solder pad |
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