JPH10228445A - Ring bus input-output controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the delay of data transfer between processor nodes to a minimum by sending a receiving packet to a bypass FIFO memory until receiving packets in a target FIFO are all taken out when the target FIFO memory of a transfer request destination processor node is filled with receiving packets. SOLUTION: When a transfer request destination processor node address in a receiving packet does not coincide with addresses that are inherently set to each processor node or when a receiving packet exists in a target FIFO memory 29, the receiving packet is stored in a bypass FIFO memory 30 that temporarily performs buffering of a packet that is transferred to a processor node 20 on the next stage. That is, even though the receiving packet coincides with the addresses that are inherently set to processor nodes, when a receiving packet that precedes the memory 29, exists the receiving packet circulates on a ring bus until the memory 29 becomes empty.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for improving the operation performance of a so-called multiprocessor computer system in which processing to be operated is distributed to a plurality of CPUs and parallel processing is executed. More specifically, the present invention relates to speeding up data transfer of a ring bus input / output control device that controls data transfer between CPUs connected in a ring.

[0002]

2. Description of the Related Art Conventionally, a computer system having a multiprocessor configuration has been proposed as one of the promising solutions for overcoming the computational performance limit of a single CPU. In a computer system with a multiprocessor configuration, each single CP
The data communication performance between U has a great influence on the operation performance of the entire computer. That is, how to arrange and connect the individual CPUs and main memories is an important issue. One of the typical approaches is a method of arranging and connecting a plurality of CPUs and main memories on a single bus.
In this bus-connected multiprocessor computer system,
Due to the electrical limitations inherent in a single bus, the number of CPUs that can use the bus at the same time is limited to one, and there is an upper limit on the connection distance and the number of connectable CPUs, and the performance improvement is not linear with respect to the number of CPUs There is a feature. In practice, it has been pointed out that in this type of multiprocessor computer system, about 4 to 32 CPUs are the upper limit value of the number of connectable CPUs. On the other hand, a multiprocessor computer system in which CPUs are circularly connected by a ring bus input / output control device has a feature that a larger number of CPUs can be connected than a multiprocessor computer system essentially configured with a bus connection. In addition, since data can be transferred simultaneously on a plurality of transmission paths, there is a feature that the data transfer performance is relatively easily improved. Several ring bus input / output control devices for configuring this type of conventional computer system have been proposed. QuickRing (Quu) manufactured and sold by National Semiconductor
IckRing is a registered trademark of Apple Computer Inc.) Controller LSI, QR0001 is one of them. FIG. 7 shows the document number QR OPB94 (19
FIG. 6 is an internal block diagram of the controller LSI, QR0001 of National Semiconductor Co., Ltd., published on page 22, National Semiconductor Japan Co., Ltd., April 22, 1994, in which the names of the respective blocks are replaced with Japanese. In FIG. 7, reference numeral 1 denotes a ring bus input / output control device formed as an LSI, reference numeral 2 denotes a receiver to which a packet from a preceding processor node is input, and reference numeral 3 denotes a stable transfer clock based on a clock signal input from the receiver. PLL (Phase Lock Loop)
The circuit 4 is an upstream port for analyzing the packet and determining the destination of the packet, and the bypass FI 5 for temporarily holding the packet to be issued to the next processor node.
FO (First in First out) memory, 6 is a downstream port for selecting a packet to be transmitted to the next-stage processor node, 7 is a driver for transmitting a packet to the next-stage processor node, and 8 is a buffer for temporarily holding received packets. Target FIFO memory, 9
Is a receive port for taking out a received packet from the target FIFO memory 8 and sending it out onto the internal local bus.
Reference numeral 0 denotes a transmit port for converting the transfer data transmitted from the internal local bus into packets, and reference numeral 11 denotes a source FIFO memory for temporarily storing a transmission packet to be transmitted to the next stage.

Next, the operation will be described. The controller LSI, Q which is a conventional ring bus input / output control device
R0001 specifies the maximum packet size,
The packet is composed of head data and transfer data. The head data includes a transfer request destination processor node address and transfer request processor node address information. A packet input from the internal local bus is generated by the transmit port 10 and temporarily stored in the source FIFO memory 11. If there is no packet to be transmitted in the bypass FIFO memory 5,
The downstream port 6 transmits a transmission packet temporarily stored in the source FIFO memory 11 to the next processor node via the driver 7.
On the other hand, the received packet is synchronized with the transfer clock by the PLL circuit 3 via the receiver 2 and is taken into the ring bus input / output control device 1. That is, the controller LSI, QR,
When a ring bus is configured using 0001, all the controllers LSI and QR0001 are controlled by a single clock. Upstream port 4
The head data of the received packet is analyzed to check the transfer request destination processor node address. If the processor node address unique to the ring bus input / output control device 1 does not match, the received packet is sent to the bypass FIFO memory 5. The reception packet temporarily stored in the bypass FIFO memory 5 is selected as a transmission packet from the source FIFO memory 11 by the downstream port 6, and then transmitted as a transmission packet from the driver 7 to the next processor node. You. On the other hand, the upstream port 4 analyzes the head data of the received packet, examines the transfer request destination processor node address, and if it matches the processor node address unique to the ring bus input / output control device 1, the received packet is targeted. The data is sent to the FIFO memory 8 and sent to the internal local bus via the receive port 9. Generally, in the ring bus input / output control device, there is a problem that the performance is reduced due to blocking when there is no free space in the target FIFO memory 8 and the bypass FIFO memory 5. A controller LSI which is a conventional ring bus input / output control device 1,
QR0001 is a means for avoiding packet destruction when there is no free area in the target FIFO memory 8.
The resource reservation method is adopted. That is, before issuing a packet containing transfer data, a packet called a voucher is sent to the transfer request destination processor node, and if there is not enough free space in the target FIFO memory 8 of the transfer request destination, the voucher packet is transferred as it is. Return to the requesting processor node via the ring bus. in this case,
After a certain time has elapsed, the ring bus input / output control device 1 of the transfer requesting processor node issues a voucher packet again in the same manner. Target F of transfer request destination
If there is sufficient space in the IFO memory 8, a packet called a ticket is sent back to the transfer requesting processor node via the ring bus. Thereafter, the transfer requesting processor node transmits the transmission packet containing the transfer data from the source FIFO memory 11 to the next processor node from the driver 7 for the first time, and the transmitted packet is
After sequentially propagating through the processor nodes on the way, they are stored in an area previously secured in the target FIFO memory 8 of the transfer request destination processor node. On the other hand, as means for avoiding packet destruction when there is not enough free space in the bypass FIFO memory 5, a controller LSI, QR0001 which is a conventional ring bus input / output control device 1 is used.
When the free area of the bypass FIFO memory 5 has no free area for one packet, the source FIFO memory 11
Has a means for controlling transmission of a packet from the server to wait. That is, even if a received packet arrives at the bypass FIFO memory 5 while a packet from the source FIFO memory 11 is being transmitted, the received packet is stored in the bypass FIFO memory 5 because there is a free space in the bypass FIFO memory 5.
Since the packet length is specified, when the packet transmission from the source FIFO memory 11 is completed, the entire area of the bypass FIFO memory 5 may be filled with the received packets. At the next point in time, when a further packet arrives, the controller LSI, QR0001, which is the conventional ring bus input / output control device 1, controls all the processor nodes in the ring bus input / output control device 1 by a single clock. Since the timing is synchronized, writing and reading of the received packet to and from the bypass FIFO memory 5 are executed at the same timing, and no packet destruction occurs in the bypass FIFO memory 5.

[0004] Also, SCI (Scalable Coher) proposed in IEEE Standard 1596-1992.
ent Interface) is one of the conventional ring bus input / output control devices. FIG. 8 shows document numbers 1-55.
937-222-2, document name IEEE STANDAR
D FOR SCALEABLE COHERENTIN
TERFACE (SCI), (IEEE-Std-15)
FIG. 96 is a block diagram showing an example of a configuration of SCI, described in section 1.4.3 (page 17), in which the name of each block is replaced with Japanese. FIG.
, 12 is a ring bus input / output device, 13 is an address decoder for determining the address of a transfer request destination processor node in the head data of a received packet, and 14 is a bypass for temporarily holding a packet issued to the next processor node. FIFO memory, 15 is an output multiplexer for selecting a packet to be sent to the next processor node, 16 is a target FIFO memory for temporarily storing received response packets and request packets,
Reference numeral 17 denotes an input queue for judging the priority of processing of the received packet and buffering it, 18 an output queue for temporarily storing transfer data to be output,
Reference numeral 19 denotes a source FIFO memory for temporarily storing a response packet and a request packet to be output to the ring bus.

Next, the operation will be described. In one configuration example of the SCI that is the conventional ring bus input / output control device 12,
The maximum packet size is specified, and the packet is composed of head data and transfer data. The head data includes a transfer request destination processor node address and a transfer request processor node address information. Transfer data input from the internal local bus is stored in the output queue 18 and, after packet generation, the source FIFO
It is temporarily stored in the O memory 19 as a request packet. If there is no packet to be sent to the bypass FIFO memory 14, the output multiplexer 15 sends the request packet temporarily stored in the source FIFO memory 19 to the next processor node. On the other hand, the received packet is taken into the ring bus input / output control device 12 via the address decoder 13. The address decoder 13 analyzes the head data of the request packet, checks the transfer request destination processor node address, and if the address does not match the processor node address unique to the ring bus input / output control device 12, sends the request to the bypass FIFO memory 14. Send a packet.
The request packet temporarily stored in the bypass FIFO memory 14 is output by the output multiplexer 15.
After being selected as a transmission packet from the source FIFO memory 19, it is transmitted to the next processor node. on the other hand,
The address decoder 13 analyzes the head data of the request packet, checks the transfer request destination processor node address, and if the address matches the processor node address unique to the ring bus input / output control device 12, the request packet is transferred to the target FIFO memory 16 To the input queue 17. The ring bus input / output controller 12 analyzes the input queue 17. If it is a write request, it sends write data attached to the packet to the internal local bus, generates an echo packet indicating completion of writing, and inputs it into the source FIFO memory 19. If the request is a read request, an echo packet for notifying the transfer requesting processor node that the read request has been recognized is generated and the source FI
The data is input to the FO memory 19 and is transferred to the processor node that has requested the transfer. After that, the ring bus input / output control device 12 in the read request destination processor node reads the transfer data from the internal local bus and puts it into the output queue 18. Next, after generating a response packet including read data, the response packet is input to the source FIFO memory 19. The response packets input to the source FIFO memory 19 are sequentially sent out on the ring bus. Further, in the case of a read request, after receiving an echo packet for the response packet, the response packet is deleted from the output queue 18. The SCI ring bus I / O controller 12 which is a conventional ring bus I / O controller includes a target FIFO memory 16
In order to avoid packet destruction when there is no free area, a retry method is adopted. That is, if there is not enough space in the target FIFO memory 16 or the input queue 17 at the time of receiving the packet,
A retry packet is generated, and the retry packet is returned to the transfer requesting processor node. Upon receiving the retry packet, the transfer requesting processor node issues an output queue 1 to issue a transfer request packet again.
Then, a packet is generated again from the transfer data held in No. 8. Target FIFO of the transfer request destination processor node
When a sufficient space is created in the memory 16 or the input queue 17, an echo packet indicating a normal end is returned. Therefore, the transfer requesting processor node deletes the transfer data held in the output queue 18 at this time. be able to. On the other hand, as means for avoiding packet destruction when there is not enough free space in the bypass FIFO memory 14, the SCI ring bus I / O controller 12, which is a conventional ring bus I / O controller, uses a conventional ring bus I / O controller. QuickRing controller L which is a control device
Similar to SI and QR0001, when the free area of the bypass FIFO memory 14 has no free area for one packet, the bypass FIFO memory 14 has means for controlling so that the packet transmission from the source FIFO memory 19 is made to wait. That is, even if a received packet arrives at the bypass FIFO memory 14 while a packet is being transmitted from the source FIFO memory 19, the received packet is stored in the bypass FIFO memory 14 since there is a free area in the bypass FIFO memory 14. Since the packet length is specified, when the packet transmission from the source FIFO memory 19 is completed, the entire area of the bypass FIFO memory 14 may be filled with the received packets. At the next point, if further packets arrive, the conventional ring bus I / O controller SC
Since the control timing of the ring bus input / output control units 12 of all I is synchronized by the transfer clocks having substantially the same frequency in the ring bus input / output control units 12 of all the processor nodes, the reception to the bypass FIFO memory 14 is performed. Writing and reading of packets are executed at substantially the same timing. Further, an elastic buffer in the address decoder 13 adjusts (expands and compresses) idle time between packets so as to absorb the difference in frequency. As a result, packet destruction in the bypass FIFO memory 14 does not occur.

[0006]

SUMMARY OF THE INVENTION A QuickRing controller LS which is a conventional ring bus input / output control device
Since I and QR0001 employ a resource reservation system, a packet called a voucher is sent to the transfer request destination processor node, and data transfer is blocked until the ticket is returned. Therefore, target F
Even if there is an empty area in the IFO memory, data transfer cannot be started unless packets are always turned for one round of the ring bus, and there has been a problem that delay in data transfer between processor nodes increases.

[0007] Further, since one configuration example of the SCI as a conventional ring bus input / output control device employs a retry method, when a retry packet is received, the transfer data held in the output queue is transferred. Read again,
It is necessary to generate a transfer request packet and write it to the source FIFO memory. In this case as well, there is a problem that a delay in data transfer between the processor nodes increases.

Further, a QuickRing controller LSI, QR00, which is a conventional ring bus input / output controller,
01 and one configuration example of the SCI, it is necessary to have a bypass FIFO memory having a depth of at least the maximum packet length, which increases the cost due to having an expensive large-capacity FIFO memory, and the transfer data due to the short packet length. Has to be divided, and by transferring them a plurality of times, there is a problem that the total throughput performance is reduced.

The present invention has been made in order to solve such a problem, and an object of the present invention is to provide a ring bus input / output control device which minimizes a delay in data transfer between processor nodes.

Another object of the present invention is to provide a ring bus input / output control device capable of dramatically reducing the capacity of the bypass FIFO memory and increasing the maximum packet length.

[0011]

In the ring bus input / output control device according to the first aspect of the present invention, when the target FIFO memory of the transfer request destination processor node is full of received packets, all the received packets of the target FIFO are taken out. And means for transmitting all subsequent received packets to said bypass FIFO memory.

A ring bus input / output control device according to a second aspect of the present invention includes:
It has a retry packet. Further, it has a rewritable source FIFO memory. Further, when a retry packet is received at the input port, a means for reading out a write request packet from the source FIFO memory again and sending it to the transfer request destination processor node again is provided. Also,
When it is determined that a received packet is present in the target FIFO memory, reject means is provided for converting the write request head data transferred from the input port into a retry packet and sending the retry packet to the bypass FIFO memory.

The ring bus input / output control device according to the third aspect of the present invention includes:
It has a retry packet. Further, it has a rewritable source FIFO memory. Further, when a retry packet is received at the input port, a means for reading out a write request packet from the source FIFO memory again and sending it to the transfer request destination processor node again is provided. Also,
There is a reject means for sending a retry packet to the bypass FIFO memory. It has a target reject flag that holds information indicating that the received packet has been rejected. Further, the apparatus has means for setting a target reject flag corresponding to a requesting processor node of a rejected packet when rejection occurs. In addition, if the target reject flag corresponding to the requesting processor node is not set in the received packet, a means for rejecting this packet again is provided. Also, in the received packet, the corresponding target reject flag of the requesting processor node is set and the target
When there is no received packet in the O memory, a means is provided for taking the received packet into the target FIFO memory. Further, there is provided means for resetting a corresponding target reject flag.

The ring bus input / output control device according to the fourth aspect of the present invention includes:
It has a retry packet. Further, it has a rewritable source FIFO memory. Further, when a retry packet is received at the input port, a means for reading out a write request packet from the source FIFO memory again and sending it to the transfer request destination processor node again is provided. Also,
It has means for monitoring whether or not the source FIFO memory is sending outgoing packets on the ring bus. When it is determined that the source FIFO memory is transmitting a transmission packet on the ring bus, the write request head data transferred from the input port is converted into a retry packet, and the retry packet is transmitted to the bypass FIFO memory. It has a reject means.

Further, the ring bus input / output control device according to the fifth aspect of the present invention includes a
It has a retry packet. Further, it has a rewritable source FIFO memory. Further, when a retry packet is received at the input port, a means for reading out a write request packet from the source FIFO memory again and sending it to the transfer request destination processor node again is provided. Also,
It has means for monitoring whether or not the source FIFO memory is sending outgoing packets on the ring bus. When it is determined that the source FIFO memory is transmitting a transmission packet on the ring bus, the write request head data transferred from the input port is converted into a retry packet, and the retry packet is transmitted to the bypass FIFO memory. It has a reject means. In addition, it has a bypass reject flag that holds information indicating that the received packet has been rejected. Further, there is provided means for setting a bypass reject flag corresponding to the transfer requesting processor node of the rejected packet when rejection occurs. Also, if the corresponding bypass reject flag of the transfer requesting processor node is not set in the received packet,
There is means for rejecting this packet again. If the corresponding bypass reject flag of the transfer requesting processor node is set in the received packet and the output from the source FIFO memory to the ring bus is not made, the received packet is transferred to the bypass FIFO memory. And means for resetting the corresponding bypass reject flag.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION

First Embodiment FIG. 1 is a block diagram showing a first embodiment of the present invention. In FIG. 1, reference numeral 20 denotes a processor node, reference numeral 21 denotes a ring bus connecting processor nodes 20, and reference numeral 22 denotes a CP.
U and 23 are main memories storing transfer data, 24
Is an internal local bus for transferring data in the processor node, 25 is a ring bus input / output control device, 26 is a packet transmitted on the ring bus 21, takes in the address of the transfer request destination processor node address in the head data of the received packet. Input port for discriminating the ring bus 27
An output port 28 for transmitting a packet onto the CPU 1 is connected to the CPU 22 and the main memory 23 via the internal local bus 24.
A channel controller for controlling data transfer between the controller and the ring bus I / O controller 25; 29, a target FIFO memory for temporarily storing received packets; and 30, a temporary memory for bypass packets issued to the next processor node. A FIFO FIFO memory 31 for storing a source FIFO for temporarily storing a transmission packet to be transmitted to the next stage
A memory 32 is an output multiplexer for selecting a packet to be sent to the next processor node. Similarly to the conventional device, the transfer data transmitted on the ring bus 21 has a predetermined packet format system. As shown in FIG. 2, the format system includes a transfer request destination processor node address, Transfer request source processor node address, transfer request destination internal local bus address,
The packet includes, as elements, a transfer request source internal local bus address and a packet including head data including information on a transfer request data length and write data. Further, the maximum packet length is defined in the packet format system as in the conventional device.

The operation of the ring bus input / output controller 25 configured as described above is as follows. First, a process until a transmission packet is transmitted from the transfer requesting processor node 20 to the ring bus 21 will be described.
When a data transfer request is issued to the CPU 22 of the transfer request source processor node 20, the CPU 22 checks the use right flag of the ring bus input / output control device 25. The transfer request source internal local bus address, the transfer request data length, and the transfer start command are transferred to the channel controller 28. After setting the use right flag of the ring bus input / output control device 25 to the unusable state, the channel controller 28 sets the transfer request destination processor node address, transfer request source processor node address, transfer request destination internal local bus address, transfer request The head data including the information of the original internal local bus address and the transfer request data length is generated, the transfer data is further read from the main memory 23, and transferred to the source FIFO memory 31 as a transmission packet shown in FIG. When the transmission packet is stored in the source FIFO memory 31 and the bypass FIFO memory 30 is empty, the transmission packet is output to the output multiplexer 32 and the output port 27.
Is transmitted to the ring bus 21 via the bus, and the packet is transmitted to the processor node 20 at the next stage. At the point when the transmission packet is stored in the source FIFO memory 31, the bypass FIFO memory 30
If the received packet received from 0 is being transmitted or if the received packet received from the preceding processor node 20 is stored, all the packets in the bypass FIFO memory 30 are transmitted, and the bypass FIFO memory 30 is transmitted.
After the memory 30 is emptied, the source FIFO memory 31
The transmission packet in the middle is sent to the ring bus 21 via the output multiplexer 32 and the output port 27, and sent to the processor node 20 in the next stage. Also, source FIFO
The transmission packet stored in the memory 31 is transferred to the ring bus 2
When a received packet arrives at the bypass FIFO memory 30 during transmission to the source FIFO memory 30, the received packet is stored in the bypass FIFO memory 30, and then stored in the source FIFO memory 3.
When the transmission packet stored in 1 has been transmitted,
The received packets stored in the bypass FIFO memory 30 are transmitted to the ring bus 21. Bypass FIFO
The memory 30 has a capacity equal to or larger than the maximum packet length as in the conventional device, and all the ring bus input / output control devices 25 on the ring bus 21 perform a single transfer in the same manner as in the conventional device. Since an elastic buffer which is controlled by a clock or operates with a clock having a recent frequency and inserts / deletes an idle packet in the input port 26 absorbs a frequency error, No packet destruction occurs due to missing received packets. Next, an operation when a received packet is received via the ring bus 21 will be described. When the received packet arrives at the input port 26 from the preceding processor node 20 via the ring bus 21, the next-stage processor node 20 determines the transfer request destination processor node address in the received packet, and the target FIFO memory 29. Or bypass FIFO memory 3
Distribute to 0. If the transfer request destination processor node address in the received packet matches the address set uniquely for each processor node, and the received packet does not exist in the target FIFO memory 29, the received packet is stored in the target FIFO memory 29. Is done.
Since the target FIFO memory 29 has a capacity equal to or larger than the maximum packet length, one received packet can be entirely taken into the target FIFO memory 29. After that, write data is generated from the received packet extracted from the target FIFO memory 29 and transmitted to the internal local bus. As a result, the transfer data is written to the main memory 23. Thereafter, a one-word length response packet including the transfer completion information shown in FIG. 3 is returned to the transfer requesting processor node 20, and the transfer requesting processor node 20 receives and decodes the response packet, thereby obtaining the source FIFO. Memory 3
At the same time as discarding the transmission packet in 1, it notifies the CPU 22 of the transfer requesting processor node that a series of transfer requests has been completed, and returns the use right flag of the input / output control device to the usable state. When a next transfer request is made, the CPU 22 issues a transfer request to the ring bus input / output control device again in a series of procedures. When the transfer request destination processor node address in the received packet does not match the address set uniquely for each processor node, or when the received packet exists in the target FIFO memory 29, the transfer to the next processor node 20 is performed. The received packet is stored in the bypass FIFO memory 30 for temporarily buffering the packet to be transmitted. In other words, if a received packet preceding the target FIFO memory 29 exists even though the received packet matches an address set uniquely for the processor node, the received packet is stored until the target FIFO memory 29 becomes empty. Orbit around the ring bus.

Embodiment 2 FIG. 1 shows Embodiment 2 in the same manner as Embodiment 1 of the present invention.
FIG. Similarly to the conventional device, the transfer data transmitted on the ring bus 21 has a predetermined packet format system. The format system includes, as shown in FIG. 2, information on a transfer request destination processor node address, a transfer request source processor node address, a transfer request destination internal local bus address, a transfer request source internal local bus address, and a transfer request data length. The packet includes, as an element, a packet including head data and write data. Further, as an element of the packet format system, a one-word-length retry packet shown in FIG. 4 is included. Further, the maximum packet length is defined in the packet format system as in the conventional device. Further, the source FIFO memory 31 according to the second embodiment of the present invention
FO memory. When a retry packet is received at the input port 21, the source FIFO memory 31
There is provided a means for reading out a write request packet and sending it to the transfer request destination processor node 20.

The above-described ring bus input / output control device operates as follows. First, the transfer requesting processor node 20
The process from transmission of the transmission packet to the ring bus 21 is the same as that of the ring bus input / output control device 25 according to the first embodiment of the present invention. next,
An operation when a received packet is received via the ring bus 21 will be described. When the received packet arrives at the input port 26 from the preceding processor node 20 via the ring bus 21, the next-stage processor node 20 determines the transfer request destination processor node address in the received packet, and the target FIFO memory 29. Alternatively, the data is distributed to the bypass FIFO memory 30. If the transfer request destination processor node address in the received packet matches the address set uniquely for each processor node, and there is no received packet in target FIFO memory 29, the ring according to the first embodiment of the present invention is used. The same operation as that of the bus input / output control device 25 is performed. If the transfer request destination processor node address in the received packet does not match the address set uniquely for each processor node, a bypass FIFO memory for temporarily buffering the packet transferred to the next processor node 20 The received packet is stored in 30. Although the received packet matches the address set uniquely for the processor node, the target FIFO
If there is a preceding received packet in the memory 29,
The write request head data in the received packet is converted into the retry packet shown in FIG. 4, the transfer data part in the received packet is discarded, and the bypass FIFO memory 3
Send a retry packet to 0. This operation is called reject. The retry packet stored in the bypass FIFO memory 30 returns to the transfer requesting processor node 20 via the ring bus 21. Upon receiving the retry packet, the transfer requesting processor node 20 performs an operation of retransmitting the rejected packet.
That is, since the source FIFO memory 31 is a readable FIFO memory, when a retry packet is received at the input port 26, the write request packet is read from the source FIFO memory 31 again and sent to the read request processor node 20. . Thereafter, the operation of rejecting and retransmitting the packet is repeated until the target FIFO memory 29 of the transfer request destination processor node 20 becomes empty.

Third Embodiment FIG. 5 is a block diagram showing a third embodiment of the present invention. In FIG. 5, reference numerals 20 to 32 are the same as those in the first embodiment of the present invention. A target reject flag 33 holds information indicating that the received packet has been rejected. Similarly to the conventional device, the transfer data transmitted on the ring bus has a predetermined packet format system. The format system includes, as shown in FIG. 2, information on a transfer request destination processor node address, a transfer request source processor node address, a transfer request destination internal local bus address, a transfer request source internal local bus address, and a transfer request data length. The packet includes, as an element, a packet including head data and write data. Further, as shown in FIG. 4, a retry packet having a length of one word is included as an element of the packet format system. Further, the maximum packet length is defined in the packet format system as in the conventional device. The source FIFO memory 31 according to the third embodiment of the present invention is a rewritable FIFO memory. When a retry packet is received at the input port 26, a means is provided for reading the write request packet from the source FIFO memory 31 again and sending it to the transfer request destination processor node 20.

The above-described ring bus input / output control device 25 operates as follows. First, in the process until the transmission packet is transmitted from the transfer requesting processor node 20 to the ring bus 21, the same operation as that of the ring bus input / output control device 25 in the first embodiment of the present invention is performed. Next, with respect to the operation when a received packet is received via the ring bus 21, the received packet preceding the target FIFO memory 29 despite the fact that the received packet matches the address set uniquely for the processor node is described. Except for the case where there exists, the same operation as the ring bus input / output control device 25 according to the second embodiment of the present invention is performed. Although the received packet matches the address set uniquely for the processor node, the target F
When the preceding received packet exists in the IFO memory 29, a reject operation is performed in the same manner as in the ring bus input / output control device 25 according to the second embodiment of the present invention, and the transfer request source processor node 20 transmits the retry packet shown in FIG. Immediately after receiving the packet, the operation of retransmitting the rejected packet is performed. At this time, the ring bus input / output control device 25 according to the third embodiment of the present invention sets the target reject flag 33 corresponding to the transfer requesting processor node 20, and holds information indicating that the received packet has been rejected. . In the packets received thereafter, the transfer request destination processor node address indicated by the head data in the received packet matches the address set uniquely for the processor node, and the target reject flag 33 corresponding to the transfer request source processor node. Is set and the received packet does not exist in the target FIFO memory 29, the received packet is fetched into the target FIFO memory 29, and the corresponding target reject flag 33 is reset. Even when the received packet does not exist in the target FIFO memory 29 and the transfer request destination processor node address indicated by the head data in the received packet matches the address set uniquely for the processor node, the corresponding target rejection is performed. If the flag 33 is not set, the received packet is rejected, and the corresponding target reject flag 33 is set.
In this way, the retransmitted packet is
Until the packet is taken into the IFO memory 29, all newly received packets are rejected, prompting the transfer requesting processor node 20 to retransmit. Thereafter, each time the target FIFO memory 29 of the transfer request destination processor node 20 becomes empty, only the packet once rejected is sequentially digested.

Embodiment 4 FIG. 1 shows Embodiment 4 in the same manner as Embodiment 1 of the present invention.
FIG. Similarly to the conventional device, the transfer data transmitted on the ring bus 21 has a predetermined packet format system. The format system includes, as shown in FIG. 2, information on a transfer request destination processor node address, a transfer request source processor node address, a transfer request destination internal local bus address, a transfer request source internal local bus address, and a transfer request data length. The packet includes, as an element, a packet including head data and write data. Further, as shown in FIG. 4, a retry packet having a length of one word is included as an element of the packet format system. Further, the maximum packet length is defined in the packet format system as in the conventional device. Embodiment 4 of the present invention
Is a readable FIFO memory. When a retry packet is received at the input port 26, a means for reading out a write request packet from the source FIFO memory 31 again and sending it to the transfer request destination processor node 20 is provided.

The above-described ring bus input / output control device 25 operates as follows. First, in the process until the transmission packet is transmitted from the transfer requesting processor node 20 to the ring bus 21, the same operation as that of the ring bus input / output control device 25 in the first embodiment of the present invention is performed. Next, an operation when a received packet is received via the ring bus 21 will be described. When the received packet arrives at the input port 26 from the preceding processor node 20 via the ring bus 21, the next-stage processor node 20 determines the transfer request destination processor node address in the received packet, and the target FIFO memory 29.
Alternatively, the data is distributed to the bypass FIFO memory 30. If the transfer request destination processor node address in the received packet matches the address set uniquely for each processor node, any one of the first, second, and third embodiments of the present invention Operates in the same manner as the ring bus input / output control device 25 in FIG. When the transfer request destination processor node address in the received packet does not match the address set uniquely for each processor node, and the transmission packet in the source FIFO memory 31 is not being transmitted to the ring bus 21 , Bypass FI
The received packet is sent to the FO memory 30, and the ring bus 2
Send on 1. If the transfer request destination processor node address in the received packet does not match the address set uniquely for each processor node, and the transmission packet in the source FIFO memory 31 is being transmitted to the ring bus 21 The write request head data in the received packet is converted into a retry packet shown in FIG. 4, the transfer data portion in the received packet is discarded, and the retry packet is sent to the bypass FIFO memory 30. This operation is called reject. Bypass FIFO memory 3
The retry packet stored in 0 is returned to the transfer requesting processor node 20 via the ring bus 21 after all the transmission packets in the source FIFO memory 31 have been transmitted. Upon receiving the retry packet, the transfer requesting processor node 20 performs an operation of retransmitting the rejected packet. That is, the source FIFO
Since the memory 31 is a re-readable FIFO memory, when a retry packet is received at the input port 26, the write request packet is read from the source FIFO memory 31 again, and the transfer request destination processor node 20
To send to. Thereafter, the operation of rejecting and retransmitting the packet is repeated until the transmission packet is stored in the target FIFO memory 29 of the transfer request destination processor node 20.

Embodiment 5 FIG. 6 is a block diagram showing Embodiment 5 of the present invention. In the drawing, reference numerals 20 to 32 are the same as those in Embodiment 1 of the present invention. Reference numeral 34 denotes a bypass reject flag that holds information indicating that the received packet has been rejected. Similarly to the conventional device, the transfer data transmitted on the ring bus 21 has a predetermined packet format system. The format system includes, as shown in FIG. 2, information on a transfer request destination processor node address, a transfer request source processor node address, a transfer request destination internal local bus address, a transfer request source internal local bus address, and a transfer request data length. The packet includes, as an element, a packet including head data and write data. Further, as an element of the packet format system, a one-word-length retry packet shown in FIG. 4 is included. Further, the maximum packet length is defined in the packet format system as in the conventional device. Further, the source F according to the fifth embodiment of the present invention
The IFO memory 31 is a re-readable FIFO memory. When the retry packet is received by the input port 26, the write request packet is read from the source FIFO memory 31 again, and the transfer request destination processor node 2
0 is provided.

The above-described ring bus input / output control device 25 operates as follows. First, in the process until the transmission packet is transmitted from the transfer requesting processor node 20 to the ring bus 21, the same operation as that of the ring bus input / output control device 25 in the first embodiment of the present invention is performed. Next, an operation when a received packet is received via the ring bus 21 will be described. When the received packet arrives at the input port 26 from the preceding processor node 20 via the ring bus 21, the next-stage processor node 20 determines the transfer request destination processor node address in the received packet, and the target FIFO memory 29.
Alternatively, the data is distributed to the bypass FIFO memory 30. If the transfer request destination processor node address in the received packet matches the address set uniquely for each processor node, any one of the first, second, and third embodiments of the present invention Operates in the same manner as the ring bus input / output control device 25 in FIG. When the transfer request destination processor node address in the received packet does not match the address set uniquely for each processor node, and the transmission packet in the source FIFO memory 31 is not being transmitted to the ring bus 21 , Bypass FI
The received packet is sent to the FO memory 30, and the ring bus 2
Send on 1. If the transfer request destination processor node address in the received packet does not match the address set uniquely for each processor node, and the transmission packet in the source FIFO memory 31 is being transmitted to the ring bus 21 The reject operation is performed in the same manner as the ring bus input / output control device 25 according to the fourth embodiment of the present invention, and the transfer requesting processor node 20 immediately retransmits the rejected packet upon receiving the retry packet. . At this time, the ring bus input / output control device 25 according to the fifth embodiment of the present invention sets the bypass reject flag 34 corresponding to the transfer requesting processor node 20, and holds information indicating that the received packet has been rejected. . In the packet received thereafter, the transfer request destination processor node address indicated by the head data in the received packet does not match the address set uniquely for the processor node, and the bypass reject corresponding to the transfer request source processor node 20 is performed. Only when the flag 34 is set and the transmission packet is not being output from the source FIFO memory 31, the received packet is taken into the bypass FIFO memory 30, and the corresponding bypass reject flag 34 is reset. The transfer request destination processor node address indicated by the head data in the received packet does not match the address set uniquely for the processor node, and the source F
Even if the transmission packet is not being output from the IFO memory 31, if the corresponding bypass reject flag 34 is not set, the reception packet is rejected and the corresponding bypass reject flag 34 is set. In this way, the retransmitted packet is
Until fetched into the memory 29, all newly bypassed packets are rejected, prompting the transfer requesting processor node 20 to retransmit.

[0026]

According to the first, second, third, fourth and fifth aspects of the present invention, when there is no preceding received packet in the target FIFO memory 29, the conventional device Qui is used.
Since the data transfer to the transfer request destination processor node 20 is completed without waiting for the arrival of the ticket packet unlike the ckRing controller LSI, the target FIFO
There is an effect that the transfer delay to the O memory 29 is shortened.

According to the first aspect, the target F
When there is a preceding received packet in the IFO memory 29, the packet circulates on the ring bus 21 so that
In order to wait for the target FIFO memory 29 to become empty, there is an effect that the transfer delay to the target FIFO memory 29 is reduced as compared with the SCI embodiment which is a conventional device that generates packets again from the output queue 18. . Further, unlike the resource reservation method and the retry method of the conventional device, since the packet circulates on the ring bus 21, the transmission / detection of vouchers and tickets, and the hardware resources associated with the transmission / detection of the retry packet are not required. A ring bus input / output control device 25 can be provided.

According to the second and third aspects of the present invention, if a preceding packet exists in the target FIFO memory 29, the packet already generated from the source FIFO memory 31 of the transfer requesting processor node 20 is deleted. Since the packet is read again, there is an effect that the transfer delay to the target FIFO memory 29 is reduced as compared with the SCI embodiment which is a conventional device that regenerates the packet from the output queue 18.

According to the third aspect, the target F
When there is a preceding received packet in the IFO memory 29, a reject operation is performed. At this time, since the once rejected packet is preferentially taken into the target FIFO memory 29 by using the target reject flag 33, as a result, the target of the transfer request destination processor node 20 first starts from the old packet that issued the transfer request. It is possible to maintain the tendency to be taken into the FIFO memory 29.

According to the fourth and fifth aspects of the present invention, when a bypass packet is taken into the bypass FIFO memory 30 and a transmission packet in the source FIFO memory 31 is being transmitted, a 1-word retry packet is output. Convert and discard the transfer data. For this reason, in the conventional device, the bypass FIFO memory 30 requiring the capacity of the maximum packet word length was required, but the bypass FIFO memory 30 having the number of words equal to the number of processor nodes was used.
You just need to prepare. Therefore, it is possible to dramatically reduce the capacity of the bypass FIFO memory 30 as compared with the conventional device, and as a result, there is no need to prepare an expensive large-capacity FIFO memory, and the cost can be reduced. In addition, since the maximum packet length can be set longer than before, the need to divide transfer data is reduced, and the number of times to transfer the disassembled transfer data multiple times is reduced, improving the overall throughput performance. There is an effect of doing.

According to the fifth aspect of the present invention, when a bypass packet is taken into the bypass FIFO memory 30 and a transmission packet in the source FIFO memory 31 is being transmitted, a reject operation is performed. At this time, since the once rejected packet is preferentially loaded into the bypass FIFO memory 29 by using the bypass reject flag 34, as a result, the target of the transfer request destination processor node 20 first receives the oldest transfer request packet first. It is possible to maintain the tendency to be taken into the FIFO memory 29.

[Brief description of the drawings]

FIG. 1 is a diagram showing Embodiments 1, 2, and 4 of a ring bus input / output control device according to the present invention.

FIG. 2 is a diagram showing a format of a transmission / reception packet used in the first, second, third, fourth and fifth embodiments of the ring bus input / output control device according to the present invention; It is.

FIG. 3 is a diagram showing a format of a response packet used in the first, second, third, fourth and fifth embodiments of the ring bus input / output control device according to the present invention; .

FIG. 4 is a diagram showing a format of a retry packet used by the second, third, fourth and fifth embodiments of the ring bus input / output control device according to the present invention;

FIG. 5 is a diagram showing Embodiment 3 of a ring bus input / output control device according to the present invention.

FIG. 6 is a diagram showing Embodiment 5 of a ring bus input / output control device according to the present invention.

FIG. 7 shows the controller LSI, QR of National Semiconductor, which is a conventional ring bus input / output control device.
It is a figure which shows the internal block of 0001.

FIG. 8 shows a conventional ring bus I / O controller, ie, IEEE.
FIG. 3 is a diagram illustrating a configuration example of an SCI of E standard 1596-1992.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 ring bus input / output control device 2 receiver 3 PLL circuit 4 upstream port 5 bypass FIFO memory 6 downstream port 7 driver 8 target FIFO memory 9 receiver port 10 transmit port 11 source FIFO memory 12 ring bus input / output control device 13 address Decoder 14 Bypass FIFO memory 15 Output multiplexer 16 Target FIFO memory 17 Input queue 18 Output queue 19 Source FIFO memory 20 Processor node 21 Ring bus 22 CPU 23 Main memory 24 Internal local bus 25 Ring bus input / output control device 26 Input port 27 Output Port 28 Channel controller 29 Target FIFO memory 30 Bypass FIFO memory 31 Source FIFO memory 32 output multiplexer 33 target reject flag 34 bypass reject flag

Claims (5)

[Claims] 1. A ring bus input / output control device provided in a processor node for connecting a plurality of processor nodes having a CPU, a main memory, and an internal local bus in a ring shape, wherein the ring bus I / O control device is connected via the internal local bus. For write data issued by the CPU, a transfer request destination processor node address, a transfer request source processor node address, a transfer request destination internal local bus address,
Means for generating a packet which is a block of data to which the head data including the information of the transfer request source internal local bus address and the transfer request data length is added, and taking out write data from the packet and transferring it to the main memory A channel controller having means, an output port for transmitting the packet to be transmitted to the other processor nodes connected in a ring, and an input port for receiving the packet received from the other processor nodes connected in a ring. And a source FIFO (First in First) for temporarily storing the packet generated by the channel controller.
out) a memory; a target FIFO memory having a capacity equal to or greater than a maximum packet length for temporarily storing the packets received from the input port;
A bypass FIFO memory for temporarily storing the packet for transferring the packet received from the input port to another processor node, and determining the transfer request destination processor node address in the received packet to determine the target Means for distributing the data to a FIFO memory or the bypass FIFO memory;
An output multiplexer for selecting outputs of the O memory and the source FIFO memory; and a transfer when the packet transmitted from the processor node that is a transfer request source is taken out from the target FIFO memory of the processor node that is a transfer request destination. Means for returning a response packet containing transfer completion information to the processor node that is the request source; and means for suppressing issuance of the write data from the CPU to the channel controller until the response packet is received, Means for monitoring the presence / absence of the packet in the target FIFO memory; and, if it is determined that the packet exists in the target FIFO, the target FIFO
Means for transmitting all subsequent received packets to said bypass FIFO memory until all of said packets are retrieved by said channel controller. 2. The method according to claim 1, wherein the source FIFO memory is a rewritable FIFO memory, and the target FIFO memory is
When it is determined that there is a received packet in the O memory, the packet transferred from the input port is converted into a retransmission request packet, and a means for transmitting the retransmission request packet to the bypass FIFO memory (this operation is called rejection) And when the retransmission request packet is received at the input port, the packet is read from the source FIFO memory again, and the packet is transmitted to the processor node again. The ring bus input / output control device according to claim 1, wherein 3. The source FIFO memory is a rewritable FIFO memory, and the target FIFO memory is
Means for converting the packet transferred from the input port into a retransmission request packet and transmitting the retransmission request packet to the bypass FIFO memory (rejection of this operation) If the retransmission request packet is received at the input port, the source
O means for reading the held packet from the O memory and sending the packet to the processor node again, and a target reject flag for holding information indicating that the received packet has been rejected,
Means for setting the target rejection flag corresponding to the processor node that is the requester of the rejected packet when rejection occurs, and corresponding to the processor node that is the requester in the subsequently received packets. If the target reject flag is not set, the means for rejecting the packet again, and the target reject flag corresponding to the requesting processor node is set in the packet received thereafter. And when the received packet does not exist in the target FIFO memory, means for fetching the received packet into the target FIFO memory and resetting the corresponding target reject flag is provided. Ring bus output control apparatus according to claim 1, wherein. 4. The source FIFO memory is a rewritable FIFO memory, and the target FIFO memory is
Means for converting the packet transferred from the input port into a retransmission request packet and transmitting the retransmission request packet to the bypass FIFO memory (rejection of this operation) If the retransmission request packet is received at the input port, the source
Means for reading the held packet from the O memory and sending the packet to the processor node again; and determining whether or not the packet is being sent from the source FIFO memory to the one-to-one unidirectional transmission path. Monitoring means; and the one-to-one from the source FIFO memory.
If it is determined that the packet is being transmitted on the unidirectional transmission path, the packet transferred from the input port is converted into the retransmission request packet, and the
2. The ring bus input / output control device according to claim 1, further comprising means for sending said retransmission request packet to an IFO memory. 5. The source FIFO memory is a rewritable FIFO memory, and the target FIFO memory is
Means for converting the packet transferred from the input port into a retransmission request packet and transmitting the retransmission request packet to the bypass FIFO memory (rejection of this operation) If the retransmission request packet is received at the input port, the source
Means for reading the held packet from the O memory and sending the packet to the processor node again; and determining whether or not the packet is being sent from the source FIFO memory to the one-to-one unidirectional transmission path. Monitoring means; and the one-to-one from the source FIFO memory.
If it is determined that the packet is being transmitted on the unidirectional transmission path, the packet transferred from the input port is converted into the retransmission request packet, and the
Means for sending the retransmission request packet to the IFO memory, and a bypass reject flag for holding information indicating that the received packet has been rejected, and a transfer request source of the rejected packet when rejection occurs Means for setting the bypass reject flag corresponding to the processor node, and if the bypass reject flag corresponding to the processor node that is the transfer request source in the packet received thereafter is not set, Means for rejecting the packet again, wherein the bypass reject flag corresponding to the processor node which is the transfer request source is set in the packet received thereafter, and the one-to-one from the source FIFO memory is set.
2. The ring according to claim 1, further comprising means for loading the received packet into the bypass FIFO memory and resetting the corresponding bypass reject flag when no output is made on the unidirectional transmission line. Bus input / output control unit.