JPH1021647A - Integrated circuit for read-write amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an IC capable of correctly operating an AGC amplifier(an automatic gain control amplifier) in a subsequent stage after the lapse of shorter and more appropriate period of time from an R/W(write/read) switching time. SOLUTION: An R/W signal is applied to a masking signal generator 5. The masking signal generator 5 provides a masking signal having a time width which is determined by a resistor R1 and a capacitor C1 included therein for setting a time constant. The masking signal is applied to a latter-stage amplifier 3b in a read amplifier 3 to thereby restrain an amplifying operation of the amplifier 3b. On the other hand, the masking signal is also applied to a one-shot circuit 11 so as to generate, upon the termination of the mask signal, an input- restriction signal having a time width T0 which is determined by a resistor R2 and a capacitor C2 included therein for setting a time constant. The input- restriction signal is applied to an input-shortcircuit switch 10 of the AGC amplifier 8. Thus, an input to the AGC amplifier 8 is further restricted for a time period of T0 from the time when the restriction on operation of the read amplifier 3 was released, thereby, the amplifying operation of the AGC amplifier 8 is allowed to start at the time when a stable output, signal is provided from the read amplifier 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read / write amplifier integrated circuit (hereinafter referred to as a read / write amplifier IC) used for a hard disk drive (hereinafter referred to as an HDD) or the like.
It is about).

[0002]

2. Description of the Related Art In an HDD, a large amount of data is read from or written to a disk-shaped magnetic storage medium via a read / write head by a read / write amplifier IC, and amplified by the read / write amplifier IC. The write signal is processed by a read channel integrated circuit (hereinafter referred to as a read channel IC) at a subsequent stage including an AGC amplifier. FIG. 6 is a block diagram showing a part of a conventional read / write amplifier IC and read channel IC of this type, and FIG. 7 is a timing chart for explaining the operation thereof.

In the drawing, reference numeral 1 denotes a read / write head, 2
Is a read / write amplifier IC, 3 is a read amplifier for amplifying the read data signal from the read / write head 1 and 3 is a read driver for writing the write data signal to the read / write head 1. 5, a mask signal generator for generating a mask signal for suppressing the operation of the read amplifier 2 for a predetermined time from the application of the R / W signal (read / write switching signal); 6, a coupling capacitor; 7, a read channel IC; AGC amplifier, 9
Are AGC amplifier input suppression signal generation circuits for generating an input suppression signal for the AGC amplifier 8 in response to the R / W signal, and 10 is an AGC amplifier input short circuit switch which is closed by the input suppression signal from the circuit 9.

Next, the operation will be described. Now, it is assumed that the R / W signal is applied and the write mode is switched from the write mode in which the write driver 4 writes the write data signal to the read / write head 1 to the read mode. At this time, the R / W signal is applied to the pre-amplifier 3a of the read amplifier 3, the mask signal generator 5, and the AGC amplifier input suppression signal generation circuit 9, and the amplifier 3a starts amplifying the read data signal from the read / write head 1. And its R / W
A mask signal having a time width Tm from the switching time is generated by a mask signal generator 5 which is a one-shot circuit, and is applied to the subsequent amplifier 3b of the read amplifier 3, and the amplifier 3
The amplification operation of b is suppressed. On the other hand, an AGC amplifier input suppression signal having a time width Ts is generated by the AGC amplifier input suppression signal generation circuit 9 from the point of time of the R / W switching, and is applied to the AGC amplifier input short circuit switch 10 to close the switch 10.

At this time, a flyback voltage or an offset voltage due to the turning off of the write current of the read / write head 1 is applied to the pre-amplifier 3a of the read amplifier 3 and the amplifying operation thereof becomes unstable. Since a mask signal having a time width Tm from the generator 5 is applied and the amplification operation thereof is suppressed, the read amplifier 3 starts the amplification operation with a time width Tm delay from the R / W switching time, and the read / write head 1 The effect of the flyback voltage and the offset voltage from the power supply can be prevented. On the other hand, the output read signal of the read amplifier 3 is output from the AG of the read channel IC7.
The input short circuit switch 10 is applied to the input terminal of the C amplifier 8 by the input suppression signal from the AGC amplifier input suppression signal generation circuit 9 for the time width Ts from the time of the R / W switching.
, The operation of the AGC amplifier 8 is suppressed, and R /
Transient response of AGC (automatic gain control) due to sudden input voltage change at the time of W switching is prevented, and a stable read data signal can be obtained with a delay of Ts from the point of time of R / W switching.

[0006]

In the conventional read / write amplifier IC as described above, the time width Tm of the mask signal of the read amplifier 3 and the time width Ts of the AGC amplifier input suppression signal are set independently. Therefore, in some cases, a large time difference may occur between these two signals, and there is a problem that a loss occurs in a time required until the AGC amplifier enters a normal operation.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and a read / write which can normally operate a next stage AGC amplifier after a shorter and more appropriate time from the point of time of R / W switching. The purpose is to obtain an amplifier IC.

[0008]

A read / write amplifier IC according to the present invention comprises: a write driver for writing a write data signal to a read / write head of a disk-shaped storage medium; and an amplifier for amplifying a read data signal from the read / write head. A read amplifier for outputting to an AGC amplifier in an external read channel integrated circuit; and a mask signal for generating a mask signal for suppressing the operation of the read amplifier for a predetermined time after application of an R / W signal for switching from a write mode to a read mode. A read / write amplifier integrated circuit comprising: a time constant for generating an input suppression signal of the AGC amplifier which is generated in accordance with an output mask signal of the mask signal generator and is terminated after a predetermined time from the output mask signal; And a one-shot circuit having a resistor and a capacitor.

Further, in the above-mentioned device, the resistor or capacitor for the time constant constituting the one-shot circuit is externally provided to the integrated circuit.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. 1 and 2 show an embodiment of the present invention. FIG. 1 is a configuration diagram showing a part of a read / write amplifier IC and a read channel IC according to the first embodiment.
Is a timing chart for explaining the operation.

In FIGS. 1 and 2, 1 is a read / write head, 2 is a read / write amplifier IC, 3 is a read amplifier, 3a is a preceding amplifier, 3b is a latter amplifier, 4 is a write driver, 5 is a time constant. Signal generator which is a one-shot circuit (monostable circuit) having a resistor R ₁ for use and a capacitor C ₁ and generating a mask signal having a time width Tm;
Is a coupling capacitor, 7 is a read channel IC, 8 is A
GC amplifier 10 is an AGC amplifier input short-circuit switch,
The above is the same as the conventional example shown in FIG. 11 is
Generated in response to completion of output mask signal masks the signal generator 5 to generate an AGC amplifier input inhibit signal to terminate delayed further predetermined time To from the signal, when having a resistor R ₂ and capacitor C ₂ for a constant This is a one-shot circuit.

Next, the operation will be described. Now, R /
It is assumed that the W signal is applied, and the mode is switched from the write mode in which the write driver 4 writes the write data signal to the read / write head 1 to the read mode. At that time, R / W
The signal is applied to the pre-amplifier 3a of the read amplifier 3 and the mask signal generator 5, and the amplification of the read data signal from the read / write head 1 by the amplifier 3a is started, and when the R / W switching is performed, A mask signal having a time width Tm determined by the constant resistor R ₁ and the capacitor C ₁ is generated by a mask signal generator 5 which is a one-shot circuit, applied to the subsequent amplifier 3b of the read amplifier 3, and amplified by the amplifier 3b. Operation is suppressed.

Meanwhile, the output pulse signal of the mask signal generator 5 is applied to the one-shot circuit 11, AGC amplifier input constant resistor R ₂ and the determined time duration To the capacitor C ₂ when the internal from the end of the signal An inhibit signal is generated. The AGC amplifier input suppression signal is applied to the input short-circuit switch 10 of the AGC amplifier 8 in the read channel IC 7, and the switch 10 is closed. As a result, the input of the AGC amplifier 8 is further suppressed for a time To from the time when the suppression of the operation of the read amplifier 3 is released,
When a stable output signal is output from the read amplifier 3, the AGC amplifier 8 starts an automatic gain control amplification operation.

As described above, since the input suppression signal of the AGC amplifier 8 is generated in relation to the mask time of the read amplifier 3, when the input suppression signal is independently generated on the read channel IC 7 side as in the prior art. In comparison, the switching time to the read data output signal is further shortened and optimized.

FIG. 3 is a circuit diagram showing an example of the one-shot circuit 11 according to the first embodiment.
Is a DC power supply, Ip is an input terminal, Op is an output terminal, Tr ₁ , Tr
₂ is a transistor, Cp is a coupling capacitor, E ₁ and E ₂ are bias power supplies, CP is a comparator, R is a resistor for a time constant, and C is a capacitor for a time constant.

[0016] In the one-shot circuit, normally the transistor Tr ₁ is turned off, the transistor Tr ₂ is in the ON state for the bias power source E _1, current capacitor C to reach the ground fart the transistor Tr ₂ from the DC power source Vcc Has been charged. Therefore one input terminal of the comparator CP low potential (hereinafter referred to as L voltage) at lower than the bias power source potential E ₂ of the other input terminal, the comparator CP output terminal Op in off state to a high potential (hereinafter referred to as H voltage) is there.

In this state, if the input terminal Ip changes from L potential to H potential, the coupling capacitor C
charges the capacitor C becomes the transistor Tr ₁ temporary on the rising pulse of fart a p is discharged, the bias is one of the input terminals of the comparator CP supply potential E
_The H potential becomes higher than ₂ , the comparator CP turns on, and the output terminal Op goes to the L potential. Transistor Tr ₁ is turned off by the discharge of the total charges of the capacitor C, recharging of the capacitor C of fart transistors Tr ₂ and the resistor R is started. As a result, the potential of one input terminal of the comparator CP decreases at a time constant determined by the resistor R and the capacitor C, and the potential is reduced to the bias power supply potential E _2.
, The comparator CP is turned off, and the output terminal Op becomes the H potential.

As described above, an output pulse voltage having a time width determined by the time constant resistor R and the capacitor C is generated at the output terminal Op of the comparator CP. The time width To of the output pulse voltage is expressed by the following equation. To = K · C ₂ / R ₂
Here, K is a proportional constant determined by the circuit, C ₂ is the capacitance value of the time constant capacitor C, and R ₂ is the resistance value of the time constant resistor R. By appropriately setting the circuit constants C ₂ and R ₂ of the resistor R and the capacitor C, a pulse output voltage having a desired time width To can be obtained.

Embodiment 2 FIG. 4 shows a read / write amplifier IC and read channel I according to a second embodiment of the present invention.
1 is a read / write head, 2 is a read / write amplifier IC, 3 is a read amplifier, 3a is a preceding amplifier, 3b is a latter amplifier, and FIG.
4 is a write driver, 5 is a mask signal generator, 6 is a coupling capacitor, 7 is a read channel IC, 8 is an AGC amplifier, 10 is an AGC amplifier input short-circuit switch, and 11 is A
This is a one-shot circuit for generating a GC amplifier input suppression signal, which is the same as that of the first embodiment shown in FIG. However, the resistor for the time constant of the one-shot circuit 11 is not built in the IC 2 as in the first embodiment, but a resistor 12 having a desired resistance value R ₂ as an external resistor is connected to the IC 2 by soldering or the like. It is attached to.

As described above, in the second embodiment, since the resistor 12 for the time constant of the one-shot circuit 11 is externally provided, the resistor 12 having the desired resistance value R ₂ is externally provided after manufacturing the read / write IC. It is possible to obtain an AGC amplifier input inhibition signal having a time width To suitable for the read / write head 1. The time width To at this time is represented by the following equation. To
= K ₁ / R ₂ Here, K ₁ is a proportional constant including a capacitance value C ₂ of a built-in time constant capacitor determined by a circuit.

Embodiment 3 FIG. 5 shows a read / write amplifier IC and read channel I according to a third embodiment of the present invention.
1 is a read / write head, 2 is a read / write amplifier IC, 3 is a read amplifier, 3a is a preceding amplifier, 3b is a latter amplifier, and FIG.
4 is a write driver, 5 is a mask signal generator, 6 is a coupling capacitor, 7 is a read channel IC, 8 is an AGC amplifier, 10 is an AGC amplifier input short-circuit switch, and 11 is A
This is a one-shot circuit for generating a GC amplifier input suppression signal, which is the same as that of the first embodiment shown in FIG. However, the capacitor for the time constant of the one-shot circuit 11 is not built in the IC 2 as in the first embodiment, but has a desired capacitance value C as an external capacitor.
Capacitor 13 having a ₂ is not attached to the IC2 by soldering or the like.

As described above, in the third embodiment, since the time constant capacitor 13 of the one-shot circuit 11 is externally mounted, the capacitor 13 having the desired capacitance value C ₂ is externally mounted after the read / write IC 2 is mounted.
It is possible to obtain an AGC amplifier input inhibition signal having a time width To suitable for the read / write head 1. The time width To at this time is represented by the following equation. To = K ₂ · C ₂ Here, K ₂ is a proportional constant including a resistance value R ₂ of a built-in time constant resistor determined by a circuit.

[0023]

As described above, the present invention provides a write driver for writing a write data signal to a read / write head of a disk storage medium, an amplifier for amplifying a read data signal from the read / write head, and an external read channel. A read circuit comprising: a read amplifier for outputting to an AGC amplifier in an integrated circuit; and a mask signal generator for generating a mask signal for inhibiting the operation of the read amplifier for a predetermined time after application of an R / W signal for switching from a write mode to a read mode. In the integrated circuit for a write amplifier, a resistor and a capacitor for a time constant, which are generated in accordance with the output mask signal of the mask signal generator and generate an input suppression signal of the AGC amplifier which is terminated after a predetermined time from this signal, are connected. The one-shot circuit that has
The input suppression signal of the GC amplifier can be obtained, and after a shorter and more appropriate time from the R / W switching time, the AGC of the next stage can be obtained.
There is an effect that a read / write amplifier IC that can operate the amplifier normally can be obtained.

Further, in the above-mentioned device, since the resistor or capacitor for the time constant constituting the one-shot circuit is externally provided to the integrated circuit, the desired circuit constant number of resistors or capacitors is externally provided so that the integrated circuit can be obtained. There is an effect that an AGC amplifier input suppression signal having a time width suitable for the read / write head can be obtained after manufacturing.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a part of a read / write amplifier IC and a read channel IC according to a first embodiment of the present invention.

FIG. 2 is a timing chart illustrating operation of the first embodiment.

FIG. 3 is a circuit diagram illustrating an example of a one-shot circuit in Embodiment 1.

FIG. 4 is a configuration diagram showing a part of a read / write amplifier IC and a read channel IC according to a second embodiment;

FIG. 5 is a configuration diagram showing a part of a read / write amplifier IC and a read channel IC according to a third embodiment;

FIG. 6 is a configuration diagram showing a part of a conventional read / write amplifier IC and a read channel IC.

FIG. 7 is a timing chart illustrating an operation of a conventional example.

[Explanation of symbols]

1 read / write head, 2 read / write amplifier I
C, 3 read amplifier, 4 write driver, 5 mask signal generator, 7 read channel IC, 8 AGC amplifier, 10 AGC amplifier input short-circuit switch, 11 one-shot circuit, 12 external resistor for time constant, 13 external for time constant Capacitors.

Claims (3)

[Claims] 1. A write driver for writing a write data signal to a read / write head of a disk-shaped storage medium, and an automatic gain control amplifier in an external read channel integrated circuit for amplifying a read data signal from the read / write head. A read signal amplifier (hereinafter, referred to as a read amplifier) to be output to an AGC amplifier and a read / write switching signal (hereinafter, referred to as an R / W signal) for switching from a write mode to a read mode are inhibited for a predetermined time from application of the read / write signal. A read / write amplifier integrated circuit having a mask signal generator for generating a mask signal, wherein said signal is generated in response to an output mask signal of said mask signal generator, and is terminated after a predetermined time delay from said signal.
An integrated circuit for a read / write amplifier, comprising a monostable circuit (hereinafter, referred to as a one-shot circuit) having a resistor and a capacitor for a time constant for generating an input suppression signal of a GC amplifier. 2. The integrated circuit for a read / write amplifier according to claim 1, wherein the resistor constituting the one-shot circuit is external to the integrated circuit. 3. The integrated circuit according to claim 1, wherein the capacitor constituting the one-shot circuit is provided externally.
An integrated circuit for a read / write amplifier according to the above.