JPH10209462A - Thin film transistor and fabrication thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease series resistance by implanting n-type impurities into the source and drain regions of a semiconductor layer thereby forming a junction. SOLUTION: Cr is deposited on an insulating substrate 21 and patterned to form a gate electrode 1. A gate insulation layer 2 and an undoped semiconductor layer, i.e., an amorphous silicon layer serving as a channel layer, is then formed continuously. Subsequently, a resist layer is formed and phosphorus is implanted using the resist layer as a mask. Thereafter, a two layer structure of Cr and Al is formed on an underlying second conductive layer and a channel region is removed by etching an isolated to obtain source electrodes 7a, 7b and drain electrodes 7c, 7d. Since ion implantation is employed for forming a junction of amorphous silicon and the n-type impurities in an n-type impurity implantation region 6, series resistance between source and drain can be decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a thin film transistor,
In particular, the present invention relates to improvement of electric characteristics of a thin film transistor used for an active matrix type liquid crystal display device, and particularly relates to improvement of electric resistance, that is, reduction of series resistance, reduction of light generation current during light irradiation, and reduction of off current.

[0002]

2. Description of the Related Art Switching elements used in active matrix type liquid crystal display devices, so-called thin film transistors (hereinafter simply referred to as TFTs).
Are classified into a forward stagger structure and a reverse stagger structure according to their structures. Further, the inverted stagger structure TFT includes an etching stopper type TFT (ES-TFT) and a channel etch (hereinafter simply referred to as CE) type TF.
T (CE-TFT). FIG. 10 is an explanatory sectional view of a conventional channel-etch type TFT.
10A shows an etching stopper (hereinafter simply referred to as ES) type TFT (ES-TFT), and FIG. 10B shows a channel etch type TFT (CE-TF).
T) shows a cross-sectional structural view, respectively. In FIG. 10, 1
Is a gate electrode, 2 is a gate insulating film, 7a and 7b are 2
A layer structure source electrode, 7c and 7d are two-layer structure drain electrodes, 9 is a channel region, 13 is an etching stopper film, 14 is an n-type doped amorphous silicon layer, 21 is an insulating substrate, and 23 is a channel layer Are respectively shown.

Each type of TFT has advantages and disadvantages. For example, in the case of an ES-TFT, the interface between the etching stopper and the amorphous silicon layer is formed cleanly, so that a characteristic with a small off-current can be obtained. However, on the other hand, in terms of miniaturization, the patterning size of the etching stopper and the separation of the source electrode and the drain electrode riding on the etching stopper are defined by the transfer accuracy of the transfer device (stepper), so that miniaturization is difficult. At the same time, the source electrode and the drain electrode are formed asymmetrically with respect to the etching stopper, and the characteristics may also be asymmetric. Here, non-characteristics means that current-voltage characteristics are different between when the ground electrode is used as the source electrode and when the ground electrode is used as the drain electrode. On the other hand, the CE-TFT can be easily reduced in size and the characteristics are not asymmetrical.
Although it is more advantageous than the S-TFT, the channel region of the amorphous silicon layer through which a current flows is etched to separate the source electrode and the drain electrode, so that etching damage is present in the channel region. An increase in off-state current is observed. In addition, regarding the etching of the channel region, the thickness of the channel region is inevitably increased in order to prevent the amorphous silicon layer in the channel region from disappearing due to over-etching. Such thickening causes a problem that the series resistance from the source electrode to the channel region increases and the photo-generated current increases.
In such a background, the structure of a TFT used in an active matrix type liquid crystal display device is an ES-TFT type,
This is a situation where E-TFT types are mixed.

Here, a conventional method for manufacturing a CE-TFT will be described in detail with reference to the drawings. 11 and 12 are process cross-sectional views showing the steps of manufacturing a conventional CE-TFT by process. The process flow will be described below with reference to FIGS. First, a Cr film serving as the gate electrode 1 is deposited to a thickness of about 300 nm on an insulating substrate 21 made of glass or the like by sputtering. This is shown in FIG.
(A). Next, a silicon nitride film (SiNx) serving as the gate insulating film 2, an amorphous silicon layer serving as the channel layer 23, and an n-type doped amorphous silicon layer (hereinafter, also simply referred to as an n-type amorphous silicon layer) 14 are subjected to plasma CVD ( Chemical Vapor depositio
n, hereinafter simply referred to as CVD) to form a continuous film. The thickness of the gate insulating film 2 is 300 to 400 n.
m, amorphous silicon layer is 200 to 400 nm, n
Type amorphous silicon layer (hereinafter referred to as
14 is 50-
100 nm. This is shown in FIG. Next, the amorphous silicon layer serving as a channel layer and the n-type amorphous silicon layer 14 are patterned into an island shape by a dry etching method. This is shown in FIG.
Next, in order to form the source electrodes 7a and 7b and the drain electrodes 7c and 7d, Cr and then Al are sequentially deposited as a two-layer structure by a sputtering method, patterned by photolithography, and etched to form a Cr film on the channel region 9 by etching. And the Al film is removed to remove the source electrode 7a.
And 7b and drain electrodes 7c and 7d are formed. This is shown in FIG. Next, dry etching is performed to completely remove the etching residue on the n-type amorphous silicon layer 14 in the region between the source electrode and the drain electrode, that is, in the channel region 9. At this time, part of the amorphous silicon layer in the channel region is also etched by over-etching. The amount of over-etching is 50 to 100 nm. A diagram of this step is shown in FIG. Finally, a passivation film 10 is formed of a silicon nitride film, and a channel-etch type TFT (CE-TFT) is manufactured.
This is shown in FIG.

[0005]

SUMMARY OF THE INVENTION Channel-etch type TF
In order to improve display characteristics by applying T (CE-TFT) to an active matrix type liquid crystal display, the thickness of an amorphous silicon layer serving as a channel layer is reduced, and the mutual relation is obtained as follows. Various properties need to be improved. That is, reduction of series resistance,
A reduction in light generation current, a reduction in off-state current due to the junction, and a reduction in off-state current due to the back channel interface. Hereinafter, each will be described in detail.

First, the reduction of the series resistance will be described. In a CE-TFT, as shown in the process flow of the related art, an n-type doped amorphous layer remaining between the source electrode and the drain electrode (hereinafter, simply referred to as “source-drain”) after the formation of the source electrode and the drain electrode. Overetching is performed to completely remove the silicon residue. If this residue remains, a short circuit occurs between the source and the drain due to the residue of the low-resistance n-type amorphous silicon layer, or
A short circuit occurs between the source and the drain due to the silicide film formed of amorphous silicon and Cr. Since the etching selectivity between the n-type amorphous silicon layer and the amorphous silicon layer serving as the channel region is small, the amorphous silicon layer serving as the channel region is also etched by over-etching. In order to prevent disconnection between the source and drain due to over-etching, it is necessary to increase the thickness of the amorphous silicon layer serving as a channel region.
In the case of the CE-TFT, the thickness of the amorphous silicon layer set to about 100 nm is required to be 200 to 400 nm. Since the amorphous silicon layer serving as the channel region is not doped, it becomes a high-resistance layer, and has a great influence on the TFT characteristics, so that a sufficient current cannot be obtained in the current-voltage characteristics.

Next, the reduction of the light generation current will be described. A current generated by light irradiation (hereinafter, referred to as a light generation current) deteriorates display characteristics, and thus needs to be reduced. This photo-generated current is closely related to the thickness of the amorphous silicon layer, and increases as the thickness increases. As described in the section on reducing series resistance, CE-T
In FT, since the thickness of the amorphous silicon layer is large, the amount of photogenerated current is also large.

Next, a description will be given of a reduction in off-state current caused by junction. In order to improve display characteristics, it is necessary to reduce the off-current. There are several possible off-current generation mechanisms, one of which is a junction breakdown in a stepwise junction between an n-type amorphous silicon layer and a non-doped amorphous silicon layer. Conventional CE-TF
In T, the method for forming the n-type amorphous silicon layer is CV.
D is used. Therefore, the interface between the n-type amorphous silicon layer and the non-doped amorphous silicon layer is
Because of the so-called step junction, the impurity profile becomes steep, a high electric field is generated, and a large off-state current flows. This situation is the same in the case of the ES-TFT.
In order to improve the steepness of such an impurity profile, the impurity profile is inclined by adopting an ion implantation method as a doping method, so that a steep electric field intensity peak at an interface in the case of a step junction is provided. , The off-state current can be reduced by forming a so-called gentle junction. Here, an amorphous silicon semiconductor,
When a junction is formed in the amorphous silicon semiconductor with, for example, a region doped with an n-type impurity, the doping concentration is kept constant over the entire region doped with the n-type impurity so that the doping concentration changes abruptly at the interface of the junction. What is formed is a "step junction". On the other hand, in the region where the n-type impurity is doped, the doping concentration is gradually reduced toward the junction interface, so that the concentration becomes low near the junction interface. “Smooth junction” is formed so that the doping concentration changes gradually at the interface of the junction. The electric field strength at the interface of bonding, since the impurity concentration at the interface with an abrupt junction and abruptly changed from 0 to a certain value, indicate peak E ₁ field intensity steeply across the interface at this time On the other hand, in the case of a gentle junction, the impurity concentration gradually changes at the interface, and therefore, a gentle and low peak E ₂ (E ₁ > E ₁ )
₂ ) is shown. As described above, the off-state current can be reduced by forming a gentle junction. However, in order to apply the ion implantation method to the conventional CE-TFT structure, the impurity is also added to the channel region in terms of the process flow. Is limited, which is difficult.

Next, the reduction of off-state current caused by the back channel interface will be described. The back channel is the part of the amorphous silicon layer that is not in contact with the gate insulating film but is in contact with the passivation insulating film. The back channel interface is the interface between the amorphous silicon layer and the passivation film. It is. In a CE-TFT, when a conductive film formed over the entire surface is separated into a source electrode and a drain electrode, an amorphous silicon layer serving as a channel region is also etched. Due to this etching, irregularities are formed at the interface between the amorphous silicon layer serving as a channel region and the passivation film, and defects due to plasma damage during etching and interface states caused by dangling bonds of atoms are formed. An increase in off-state current that passes through the interface state is observed.

An object of the present invention is to provide a thin film transistor having a structure capable of obtaining a thin amorphous silicon layer, a gentle impurity profile, and a clean back channel interface in order to solve these problems, and a method of manufacturing the same.

[0011]

In order to solve the above-mentioned problems, according to the present invention, after forming an amorphous silicon layer to be a thinner channel layer than before, a resist mask is formed on the amorphous silicon layer by photolithography. In addition, a feature is that a junction is formed by ion implantation to form a junction having a small series resistance and a gentle impurity profile.

Therefore, the transistor of the present invention becomes an insulating substrate, a first conductive film layer provided on the insulating substrate and serving as a gate electrode, and a gate insulating film layer on the first conductive film layer. A first insulating film layer, a non-doped semiconductor layer on the first insulating film layer, a source electrode formed on a source region of the semiconductor layer, and a drain electrode formed on a drain region of the semiconductor layer. Wherein a junction in which an n-type impurity is implanted is formed in a source region of the semiconductor layer and a drain region of the semiconductor layer.

In the method of manufacturing a thin film transistor according to the present invention, (a) a first conductive film is formed on an insulating substrate, and then the first conductive film is etched to provide a gate electrode;
(B) forming a first insulating film layer and a non-doped semiconductor layer on the gate electrode, patterning the semiconductor layer in an island shape, and (c) forming a resist film on the semiconductor layer by photolithography. An n-type impurity is vertically injected using the resist film as a mask to form a junction. (D) After removing the resist film, a second conductive film is formed, and a photo is formed on the second conductive film. An electrode pattern is formed by plate making, and the second conductive film is etched to provide a source electrode and a gate electrode.

The method of manufacturing a thin film transistor according to the present invention comprises the steps of (a) forming a first conductive film on an insulating substrate and then etching the first conductive film to form a gate electrode;
(B) forming a first insulating film layer and a non-doped semiconductor layer on the gate electrode, patterning the semiconductor layer in an island shape, and (c) forming a resist film on the semiconductor layer by photolithography. A junction is formed by ion-implanting an n-type impurity by rotational oblique implantation using the resist film as a mask, and (d) removing the resist film, forming a second conductive film, and then forming the second conductive film. A method for manufacturing a thin film transistor, comprising forming an electrode pattern on a film by photolithography and etching the second conductive film to provide a source electrode and a gate electrode.

The thin-film transistor of the present invention comprises an insulating substrate, a first conductive film layer provided on the insulating substrate and serving as a gate electrode, and a first conductive film layer serving as a gate insulating film layer on the first conductive film layer. An insulating film layer, a non-doped semiconductor layer on the first insulating film layer, and a source electrode formed on a source region of the semiconductor layer and a drain electrode formed on a drain region of the semiconductor layer. In a thin film transistor including a second conductive film layer, a junction into which an n-type impurity is implanted is formed in a source region of the semiconductor layer and a drain region of the semiconductor layer, and An n-type impurity is also implanted into a portion below the source electrode and a portion below the drain electrode.

The method for manufacturing the thin film transistor of the present invention is as follows.
(A) forming a first conductive film on an insulating substrate and then etching the first conductive film to provide a gate electrode;
Forming a first insulating film layer and a non-doped semiconductor layer on the gate electrode; and (c) forming a resist film on the semiconductor layer and exposing the resist film by exposing from the back side of the insulating substrate. After forming a resist pattern and implanting n-type impurities by ion implantation as a mask, (d) removing the resist film, (e) forming a second conductive film, and then photographing the second conductive film. An electrode pattern is formed by plate making, and the second conductive film is etched to provide a source electrode and a gate electrode.

(A) After forming a first conductive film on an insulating substrate, the first conductive film is etched to provide a gate electrode, and (b) a first insulating film is formed on the gate electrode. (C) forming a resist film on the semiconductor layer, and then exposing from the back side of the insulating substrate to form a resist pattern on the resist film, and forming an n-type impurity as a mask. (D) removing the resist film, (e) forming a second conductive film, and forming an electrode pattern on the second conductive film by photolithography. A source electrode and a gate electrode are provided by etching the second conductive film.

According to the thin film transistor and the method of manufacturing the same of the present invention, the thickness of the amorphous silicon layer in the channel region is reduced, and the series resistance is reduced. Further, since the ion implantation is applied to the formation of the junction, the impurity profile becomes gentle, the electric field is relaxed, and the off-current is reduced. As a result, the electrical characteristics of the obtained CE-TFT are greatly improved, and stable and high-quality display characteristics can be obtained.

[0019]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

Embodiment 1 FIG. 1 shows a CE-TFT according to an embodiment of the present invention.
FIG. FIG. 1A is an explanatory plan view showing a configuration of an electrode related to a CE-TFT, and FIG.
It is sectional drawing of the CE-TFT cut | disconnected by the AA line shown in (a). In FIG. 1, 1 is a gate electrode as a first conductive film layer, 2 is a gate insulating film as a first insulating film layer, 3 is a channel layer as a non-doped semiconductor layer, 6
Are n-type impurity implanted regions in the channel layer, 7a and 7b
Denotes a source electrode having a two-layer structure, 7c and 7d denote drain electrodes having a two-layer structure, 9 denotes a channel region, 10 denotes a passivation film, and 21 denotes an insulating substrate, respectively (FIG. 1A).
The passivation film 10 is not shown in FIG. FIGS. 2 and 3 are process cross-sectional views showing a method of manufacturing a CE-TFT according to the present invention, wherein 4 denotes a resist film, 5 denotes phosphorus implantation, and 8 denotes a chromium silicide film. The same elements as those shown in FIG. 1 are denoted by the same reference numerals (the same applies to the following drawings).

FIG. 1B is a sectional view of the TF shown in FIG.
The method of manufacturing T will be described in order with reference to FIGS. 2A to 2C and 3D to 3G according to a process flow. First, a Cr film, which is a metal having a low resistance and a high melting point, is formed on an insulating substrate 21 made of glass or the like by a sputtering method. Next, a pattern is formed by photolithography, and a Cr film is patterned by etching to form a gate electrode 1 (FIG. 2A). Next, the gate insulating film 2,
As an intrinsic, ie, non-doped, semiconductor layer serving as the channel layer 3, amorphous silicon (i-
An a-Si: H) layer is continuously formed by plasma CVD. At this time, the thickness of the gate insulating film is about 400 n.
m, about 1 amorphous intrinsic silicon layer
It is about 00 nm. Next, a resist film 4 is formed by photolithography (FIG. 2B). Next, phosphorus implantation 5 is performed using the resist film as a mask. Since the implantation energy and the implantation amount at this time depend on the thickness of the amorphous silicon layer serving as the channel layer, they are determined according to the thickness of the amorphous silicon layer. The magnitude of the implantation energy can be represented by using the implantation range Rp as an index. The implantation range Rp is such that the range in which impurities are actually implanted is Rp−Rw with a width Rw relative to a certain center value Rp. To Rp
The center value Rp when expressed as a range of + Rw. In this case, when the injection energy is large, Rp increases and Rw increases.

When the implantation range Rp is appropriately selected with respect to the layer thickness t of the amorphous silicon layer into which the impurity is to be implanted, Rp is located at the center of the layer thickness t, and Rp-Rw To Rp + Rw is 2R with respect to the layer thickness t.
Although w ≦ t can be satisfied, if not properly selected, for example, if it is selected to be too large, Rp deviates from the center of t and Rw is also large. It will also be implanted into other adjacent layers.

If Rp is set to a large value so that impurities are implanted into an insulating film to which impurities should not be implanted, the surface impurity concentration of the amorphous silicon layer decreases, and the amount of impurities is small. Since the region is included in the amorphous silicon layer, the resistance of the amorphous silicon layer is increased, and therefore, the TFT characteristics are deteriorated.

As described above, it is necessary to appropriately set the implantation range of the impurity and therefore the implantation energy in accordance with the thickness t of the amorphous silicon layer.
It is desirable that p be equal to or less than the thickness of the amorphous silicon layer. For example, if the thickness of the amorphous silicon layer is 100
For a film thickness of about nm, the implantation energy is about 30K
eV, the injection amount is about 5E14 / cm ² or more,
At this time, the injection range Rp is about 300 ° (FIG. 2).
(C)). Next, the resist is stripped off, photolithography is performed, and the amorphous silicon layer is etched into an island shape (FIG. 3D). Next, a second conductive film is formed on
After forming a two-layer structure in which Al is deposited thereon, the channel region of the second conductive film is removed by etching to separate it into a source electrode and a drain electrode. In order to form the two-layer structure, a Cr film and then an Al film are sequentially deposited over the entire surface of the gate insulating film and the channel layer by sputtering. An electrode pattern is formed by photolithography on a region where the source electrode is formed (source region) and a region where the drain electrode is formed (drain region), and the channel of the channel layer 3 in the conductive film having the two-layer structure is formed. The Cr film and the Al film in the portion on the region 9 are etched (FIG. 3E). When this etching is performed, a small amount of the chromium silicide (CrSix) film 8 is formed discontinuously as shown symbolically in the figure due to the reaction between Cr and the amorphous silicon layer, which may cause a short circuit between the source and the drain. Therefore, the CrSix film is further removed by dry etching (FIG. 3F). In this dry etching, the selectivity between the CrSix film and the amorphous silicon film is sufficient, so that the amorphous silicon layer is not greatly etched, so that the thinned amorphous silicon layer is not disconnected in the channel region. Further, a nitride film 10 serving as a passivation film is deposited to a thickness of about 500 nm by plasma CVD to complete the CE-TFT (FIG. 3 (g)). As a result, the amorphous silicon layer serving as the channel layer is formed thin, and the ion implantation is used to form the junction between the amorphous silicon and the n-type impurity in the n-type impurity implantation region 6. Has a small series resistance, suppresses an increase in photogenerated current, and forms a junction with a gentle impurity profile by ion implantation, thereby reducing the electric field generated at the junction interface and suppressing an increase in off-current. T
A CE-TFT with stable FT characteristics can be obtained.

Second Embodiment In the first embodiment, phosphorus is implanted vertically into an intrinsic amorphous silicon layer when phosphorus as an impurity is implanted. In Embodiment 2, as shown in the cross-sectional view of the TFT according to another embodiment of the present invention shown in FIG. 4, the oblique implantation of phosphorus 11 is performed by continuously rotating a stage of an ion implanter on which a substrate is set. While doing. As a result, the impurity profile at the interface between the amorphous silicon layer serving as a channel and the impurity-implanted region becomes more gentle, the generation of a high electric field at the junction during the operation of the TFT is suppressed, and a reduction in off-current is achieved. Will be. As an implantation condition at this time, when the implantation is performed at the implantation angle θ, the range Rp of the impurity is expressed by the following formula: Rp = d / co
It is necessary to select an implantation energy that satisfies sθ.
Here, d is the film thickness of the amorphous silicon layer serving as a channel. The injection amount may be about the same as in the first embodiment (FIG. 4).

Third Embodiment In the third embodiment, a CE-type TFT having more stable TFT characteristics is used.
The structure and manufacturing method of the TFT will be described. Embodiment 1,
In pattern No. 2, patterning of the Cr film and the Al film serving as the source electrode and the drain electrode after the formation of the junction by ion implantation was performed so that the source electrode and the drain electrode covered the n-type impurity implanted region 6. This is shown in FIG. The following problems may occur in this structure. FIG. 5 shows a TF according to another embodiment of the present invention.
FIG. 5 is an explanatory cross-sectional view illustrating the length of an impurity implantation region of T. In FIG. 5B, reference numeral 16 denotes an impurity implantation region.
In FIG. 5A, when the lengths A and B of the regions under the source electrode and the drain electrode where no impurities are present are equal, T
The FT characteristics are symmetric. However, when the lengths of A and B are different, the region under the source electrode and the drain electrode where no impurity exists becomes a resistance, and the parasitic resistance differs between the source electrode and the drain electrode, resulting in asymmetry in characteristics. Will be. In order to solve this, it is necessary to define the length of the source electrode and the drain electrode by the length of the impurity implantation region. A method of manufacturing a TFT having a structure in which the lengths of the source electrode and the drain electrode are defined by the length of the impurity region will be described. It is the same as the first and second embodiments until the ion implantation is performed and the impurity layer is formed. In forming the source electrode and the drain electrode, a conductive film having a two-layer structure in which the underlayer is Cr and the upper layer is Al is formed by a sputtering method so that the impurity layer injection region 16 exists under the source electrode and the drain electrode. Perform photoengraving. Thereafter, the film having the two-layer structure is etched, and the desired CE-T
An FT is formed. This is shown in FIG. By employing this structure, there is no amorphous silicon layer having a high resistance under the source electrode and the drain electrode, so that the problem of the asymmetry of the TFT characteristics is eliminated. In this case, the curved portion of the impurity-implanted region indicated by reference numeral 16 is a junction.

Fourth Embodiment In a fourth embodiment, the basic TF shown in the first to third embodiments is used.
A method for reducing the size of a TFT while employing the T structure will be described. 6, 7, 8 and 9 show the manufacturing method. 6, 8 and 9 are process cross-sectional views illustrating a method of manufacturing a TFT according to the present embodiment, and FIG. 7 is an explanatory view of a pattern after development by photolithography. In FIG.
Reference numeral 12 denotes exposure. In FIG. 7, reference numeral 26 denotes an impurity implantation region.

First, a Cr film, which is a metal having a low resistance and a high melting point, is formed on a glass substrate by a sputtering method. Next, a pattern is formed by photolithography, a pattern of a Cr film is formed by etching, and a gate electrode 1 is formed (FIG. 6).
(A)). Next, intrinsic amorphous silicon (iaS) which becomes the gate insulating film 2 and the channel layer 3 is formed.
i: H) A layer is continuously formed by plasma CVD. At this time, the gate insulating film has a thickness of about 400 nm, and the intrinsic amorphous silicon layer has a thickness of about 100 nm (FIG. 6B). Next, a resist film is applied by photolithography. Next, in FIG.
Exposure 12 is performed by irradiating light from the back side as indicated by the arrow indicated by. The pattern after exposure 12 from the back side and development is shown in FIG. 6C and FIG. FIG. 8 is an explanatory plan view of the pattern after development, and FIG.
It is sectional drawing of the CE-TFT in the AA line shown in the inside. The pattern of the resist film formed as shown in this figure is a pattern smaller than the gate wiring pattern. In this state, phosphorus implantation 5 is performed on the entire surface using the resist as a mask (FIG. 8D). The implantation energy and the implantation amount at this time are the same as the conditions described in the first embodiment. Next, the resist is stripped, and a predetermined region, that is, a region where a TFT is formed is formed in an island shape, and an n-type impurity implantation region 26 is formed (FIG. 8E). After removing the resist film, a Cr film and an Al film serving as a source electrode and a drain electrode are deposited by a sputtering method. An electrode pattern is formed by photolithography, and the Cr film and the Al film are etched (FIG. 9F). When performing this etching, a small amount of chromium silicide (CrSix) is formed due to the reaction between Cr and amorphous silicon, which may cause a short circuit between the source and the drain. Therefore, CrSix is further removed by dry etching (FIG. 9 ( g)). In this dry etching, since the selectivity between CrSix and the amorphous silicon film is sufficient, the amorphous silicon layer is not largely etched and does not greatly affect the formed amorphous silicon layer. Further, a nitride film serving as the passivation film 10 is deposited to a thickness of about 500 nm by plasma CVD, thereby completing the CE-TFT (FIG. 9 (h)). By this method, the gate wiring width in the wiring region where the TFT is formed is reduced, the aperture ratio is improved, and the parasitic capacitance of the TFT itself is reduced.

[0029]

As described above in detail, in the channel-etch type thin film transistor according to the present invention, the thickness of the amorphous silicon layer serving as the channel layer is reduced, and the impurity layers in the source region and the drain region are formed by ion implantation. As a result, the reduction of series resistance, which has been a problem in the conventional structure, is achieved, and the generation of a high electric field at the time of voltage application is suppressed by the gentle junction formation by ion implantation, thereby preventing an increase in off-current. As a result, an active matrix liquid crystal display having excellent display characteristics can be obtained.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a TFT according to an embodiment of the present invention.

FIG. 2 is an explanatory cross-sectional view of a process of a TFT according to an embodiment of the present invention.

FIG. 3 is an explanatory sectional view showing a step of a TFT according to an embodiment of the present invention.

FIG. 4 is an explanatory cross-sectional view showing a step of a TFT according to another embodiment of the present invention.

FIG. 5 is an explanatory sectional view showing a step of a TFT according to another embodiment of the present invention.

FIG. 6 is an explanatory sectional view showing a step of a TFT according to another embodiment of the present invention.

FIG. 7 is an explanatory plan view of a pattern after development according to another embodiment of the present invention.

FIG. 8 is an explanatory sectional view showing a step of a TFT according to another embodiment of the present invention.

FIG. 9 is an explanatory process sectional view of a TFT according to another embodiment of the present invention.

FIG. 10 is an explanatory sectional view of a conventional etching stopper type TFT.

FIG. 11 is a process sectional view for explaining a conventional channel-etch type TFT.

FIG. 12 is a process cross-sectional view illustrating a conventional channel-etch type TFT.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Gate electrode 2 Gate insulating film 3 Channel layer 4 Resist film 5 Phosphorus injection 6, 16, 26 n-type impurity implantation regions 7a, 7b Source electrode 7c, 7d Drain electrode 8 Chromium silicide film 9 Channel region 10 Passivation film 11 Phosphorus Oblique injection 12 Exposure 21 Insulating substrate

Claims (6)

[Claims] 1. An insulating substrate and a first conductive film layer provided on the insulating substrate and serving as a gate electrode, and a first insulating film layer serving as a gate insulating film layer over the first conductive film layer A non-doped semiconductor layer on the first insulating film layer, and a second conductive layer serving as a source electrode formed on a source region of the semiconductor layer and a drain electrode formed on a drain region of the semiconductor layer. A thin film transistor comprising a film layer, wherein a junction in which an n-type impurity is implanted is formed in a source region of the semiconductor layer and a drain region of the semiconductor layer. (A) forming a first conductive film on an insulating substrate, etching the first conductive film to provide a gate electrode, and (b) forming a first conductive film on the gate electrode. An insulating film layer and a non-doped semiconductor layer are formed, the semiconductor layer is patterned into an island shape, and (c) a resist film is formed on the semiconductor layer by photolithography, and n-type impurities are vertically formed using the resist film as a mask. (D) removing the resist film, forming a second conductive film, forming an electrode pattern on the second conductive film by photolithography, and forming the second conductive film. A method for manufacturing a thin film transistor, comprising providing a source electrode and a gate electrode by etching a conductive film. And (a) forming a first conductive film on the insulating substrate and then etching the first conductive film to form a gate electrode; and (b) forming a first conductive film on the gate electrode. Forming an insulating film layer and a non-doped semiconductor layer, patterning the semiconductor layer into an island shape, (c) forming a resist film on the semiconductor layer by photolithography, and rotating the n-type impurity using the resist film as a mask; A junction is formed by ion implantation by oblique implantation, and (d) after removing the resist film,
A method for producing a thin film transistor, comprising forming an electrode pattern on the second conductive film by photolithography, etching the second conductive film, and providing a source electrode and a gate electrode. 4. An insulating substrate and a first conductive film layer provided on the insulating substrate and serving as a gate electrode, and a first insulating film layer serving as a gate insulating film layer on the first conductive film layer A non-doped semiconductor layer on the first insulating film layer, and a second conductive layer serving as a source electrode formed on a source region of the semiconductor layer and a drain electrode formed on a drain region of the semiconductor layer. A thin film transistor including a film layer, wherein a junction into which an n-type impurity is implanted is formed in a source region of the semiconductor layer and a drain region of the semiconductor layer, and a junction of the semiconductor layer below the source electrode. And a portion below the drain electrode is also doped with an n-type impurity. 5. A gate electrode is provided by (a) forming a first conductive film on an insulating substrate and then etching the first conductive film, and (b) forming a first conductive film on the gate electrode. Forming an insulating film layer and a non-doped semiconductor layer, (c) forming a resist film on the semiconductor layer, and exposing from the back side of the insulating substrate to form a resist pattern on the resist film to form a mask with n (D) removing the resist film, (e) forming a second conductive film, and forming an electrode pattern on the second conductive film by photolithography. A method for manufacturing a thin film transistor, wherein a source electrode and a gate electrode are provided by etching a second conductive film. 6. A gate electrode is provided by (a) forming a first conductive film on an insulating substrate and then etching the first conductive film, and (b) forming a first conductive film on the gate electrode. Forming an insulating film layer and a non-doped semiconductor layer, (c) forming a resist film on the semiconductor layer, and exposing from the back side of the insulating substrate to form a resist pattern on the resist film to form a mask with n (D) removing the resist film, and (e) removing the second
Forming a conductive film, forming an electrode pattern on the second conductive film by photolithography, etching the second conductive film, and providing a source electrode and a gate electrode. .