JPH10209369A - Packaging method of semiconductor integrated circuit - Google Patents
Packaging method of semiconductor integrated circuitInfo
- Publication number
- JPH10209369A JPH10209369A JP834697A JP834697A JPH10209369A JP H10209369 A JPH10209369 A JP H10209369A JP 834697 A JP834697 A JP 834697A JP 834697 A JP834697 A JP 834697A JP H10209369 A JPH10209369 A JP H10209369A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- terminal
- mounting
- integrated circuit
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は実装基板上に複数の
ＩＣチップを搭載する半導体集積回路の実装方法に関す
るものである。The present invention relates to a method for mounting a semiconductor integrated circuit in which a plurality of IC chips are mounted on a mounting board.
【０００２】[0002]
【従来の技術】図３は従来例の実装基板上に複数のＩＣ
チップを搭載する半導体集積回路の構成を示す図であ
る。FIG. 3 shows a conventional example in which a plurality of ICs are mounted on a mounting substrate.
FIG. 2 is a diagram illustrating a configuration of a semiconductor integrated circuit on which a chip is mounted.
【０００３】第１のＩＣチップ５１は実装基板５４上に
配置し、第１のＩＣチップ５１の第１の端子６１は実装
基板５４上の第１の端子７１に第１のワイヤー８１をも
って接続する。また、第１のＩＣチップ５１の第２の端
子６２も同様に実装基板５４上の第２の端子７２に第２
のワイヤー８２をもって接続する。A first IC chip 51 is disposed on a mounting substrate 54, and a first terminal 61 of the first IC chip 51 is connected to a first terminal 71 on the mounting substrate 54 with a first wire 81. . Similarly, the second terminal 62 of the first IC chip 51 is also connected to the second terminal 72 on the mounting substrate 54 by the second terminal.
With the wire 82.
【０００４】第２のＩＣチップ５２は実装基板５４上に
配置し、第２のＩＣチップ５２の第１の端子６３は実装
基板５４上の第３の端子７３に第３のワイヤー８３をも
って接続する。また、第２のＩＣチップ５２の第２の端
子６５も同様に実装基板５４上の第４の端子７５に第４
のワイヤー８５をもって接続する。[0004] The second IC chip 52 is disposed on a mounting board 54, and the first terminal 63 of the second IC chip 52 is connected to a third terminal 73 on the mounting board 54 with a third wire 83. . Similarly, the second terminal 65 of the second IC chip 52 is also connected to the fourth terminal 75 on the mounting substrate 54 by the fourth terminal 75.
With the wire 85.
【０００５】第３のＩＣチップ５３は実装基板５４上に
配置し、第３のＩＣチップ５３の第１の端子６４は実装
基板５４上の第５の端子７４に第５のワイヤー８４をも
って接続する。また、第３のＩＣチップ５３の第２の端
子６６も同様に実装基板５４上の第６の端子７６に第６
のワイヤー８６をもって接続する。[0005] The third IC chip 53 is arranged on a mounting board 54, and the first terminal 64 of the third IC chip 53 is connected to a fifth terminal 74 on the mounting board 54 with a fifth wire 84. . Similarly, the second terminal 66 of the third IC chip 53 is also connected to the sixth terminal 76 on the mounting board 54 by the sixth terminal 76.
With the wire 86 of FIG.
【０００６】同一信号である第１のＩＣチップ５１の第
１の端子６１と第２のＩＣチップ５２の第１の端子６３
と第３のＩＣチップ５３の第１の端子６４とそれぞれ接
続する実装基板上の第１の端子７１と第３の端子７３と
第５の端子７４を実装基板５４上の配線９１により接続
する。[0006] The first terminal 61 of the first IC chip 51 and the first terminal 63 of the second IC chip 52 which have the same signal.
The first terminal 71, the third terminal 73, and the fifth terminal 74 on the mounting board, which are respectively connected to the first terminal 64 of the third IC chip 53, are connected by the wiring 91 on the mounting board 54.
【０００７】同一信号である第２のＩＣチップ５２の第
２の端子６５と第３のＩＣチップ５３の第２の端子６６
とそれぞれ接続する実装基板５４上の第４の端子７５と
第６の端子７６を実装基板５４上の配線９２により接続
する。[0007] The second terminal 65 of the second IC chip 52 and the second terminal 66 of the third IC chip 53 that have the same signal.
The fourth terminal 75 and the sixth terminal 76 on the mounting board 54 that are respectively connected to are connected by the wiring 92 on the mounting board 54.
【０００８】[0008]
【発明が解決しようとする課題】従来の複数のＩＣチッ
プを搭載する半導体集積回路では複数のＩＣチップを配
置する面積とこれらの端子を接続する配線領域の面積を
実装基板上で確保しなくてはならないという課題があ
る。In a conventional semiconductor integrated circuit on which a plurality of IC chips are mounted, an area for arranging the plurality of IC chips and an area for a wiring region for connecting these terminals need not be secured on a mounting substrate. There is a problem that must not be.
【０００９】本発明の目的は、上記課題を解決して複数
のＩＣチップを少ない実装基板上の面積に配置して配線
することが可能な半導体集積回路を提供することにあ
る。An object of the present invention is to provide a semiconductor integrated circuit capable of solving the above-mentioned problems and arranging and wiring a plurality of IC chips in a small area on a mounting board.
【００１０】[0010]
【課題を解決するための手段】上記の目的を達成するた
めに本発明の半導体集積回路は、実装基板４の第１の端
子２１、第２の端子２２と、第１のＩＣチップ１の第１
の端子１１、第２の端子１２とをそれぞれ向かい合わせ
て接続する発熱量の少ない第１のＩＣチップ１と、第１
のＩＣチップ１の背面と第２のＩＣチップ２の背面を接
着して第２のＩＣチップ２の第１の端子１３を実装基板
４の第３の端子２３に接続して、且つ第１のＩＣチップ
１の背面と第３のＩＣチップ３の背面を接着して第３の
ＩＣチップの第１の端子１４を実装基板４の第４の端子
２４に接続することを特徴とする。In order to achieve the above object, a semiconductor integrated circuit according to the present invention comprises a first terminal 21, a second terminal 22 of a mounting substrate 4, and a first terminal 21 of a first IC chip 1. 1
A first IC chip 1 having a small amount of heat and connecting the first terminal 11 and the second terminal 12 to face each other;
The first terminal 13 of the second IC chip 2 is connected to the third terminal 23 of the mounting substrate 4 by bonding the back surface of the IC chip 1 and the back surface of the second IC chip 2 to each other. The back surface of the IC chip 1 and the back surface of the third IC chip 3 are bonded to connect the first terminal 14 of the third IC chip to the fourth terminal 24 of the mounting board 4.
【００１１】また、本発明の半導体集積回路は、第１の
ＩＣチップ１の背面と実装基板４の第５の端子２５とを
ワイヤーで接続してこれを接地電位に接続し、第２のＩ
Ｃチップ２の第２の端子１５と、第３のＩＣチップ３の
第２の端子１６とを直接ワイヤーで接続することを特徴
とする。Further, in the semiconductor integrated circuit of the present invention, the back surface of the first IC chip 1 and the fifth terminal 25 of the mounting substrate 4 are connected by a wire, and this is connected to the ground potential.
The second terminal 15 of the C chip 2 and the second terminal 16 of the third IC chip 3 are directly connected by a wire.
【００１２】[0012]
【発明の実施の形態】実装基板４の第１の端子２１、第
２の端子２２と、第１のＩＣチップ１の第１の端子１
１、第２の端子１２とをそれぞれ向かい合わせて接続す
る発熱量の少ない第１のＩＣチップ１と、第１のＩＣチ
ップ１の背面と第２のＩＣチップ２の背面を接着して第
２のＩＣチップ２の第１の端子１３を実装基板４の第３
の端子２３に接続して、且つ第１のＩＣチップ１の背面
と第３のＩＣチップ３の背面を接着して第３のＩＣチッ
プの第１の端子１４を実装基板４の第４の端子２４に接
続し、また、第１のＩＣチップ１の背面と実装基板４の
第５の端子２５とをワイヤーで接続してこれを接地電位
に接続し、第２のＩＣチップ２の第２の端子１５と、第
３のＩＣチップ３の第２の端子１６とを直接ワイヤーで
接続することを特徴とする半導体集積回路の実装方法。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first terminal 21 and a second terminal 22 of a mounting substrate 4 and a first terminal 1 of a first IC chip 1 are described.
A first IC chip 1 that generates a small amount of heat for connecting the first and second terminals 12 to face each other and a back surface of the first IC chip 1 and a back surface of the second IC chip 2, The first terminal 13 of the IC chip 2
And the back surface of the first IC chip 1 and the back surface of the third IC chip 3 are adhered to each other to connect the first terminal 14 of the third IC chip to the fourth terminal of the mounting board 4. 24, and the back surface of the first IC chip 1 and the fifth terminal 25 of the mounting substrate 4 are connected by a wire, and this is connected to the ground potential, and the second terminal of the second IC chip 2 is connected to the ground. A method for mounting a semiconductor integrated circuit, wherein the terminal 15 and the second terminal 16 of the third IC chip 3 are directly connected by a wire.
【００１３】[0013]
【実施例】図１は本発明の半導体集積回路の構成を示す
実装基板上面から見た図である。また、図２は本発明の
半導体集積回路の構成を示す実装基板横面から見た図で
ある。図１および図２を用いて本発明の半導体集積回路
の構成を説明する。本発明の半導体集積回路は第１のＩ
Ｃチップ１と第２のＩＣチップ２と第３のＩＣチップ３
と実装基板４とで構成している。FIG. 1 is a diagram showing the configuration of a semiconductor integrated circuit according to the present invention as viewed from the top of a mounting substrate. FIG. 2 is a diagram showing the configuration of the semiconductor integrated circuit according to the present invention as viewed from the side of a mounting substrate. The configuration of the semiconductor integrated circuit of the present invention will be described with reference to FIGS. The semiconductor integrated circuit of the present invention has a first I
C chip 1, second IC chip 2, and third IC chip 3
And the mounting board 4.
【００１４】第１のＩＣチップ１は実装基板４上に背面
を上にしてそれぞれの端子が向かい合うように配置す
る。向かい合っている第１のＩＣチップ１の第１の端子
１１と実装基板４の第１の端子２１とを実装バンプ等で
接続し、第１のＩＣチップ１の第２の端子１２と実装基
板４の第２の端子２２とを実装バンプ等で接続する。The first IC chip 1 is disposed on a mounting board 4 such that the terminals face each other with the back face up. The facing first terminal 11 of the first IC chip 1 and the first terminal 21 of the mounting board 4 are connected by mounting bumps or the like, and the second terminal 12 of the first IC chip 1 and the mounting board 4 are connected. Is connected to the second terminal 22 by a mounting bump or the like.
【００１５】第２のＩＣチップ２は第１のＩＣチップ１
の背面上に端子が上面となるように配置する。第２のＩ
Ｃチップ２の第１の端子１３と実装基板４の第３の端子
２３とを第１のワイヤー３３で接続する。The second IC chip 2 is the first IC chip 1
Are arranged on the back surface of the device such that the terminals face upward. Second I
The first terminal 13 of the C chip 2 and the third terminal 23 of the mounting board 4 are connected by a first wire 33.
【００１６】第３のＩＣチップ３は第１のＩＣチップ１
の背面上に端子が上面となるように配置する。第３のＩ
Ｃチップ３の第１の端子１４と実装基板４の第４の端子
２４とを第２のワイヤー３４で接続する。The third IC chip 3 is the first IC chip 1
Are arranged on the back surface of the device such that the terminals face upward. Third I
The first terminal 14 of the C chip 3 and the fourth terminal 24 of the mounting board 4 are connected by a second wire 34.
【００１７】第１のＩＣチップ１は、背面に第２のＩＣ
チップ２および第３のＩＣチップ３を接続しても発熱に
よるＩＣの誤動作が起こらない程度に少ない発熱量のＩ
Ｃとする。The first IC chip 1 has a second IC chip
Even if the chip 2 and the third IC chip 3 are connected, a small amount of heat is generated so that the IC does not malfunction due to heat.
C.
【００１８】同一信号である第２のＩＣチップ２の第２
の端子１５と第３のＩＣチップ３の第２の端子１６を第
３のワイヤー３５で接続する。The second signal of the second IC chip 2 having the same signal
And the second terminal 16 of the third IC chip 3 are connected by a third wire 35.
【００１９】実装基板４の第１の端子２１と実装基板４
の第３の端子２３と実装基板４の第４の端子２４とを実
装基板４上の配線４１で接続する。First terminal 21 of mounting substrate 4 and mounting terminal 4
The third terminal 23 and the fourth terminal 24 of the mounting board 4 are connected by the wiring 41 on the mounting board 4.
【００２０】本発明の半導体集積回路では第１のＩＣチ
ップの上に第２のＩＣチップと第３のＩＣチップを載せ
ることで、実装基板４上面から見たＩＣチップ３個の占
める面積を大幅に減少している。In the semiconductor integrated circuit of the present invention, by mounting the second IC chip and the third IC chip on the first IC chip, the area occupied by the three IC chips viewed from the upper surface of the mounting substrate 4 is greatly increased. Has decreased.
【００２１】また、本発明の半導体集積回路では第２の
ＩＣチップ２の第２の端子１５と第３のＩＣチップ３の
第２の端子１６を第３のワイヤー３５で接続することで
実装基板４上の配線が占める面積を大幅に減少してい
る。Further, in the semiconductor integrated circuit of the present invention, the second terminal 15 of the second IC chip 2 and the second terminal 16 of the third IC chip 3 are connected by the third wire 35, so that the mounting substrate 4, the area occupied by the wiring on the substrate 4 is greatly reduced.
【００２２】また、第１のＩＣチップ１の背面上の任意
の点１７と実装基板４の第５の端子２５をワイヤー３６
で接続する。これにより第１のＩＣチップ１の背面の電
位を実装基板４から設定することが可能となる。Also, an arbitrary point 17 on the back surface of the first IC chip 1 and the fifth terminal 25 of the mounting substrate 4 are connected to a wire 36.
Connect with. As a result, the potential on the back surface of the first IC chip 1 can be set from the mounting substrate 4.
【００２３】また、第１のＩＣチップ１の背面上の任意
の点１７と実装基板４の第５の端子２５をワイヤー３６
で接続してこれを接地電位に接続する。これにより第１
のＩＣチップ１の背面の電位は安定な接地電位となり第
１のＩＣ１と第２のＩＣ２、第３のＩＣ３との間での電
気的干渉を排除することが可能となる。Further, an arbitrary point 17 on the back surface of the first IC chip 1 and the fifth terminal 25 of the mounting board 4 are connected to a wire 36.
And connect it to ground potential. This makes the first
The potential on the back surface of the IC chip 1 becomes a stable ground potential, and electrical interference between the first IC 1, the second IC 2, and the third IC 3 can be eliminated.
【００２４】[0024]
【発明の効果】上記記載の本発明の半導体集積回路によ
れば、実装基板上に複数のＩＣチップを少ない面積の実
装基板に配置することが可能である。According to the semiconductor integrated circuit of the present invention described above, it is possible to arrange a plurality of IC chips on a mounting board having a small area on the mounting board.
【図１】本発明の半導体集積回路の構成を示す上面から
見た図である。FIG. 1 is a diagram illustrating a configuration of a semiconductor integrated circuit according to the present invention as viewed from above.
【図２】本発明の半導体集積回路を構成を示す横方向か
ら見た図である。FIG. 2 is a diagram showing a configuration of a semiconductor integrated circuit of the present invention as viewed from a lateral direction.
【図３】従来例の半導体集積回路の構成を示す図であ
る。FIG. 3 is a diagram showing a configuration of a conventional semiconductor integrated circuit.
１ 第１のＩＣチップ ２ 第２のＩＣチップ ３ 第３のＩＣチップ ４ 実装基板 １１ 第１のＩＣチップの第１の端子 １２ 第１のＩＣチップの第２の端子 １３ 第２のＩＣチップの第１の端子 １４ 第３のＩＣチップの第１の端子 １５ 第２のＩＣチップの第２の端子 １６ 第３のＩＣチップの第２の端子 １７ 第１のＩＣチップの背面上の任意の点 ２１ 実装基板上の第１の端子 ２２ 実装基板上の第２の端子 ２３ 実装基板上の第３の端子 ２４ 実装基板上の第４の端子 ２５ 実装基板上の第５の端子 ３３、３４、３５、３６ ワイヤー DESCRIPTION OF SYMBOLS 1 1st IC chip 2 2nd IC chip 3 3rd IC chip 4 Mounting board 11 1st terminal of 1st IC chip 12 2nd terminal of 1st IC chip 13 2nd IC chip 1st terminal 14 1st terminal of 3rd IC chip 15 2nd terminal of 2nd IC chip 16 2nd terminal of 3rd IC chip 17 Any point on the back of the 1st IC chip DESCRIPTION OF SYMBOLS 21 1st terminal on mounting board 22 2nd terminal on mounting board 23 3rd terminal on mounting board 24 4th terminal on mounting board 25 5th terminal on mounting board 33,34,35 , 36 wires
Claims (3)
子２２と、第１のＩＣチップ１の第１の端子１１、第２
の端子１２とをそれぞれ向かい合わせて接続する発熱量
の少ない第１のＩＣチップ１と、第１のＩＣチップ１の
背面と第２のＩＣチップ２の背面を接着して第２のＩＣ
チップ２の第１の端子１３を実装基板４の第３の端子２
３に接続して、且つ第１のＩＣチップ１の背面と第３の
ＩＣチップ３の背面を接着して第３のＩＣチップの第１
の端子１４を実装基板４の第４の端子２４に接続するこ
とを特徴とする半導体集積回路の実装方法。1. A first terminal 21 and a second terminal 22 of a mounting substrate 4 and a first terminal 11 and a second terminal
A first IC chip 1 having a small amount of heat to be connected to each of the terminals 12 facing each other, and a back surface of the first IC chip 1 and a back surface of the second IC chip 2 are bonded to each other to form a second IC chip.
The first terminal 13 of the chip 2 is connected to the third terminal 2 of the mounting board 4.
3 and bonding the back surface of the first IC chip 1 and the back surface of the third IC chip 3 to the first IC chip 1
The method of mounting a semiconductor integrated circuit according to claim 1, wherein the terminal (14) is connected to the fourth terminal (24) of the mounting substrate (4).
て、第１のＩＣチップ１の背面と実装基板４の第５の端
子２５とをワイヤーで接続することを特徴とする半導体
集積回路の実装方法。2. The method of mounting a semiconductor integrated circuit according to claim 1, wherein the back surface of the first IC chip and the fifth terminal of the mounting substrate are connected by wires.
て、第１のＩＣチップ１の背面と実装基板４の第５の端
子２５とをワイヤーで接続してこれを接地電位に接続す
ることを特徴とする半導体集積回路の実装方法。3. The method of mounting a semiconductor integrated circuit according to claim 2, wherein the back surface of the first IC chip 1 and the fifth terminal 25 of the mounting substrate 4 are connected by a wire and connected to a ground potential. Semiconductor integrated circuit mounting method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP834697A JPH10209369A (en) | 1997-01-21 | 1997-01-21 | Packaging method of semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP834697A JPH10209369A (en) | 1997-01-21 | 1997-01-21 | Packaging method of semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10209369A true JPH10209369A (en) | 1998-08-07 |
Family
ID=11690666
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP834697A Pending JPH10209369A (en) | 1997-01-21 | 1997-01-21 | Packaging method of semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10209369A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1187210A3 (en) * | 2000-09-07 | 2005-03-02 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
-
1997
- 1997-01-21 JP JP834697A patent/JPH10209369A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1187210A3 (en) * | 2000-09-07 | 2005-03-02 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7812436B2 (en) | Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice | |
| US6232148B1 (en) | Method and apparatus leads-between-chips | |
| US6091143A (en) | Stacked leads-over chip multi-chip module | |
| US6376914B2 (en) | Dual-die integrated circuit package | |
| US6208018B1 (en) | Piggyback multiple dice assembly | |
| US6611434B1 (en) | Stacked multi-chip package structure with on-chip integration of passive component | |
| US20070048903A1 (en) | Multi-chip package type semiconductor device | |
| US20020140070A1 (en) | Packaging system for die-up connection of a die-down oriented integrated circuit | |
| EP0782191A2 (en) | Multi-level stacked integrated-circuit-chip assembly | |
| KR20020062820A (en) | Semiconductor device having stacked multi chip module structure | |
| US20020000652A1 (en) | Board on chip ball grid array | |
| JPH08504060A (en) | Module for an IC microprocessor, including an IC memory stack structurally combined with the IC microprocessor | |
| US6340839B1 (en) | Hybrid integrated circuit | |
| JP2001156251A (en) | Semiconductor device | |
| US6682954B1 (en) | Method for employing piggyback multiple die #3 | |
| US5559305A (en) | Semiconductor package having adjacently arranged semiconductor chips | |
| US6590297B2 (en) | Semiconductor chip having pads with plural junctions for different assembly methods | |
| WO1996004682A1 (en) | Electronic circuit package | |
| US6495910B1 (en) | Package structure for accommodating thicker semiconductor unit | |
| JPH10209369A (en) | Packaging method of semiconductor integrated circuit | |
| US20070267756A1 (en) | Integrated circuit package and multi-layer lead frame utilized | |
| US6984882B2 (en) | Semiconductor device with reduced wiring paths between an array of semiconductor chip parts | |
| JPH10200062A (en) | Semiconductor device | |
| JP2002237567A (en) | Semiconductor device | |
| KR20050027384A (en) | Chip size package having rerouting pad and stack thereof |