JPH10190453A - Differential charge pump circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correct the error of first and second currents for charging a capacitor means and to control and equalize both currents by providing two detection means for detecting the currents respectively flowing to both ends of the capacitor means, negatively feeding back and amplifying the difference voltage of the output and adding it to a negative feedback amplification means. SOLUTION: By first and second current detection circuits Q3 and Q14, the current ratio of third and forth emitter-followers Q2 and Q13 is detected. Input is performed through fifth and sixth emitter-followers Q6 and Q9 to the differential pairs Q7 and Q8 of a negative feedback amplifier circuit. The collectors of the differential pair are connected to first and third resistors R1 and R3 and the output of the negative feedback amplifier circuit is added to the output of the feedback amplifier circuit of a gain 1. The gain of the negative feedback amplifier circuit is decided by the current value I of a current source 16 and the resistance value R of the first and third resistors R1 and R3. Thus, an operation is performed without changing the characteristics of a system from a minute current to the maximum current value of a transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential charge pump circuit having a storage means charged by a first current (attack current) and a second current (recovery current).
In particular, a differential charge pump circuit capable of controlling the currents flowing through both ends of the power storage means to be equal to correct an error between a first current (attack current) and a second current (recovery current) for charging the power storage means. About.

[0002]

2. Description of the Related Art FIG. 3 shows a circuit diagram of a conventional differential charge pump circuit. In the figure, a differential charge pump circuit of the conventional example roughly includes a power supply V1 for supplying a power supply potential VCC, a capacitor C1 (capacitance C) charged by an attack current and a recovery current, and a capacitor C1.
Transistors Q4 and Q11 for inputting the voltage between both ends of the first and second transistors to the base via the first and second emitter followers, respectively, and the first and second transistors Q4
And third and fourth emitter followers for supplying the collector outputs of Q11 and Q11 to both ends of the capacitor C1, respectively, and a feedback amplifier circuit for feedback-amplifying the difference voltage between both ends of the capacitor C1 and biasing the capacitor C1. It is configured.

A first emitter follower has a base connected to a first terminal N1 of a capacitor C1, and a collector connected to a power supply potential VC.
C, an NPN transistor Q1 having an emitter connected to a second current source I2 (current value I), and a base connected to a PNP transistor Q1.
The collector of the transistor Q1 is connected to the ground potential G.
The ND includes a PNP transistor P1 having an emitter connected to the first current source I1 (current value I).

A second emitter follower has a base connected to the second terminal N2 of the capacitor C1, and a collector connected to the power supply potential VC.
C, an NPN transistor Q16 having an emitter connected to the tenth current source I10 (current value I), a base connected to the emitter of the PNP transistor Q16, a collector connected to the ground potential GND, and an emitter connected to the eleventh current source I11 (current value I). I) and a PNP transistor P2 connected to each of them.

The feedback amplifier circuit has a base connected to the emitter of the PNP transistor P1 and a collector connected to the first resistor R1.
One terminal of (resistance value R) is connected to the fourth current source I
4 (current value I), the first transistor (NPN transistor) Q4, the base is connected to the emitter of the PNP transistor P2, the collector is connected to one terminal of the third resistor R3 (resistance R), and the emitter is connected to the third terminal. 8 current source I8
(Current value I), a second transistor (NPN transistor) Q11, an NPN transistor Q5 having a base and a collector connected to the power supply potential VCC, an emitter connected to the other terminal of the first resistor R1, a base and a collector, respectively. The collector is set to the power supply potential VCC, and the emitter is set to the third
An NPN transistor Q10 connected to the other terminal of the resistor R3, first and third resistors R1 and R3, one as the emitter of the NPN transistor Q4, and the other as NP
And a second resistor R2 (resistance 2R) connected to the emitter of the N-transistor Q11.

The third emitter follower has a base at the collector of an NPN transistor (first transistor) Q4, a collector at a power supply potential VCC, and an emitter at N4.
This is realized by NPN transistors Q13 connected to a ninth current source I9 (current value is an attack current Iat) via a PN transistor Q12, and the fourth emitter follower has a base connected to the collector of an NPN transistor (second transistor) Q11. To the power supply potential VCC
And an NPN transistor Q2 having an emitter connected to a third current source I3 (current value is a recovery current Idec).
Has been realized.

Further, in the conventional differential charge pump circuit, the base is connected to the signal ATK_H, the collector is connected to the second terminal N2 of the capacitor C1, and the emitter is connected to the ninth current source I9. An NPN transistor Q12 which is turned on at H level, a base connected to the signal ATK_L, a collector connected to the power supply potential VCC, and an emitter connected to the ninth current source I9,
N that is turned on when signal ATK_H is at “L” level
And a PN transistor Q15.

In the above configuration, in the conventional differential charge pump circuit, the capacitor C1 is charged by the attack current Iat of the ninth current source I9 and the recovery current Idec of the third current source I3.

The voltage across the capacitor C1 is divided into first and second emitter followers Q1, P1 and Q16,
Via P2, the first and second transistors Q4 and Q4
11 and a feedback amplifier circuit composed of first, second and third resistors R1, R2 and R3. The gain of this differential amplifier circuit is about one, and the output of this differential amplifier circuit is connected to both ends of the capacitor C1 via third and fourth emitter followers Q2 and Q13.

[0010]

In the above conventional differential charge pump circuit, if the base-emitter voltages VBE of the NPN transistors Q2 and Q13 forming the third and fourth emitter followers are equal, the NPN transistor Q2 and the The current shunted equally to Q13 and flowing into the capacitor C1 is exactly half the current of the attack current or the recovery current flowing from one of its terminals. However, in practice, the NPN transistors Q2 and Q13
The base-emitter voltage VBE of
The current flowing through the NPN transistors Q2 and Q13 deviates from 1: 1. In particular, when the voltage between both ends of the capacitor C1 increases, the effect of the gain error increases, and an error occurs in the current value flowing through the capacitor C1.

Considering quantitatively, if there is a difference between the base-emitter voltages VBE of a pair of emitter followers (NPN transistors Q2 and Q13) biasing the capacitor C1, the ratio of the current flowing through each of them becomes ΔVBE. Base-emitter voltage VBE of NPN transistors Q2 and Q13
When the differences I1 and I2 are current values flowing through the NPN transistors Q2 and Q13, respectively, the following equation is obtained. I2 / I1 = exp (ΔVBE / VT)

In the above-described conventional differential charge pump circuit, I2 / I1 ≠ 1 due to a gain error of a feedback amplifier circuit (1x gain) for biasing the capacitor C1.
As a result, a large error occurs in the current values of the attack current and the recovery current flowing through the capacitor C1. This error depends on the voltage VCAP across the capacitor C1,
It changes depending on the gain error ΔG of the feedback amplifier circuit, and as is clear from the block diagram of FIG. 4, ΔVBE = VCAP × Δ
Therefore, when the potential difference between both ends of the capacitor C1 increases, the error of I2 / I1 becomes a magnitude that cannot be ignored.

The present invention has been made in view of the above-mentioned conventional circumstances, and has a first current (attack current) and a second current (attack current).
In the differential charge pump circuit including the power storage means charged by the current (recovery current), the first current (attack current) for charging the power storage means by controlling the currents flowing through both ends of the power storage means to be equal. It is another object of the present invention to provide a differential charge pump circuit capable of correcting an error of a second current (recovery current).

[0014]

In order to solve the above-mentioned problems, a differential charge pump circuit according to the present invention comprises a storage means charged by a first current and a second current; A differential charge pump circuit comprising feedback amplification means for feedback-amplifying a difference voltage and biasing the power storage means, wherein two current detection means for detecting currents flowing through both ends of the power storage means, Negative feedback amplification means for performing negative feedback amplification of the difference voltage between the outputs of the two current detection means and adding the difference voltage to the output of the feedback amplification means.

Further, the differential charge pump circuit according to the present invention comprises a power storage means charged by a first current and a second current, and a voltage across the power storage means having first and second emitter followers respectively. First and second transistors input to a base via the first and second transistors, and third and fourth emitter followers for supplying collector outputs of the first and second transistors to both ends of the power storage means, respectively. And a feedback amplifying means for feedback-amplifying a difference voltage between both ends of the charge-feeding means and biasing the storage means, wherein a difference between a base-emitter voltage of the third and fourth emitter followers is determined. Voltage detection means for detection and a difference voltage by the voltage detection means are input between the bases of the two via fifth and sixth emitter followers, respectively. A third transistor that supplies an output to the third and fourth emitter followers; a negative feedback that amplifies the difference voltage detected by the voltage detection unit in a negative feedback manner and adds the difference voltage to an output of the feedback amplification unit; Amplifying means.

Further, the differential charge pump circuit according to the present invention comprises a storage means charged by a first current and a second current, and a first and a second emitter follower which respectively determine a voltage between both ends of the storage means. First and second transistors input to a base via the first and second transistors, and third and fourth emitter followers for supplying collector outputs of the first and second transistors to both ends of the power storage means, respectively. And a feedback amplifier means for feedback-amplifying the difference voltage between both ends of the power supply means and biasing the power storage means, wherein the two current-detecting circuits detect currents flowing through the third and fourth emitter followers, respectively. Current detecting means;
The outputs of the two current detecting means are respectively referred to as fifth and sixth outputs.
A third transistor and a fourth transistor, respectively, which are inputted to a base via an emitter follower of the above and supply respective collector outputs to the third and fourth emitter followers.
Negative feedback amplification means for negative feedback amplifying the difference voltage between the outputs of the current detection means and adding the difference voltage to the output of the feedback amplification means.

In the differential charge pump circuit according to the present invention, the negative feedback amplifying means includes a current source connected to emitters of the third and fourth transistors, and a collector of the third and fourth transistors. And a first resistor and a second resistor connected to the first and second resistors, and a negative feedback amplification factor of the negative feedback amplifier is determined by a current value of the current source and a resistance value of the first and second resistors. It is.

In the differential charge pump circuit according to the present invention, the power storage means is charged by the first current (attack current) and the second current (recovery current), and essentially constitutes third and fourth emitter followers. If the base-emitter voltage VBE of the transistor to be operated is equal, the current shunts equally to each transistor, and the current flowing to the storage means should flow exactly 1/2 of the attack current or recovery current flowing from any of its terminals. However, in practice, the base-emitter voltage VBE of each transistor does not become exactly equal due to the offset and gain error of the differential amplifier circuit, and the current value flowing through both transistors deviates from 1: 1.

Therefore, in the differential charge pump circuit according to the present invention, the current ratio of the third and fourth emitter followers is detected by the current detecting means, or the third ratio is detected by the voltage detecting means.
And the difference between the base-emitter voltages of the fourth and fourth emitter followers is detected and input to the differential pair (third and fourth transistors) of the negative feedback amplifier through the fifth and sixth emitter followers. By connecting the collector of the differential pair to the first and second resistors, the differential voltage detected by the voltage detecting means or the current detecting means is negatively amplified and added to the output of the feedback amplifying means. .

Here, the difference voltage between the emitters of the voltage detecting means or the current detecting means depends only on the current ratio without depending on the collector currents of the third and fourth emitter followers. And the first and second resistors. Therefore, the fifth and sixth emitter followers can be operated without changing the characteristics of the system at a current value in a range from a very small current that is negligible to the maximum current capability of the transistor. An error between the first current (attack current) and the second current (recovery current) can be corrected.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the differential charge pump circuit according to the present invention will be described below in detail with reference to the drawings.

[Embodiment] FIG. 1 is a configuration diagram of a differential charge pump circuit according to an embodiment of the present invention. In the figure, the same reference numerals are given to portions overlapping with FIG. 3 (conventional example).

Referring to FIG. 1, a differential charge pump circuit according to the present embodiment includes a power supply V1 for supplying a power supply potential VCC, a capacitor C1 (capacitance C) charged by an attack current and a recovery current, and a capacitor. C1
Transistors Q4 and Q11 for inputting the voltage between both ends of the first and second transistors to the base via the first and second emitter followers, respectively, and the first and second transistors Q4
A third and a fourth emitter follower for respectively supplying the collector output of Q1 and Q11 to both ends of a capacitor C1, a feedback amplifier circuit for feedback-amplifying a difference voltage between both ends of the capacitor C1 and biasing the capacitor C1, First and second current detection circuits for detecting currents flowing through the fourth and fourth emitter followers, and outputs of the first and second current detection circuits to a base via fifth and sixth emitter followers, respectively. And third and fourth transistors for inputting and supplying respective collector outputs to third and fourth emitter followers, and a negative feedback amplification of a difference voltage between outputs of the first and second current detection circuits. And a negative feedback amplifier circuit for adding to the output of the feedback amplifier circuit.

The first emitter follower has a base connected to the first terminal N1 of the capacitor C1 and a collector connected to the power supply potential VC.
C, and N having an emitter connected to the second current source I2, respectively.
A PN transistor Q1, a PNP transistor P1 having a base connected to the emitter of the PNP transistor Q1, a collector connected to the ground potential GND, and an emitter connected to the first current source I1, respectively, and first and second current sources I1 (current value I) And I2 (current value I).

The second emitter follower has a base connected to the second terminal N2 of the capacitor C1, and a collector connected to the power supply potential VC.
C, an NPN transistor Q16 having an emitter connected to the tenth current source I10, a base connected to the emitter of the PNP transistor Q16, and a collector connected to the ground potential GND.
A PNP transistor P2 having an emitter connected to the eleventh current source I11, and a tenth and eleventh current source I
10 (current value I) and I10 (current value I).

The feedback amplifier circuit has a base connected to the emitter of the PNP transistor P1 and a collector connected to the first resistor R1.
One terminal of (resistance value R) is connected to the fourth current source I
4, a first transistor (NPN transistor) Q4, a base connected to the emitter of the PNP transistor P2, a collector connected to one terminal of the third resistor R3 (resistance value R), and an emitter connected to the eighth current source I8. Second transistors (NPN transistors) Q11 connected to each other
The fourth and eighth current sources I4 (current value I) and I8 (current value I), and the base and collector to the power supply potential VCC,
An NPN transistor Q5 having an emitter connected to the other terminal of the first resistor R1, an NPN transistor Q10 having a base and collector connected to the power supply potential VCC, and an emitter connected to the other terminal of the third resistor R3, respectively;
And third resistors R1 and R3, one of which is the emitter of NPN transistor Q4 and the other of which is NPN transistor Q11.
The second resistor R2 (resistance 2
R).

The third emitter follower has a base at the collector of the NPN transistor (first transistor) Q4, a collector at the power supply potential VCC, and an emitter at N4.
An NPN transistor Q13 connected to a ninth current source I9 via a PN transistor Q12 and a ninth current source I9 (current value is an attack current Iat) are realized, and a fourth emitter follower has an NPN transistor ( An NPN transistor Q2 having a collector connected to the power supply potential VCC, an emitter connected to the third current source I3, and a third current source I2.
3 (the current value is the recovery current Idec).

The first current detection circuit is realized by an NPN transistor Q3 whose base and collector are connected to the power supply potential VCC and whose emitter is connected to the collector of an NPN transistor (third emitter follower) Q2, respectively. The circuit uses the power supply potential VCC for the base and collector.
The NPN transistor Q14 has an emitter connected to the collector of an NPN transistor (fourth emitter follower) Q13, and detects currents flowing through the third and fourth emitter followers Q2 and Q14, respectively.

The fifth emitter follower connects the base to the first
Of the current detection circuit (NPN transistor) Q3, the collector to the power supply potential VCC, and the emitter to the fifth
NPN transistors Q6 respectively connected to the current source I5
And a fifth current source I5 (current value I).
The sixth emitter follower has a base at the emitter output of the second current detection circuit (NPN transistor) Q14, a collector at the power supply potential VCC, and an emitter at the seventh current source I7.
, And a seventh current source I7 (current value I), and supplies the outputs of the first current detection circuit Q3 and the second current detection circuit Q14 to the feedback amplifier circuit. .

The negative feedback amplifier circuit has a base connected to the emitter of a fifth emitter follower (NPN transistor) Q6,
The collector is connected to one terminal of the capacitor C2, the emitter is connected to a third transistor (NPN transistor) Q7 whose emitter is connected to the sixth current source I6, and the base is connected to the emitter of a sixth emitter follower (NPN transistor) Q9.
A fourth transistor (NPN transistor) Q8 having a collector connected to the other terminal of the capacitor C2 and an emitter connected to the sixth current source I6, a capacitor C2 (capacitance C), and a sixth current source I6 (current value I6). ). The collector outputs of the third and fourth transistors Q7 and Q8 are connected to the collectors of the first and second transistors Q4 and Q11, respectively, which are the outputs of the feedback amplifier circuit. The differential voltage between the outputs of the detection circuits Q3 and Q14 is subjected to negative feedback amplification and added to the output of the feedback amplifier circuit.

Further, in the differential charge pump circuit of this embodiment, the base is connected to the signal ATK_H, the collector is connected to the second terminal N2 of the capacitor C1, and the emitter is connected to the ninth current source I9. The NPN transistor Q12, which is turned on when the signal is at H level, the base is connected to the signal ATK_L, the collector is connected to the power supply potential VCC, the emitter is connected to the ninth current source I9, and the signal ATK_H is at the "L" level. An NPN transistor Q15 which is turned on at the time.

In the configuration as described above, in the differential charge pump circuit of the present embodiment, the capacitor C1 is
It is charged by the attack current Iat of the current source I9 and the recovery current Idec of the third current source I3.

The voltage across the capacitor C1 is equal to the first and second emitter followers Q1, P1 and Q16,
Via P2, the first and second transistors Q4 and Q4
11 and a feedback amplifier circuit composed of first, second and third resistors R1, R2 and R3. The gain of this differential amplifier circuit is about one, and the output of this differential amplifier circuit is connected to both ends of the capacitor C1 via third and fourth emitter followers Q2 and Q13.

The bases of the NPN transistors Q2 and Q13 which originally constitute the third and fourth emitter followers
If the emitter voltages VBE are equal, the NPN transistor Q
2 and Q13, the current flowing through the capacitor C1 should be exactly 1/2 of the attack current or the recovery current flowing from any of its terminals. , The base-emitter voltages VBE of the NPN transistors Q2 and Q13 are not exactly equal, and the current flowing through the NPN transistors Q2 and Q13 deviates from 1: 1.

In the differential charge pump circuit of this embodiment, the first and second current detection circuits Q3 and Q14 detect the current ratio between the third and fourth emitter followers (NPN transistors) Q2 and Q13, Fifth and sixth
Emitter followers (NPN transistors) Q6 and Q
9 and is input to a differential pair (third and fourth transistors (NPN transistors) Q7 and Q8) of the negative feedback amplifier circuit. The collector of this differential pair has first and third resistors R
1 and R3, and the output of the negative feedback amplifier circuit is added to the output of the feedback amplifier circuit having a gain of 1.

The first and second current detection circuits Q3 and Q1
Since the differential voltage of the emitter No. 4 does not depend on the collector currents Ic of the third and fourth emitter followers (NPN transistors) Q2 and Q13, but depends only on the current ratio, the gain of the negative feedback amplifier circuit is the current value of the current source I6. I and the resistance R of the first and third resistors R1 and R3.

Therefore, the characteristic of the system is changed by a current value in a range from a very small current where the base currents of the fifth and sixth emitter followers (NPN transistors) Q6 and Q9 can be ignored to the maximum current capability of the transistors. It is possible to operate without making it operate. In addition, the number of elements can be reduced to about 6 transistors and 3 current sources compared to the conventional example (see FIG. 3), which is economical.

FIG. 2 is a block diagram functionally explaining the operation of the differential charge pump circuit according to the present embodiment. In the figure, ΔVBE is the difference between the base-emitter voltages VBE of the third and fourth emitter followers (NPN transistors) Q2 and Q13, VCAP is the voltage across the capacitor C1, and ΔG is the gain of the feedback amplifier circuit. And K is the gain of the negative feedback amplifier circuit.

From FIG. 2, (1 + ΔG) VCAP−K · ΔVBE−VCAP = ΔVBE∴ΔG · VCAP = (1 + K) · ΔVBE ΔVBE = ΔG · VCAP / (1 + K) According to the above equation, if the gain K of the negative feedback amplifier circuit is sufficiently large, the third and fourth emitter followers (NP
It has been quantitatively proved that the difference .DELTA.VBE between the base-emitter voltages VBE of the (N-transistor) Q2 and Q13 can be made substantially zero.

As described above, according to the differential charge pump circuit of the present embodiment, the NPN transistors Q2 and Q2
13, the base-emitter voltage VBE is not exactly equal, and the current flowing through the NPN transistors Q2 and Q13 deviates from 1: 1.

That is, in the differential charge pump circuit of the present embodiment, the third and fourth emitter followers Q2 and Q13 are provided by the first and second current detection circuits Q3 and Q14.
And the fifth and sixth emitter followers Q
6 and Q9, the differential pair (third and fourth transistors Q7 and Q8) of the negative feedback amplifier circuit is input, and the collector of this differential pair is connected to the first and third resistors R1 and R3. Thus, the differential voltage detected by the current detecting means is negatively feedback-amplified and added to the output of the gain-amplified feedback amplifier circuit.

As a result, the differential voltage between the emitters of the first and second current detection circuits Q3 and Q14 is determined only by the current ratio without depending on the collector currents Ic of the third and fourth emitter followers Q2 and Q13. Since the gain of the negative feedback amplifier is determined by the current value I of the current source I6 and the resistance value R of the first and third resistors R1 and R3, the base currents of the fifth and sixth emitter followers Q6 and Q9 can be ignored. The operation can be performed without changing the characteristics of the system at a current value in a range from a very small current up to the maximum to the maximum current capability of the transistor. As a result, the first current (attack current) and the second current ( The error of the recovery current can be corrected.

[0043]

As described above, according to the differential charge pump circuit of the present invention, the first current (attack current) for charging the power storage means is controlled by making the currents flowing through both ends of the power storage means equal. ) And the second current (recovery current)
Can be provided.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a differential charge pump circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram functionally describing the operation of the differential charge pump circuit according to the embodiment.

FIG. 3 is a circuit diagram of a conventional differential charge pump circuit.

FIG. 4 is a block diagram functionally explaining the operation of a conventional differential charge pump circuit. It is.

[Explanation of symbols]

V1: power supply, VCC: power supply potential, GND: ground potential, C
1, C2: capacitor (capacity value C), N1: first terminal of capacitor C1, N2: second terminal of capacitor C1, R
1, R3: resistance (resistance value R), R2: resistance (resistance value 2)
R), Q1-Q16 ... NPN transistors, P1, P2
... PNP transistors, I1 to I11 ... Current sources, Q4 ...
First transistor, Q11... Second transistor, Q
7: third transistor, Q8: fourth transistor,
Q1, P1, I1, I2... First emitter follower, Q
16, P2, I10, I11: second emitter follower, Q2: third emitter follower, Q13: fourth emitter follower, Q6: fifth emitter follower, Q9
... Sixth emitter follower, Iat ... Attack current, I
dec: recovery current, Q3: first current detection circuit, Q
14... Second current detection circuit, ATK_H, ATK_L.
Signal, ΔVBE... Difference between the base-emitter voltages VBE of the third and fourth emitter followers Q2 and Q13, VCAP.
Voltage across capacitor C1, ΔG: gain error of feedback amplifier circuit, K: gain of negative feedback amplifier circuit.

Claims (4)

[Claims] 1. A differential charging device comprising: a power storage unit charged by a first current and a second current; and a feedback amplifying unit biasing the power storage unit by feedback-amplifying a difference voltage between both ends of the power storage unit. A pump circuit for detecting currents flowing through both ends of the power storage means,
A differential charge pump circuit comprising: a plurality of current detecting means; and a negative feedback amplifying means for performing negative feedback amplification of a difference voltage between outputs of the two current detecting means and adding the difference voltage to an output of the feedback amplifying means. 2. A power storage means charged by a first current and a second current, and first and second power supply means for inputting a voltage between both ends of the power storage means to a base via first and second emitter followers, respectively. 2 transistors and the first and second transistors
And third and fourth emitter followers for respectively supplying the collector output of the transistor to both ends of the power storage means, and feedback amplification means for feedback-amplifying the difference voltage across the power storage means and biasing the power storage means. A differential charge pump circuit comprising: a voltage detecting means for detecting a difference between a base-emitter voltage of the third and fourth emitter followers; and a fifth and a sixth voltage detecting means for detecting a difference voltage by the voltage detecting means.
Input between both bases via the emitter follower of
Third and fourth transistors for supplying the respective collector outputs to the third and fourth emitter followers; negative feedback amplification of the differential voltage detected by the voltage detection means to the output of the feedback amplification means; A differential charge pump circuit having an additional negative feedback amplifier. 3. A power storage means charged by a first current and a second current, and first and second power supply means for inputting a voltage between both ends of the power storage means to a base via first and second emitter followers, respectively. 2 transistors and the first and second transistors
And third and fourth emitter followers for respectively supplying the collector output of the transistor to both ends of the power storage means, and feedback amplification means for feedback-amplifying the difference voltage across the power storage means and biasing the power storage means. A differential charge pump circuit comprising: two current detection means for detecting currents flowing through the third and fourth emitter followers; and fifth and sixth outputs respectively from the two current detection means.
A third transistor and a fourth transistor, respectively, which are inputted to a base via an emitter follower of the above and supply respective collector outputs to the third and fourth emitter followers.
A negative feedback amplifying means for performing negative feedback amplification of a difference voltage between outputs of the current detection means and adding the difference voltage to an output of the feedback amplification means. 4. The negative feedback amplifying means comprises: a current source connected to the emitters of the third and fourth transistors; and a first and second current sources connected to the collectors of the third and fourth transistors. 4. The differential charge pump circuit according to claim 3, further comprising: a resistor; and determining a negative feedback amplification factor of the negative feedback amplifier based on a current value of the current source and resistance values of the first and second resistors. 5. .