JPH10189979A - Manufacture of thin-film transistor and thin-film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a formation method of a thin-film transistor of an LDD structure, wherein element characteristic is improved by a dimple process in a manufacturing method of an active matrix type liquid crystal display device in which a polysilicon TFT is used. SOLUTION: After a polysilicon layer 2 which becomes a working layer of a TFT has been formed on a substrate 1 and a gate insulation film and a gate electrode 4 have been formed, a protective film which becomes a barrier layer 5 during ion implantation is formed to a specified thickness which is predetermined with relation to ion implantation conditions. After it is patterned so that an outer shape thereof matches a boundary between a low concentration region 6a and a high concentration region 6b which become a source/drain regions of an LDD structure, ion implantation is performed for a polysilicon layer 2 by using it as a mask.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to an LDD (Lightly
The present invention relates to a manufacturing technique of a thin film transistor having a Doped Drain structure, for example, a technique suitable for use in a manufacturing process of an active matrix type liquid crystal display device using a polysilicon TFT (thin film transistor) as a switch element for selectively applying a voltage to a pixel electrode. Regarding

[0002]

2. Description of the Related Art Conventionally, as an active matrix type liquid crystal display device, pixel electrodes are formed in a matrix on a glass substrate, and a TFT using polysilicon is formed corresponding to each pixel electrode. LC with a structure in which a voltage is applied to the electrodes by a TFT to drive the liquid crystal
D (liquid crystal display) has been put to practical use.

On the other hand, in a semiconductor integrated circuit using a MOSFET as an active element, when a bias voltage is applied, an electric field concentrates on a channel-side boundary of a source / drain region formed in self-alignment with a gate electrode. In order to prevent the drawback that the breakdown voltage of the device is lowered due to the occurrence, an LDD structure MOSFET is used in which a low concentration source / drain region is formed near the gate electrode and a high concentration source / drain region is formed outside thereof. What has been done has been put to practical use.

[0004]

The above-mentioned polysilicon TF
In an active matrix type LCD using T, if an attempt is made to use a TFT having an LDD structure in order to improve device characteristics, a low-concentration source / drain region and a high-concentration source / drain region must be formed separately. Therefore, there is a problem that the process becomes complicated.

An object of the present invention is to provide an active matrix type LCD with an L
It is to provide a technique capable of forming a TFT having a DD structure.

Another object of the present invention is to provide a technique capable of reducing the resistance of a gate line in an active matrix type LCD.

Still another object of the present invention is to provide a technique capable of effectively preventing peeling between layers when a gate line has a multilayer structure in order to reduce the resistance of the gate line in an active matrix type LCD. is there.

[0008]

In order to achieve the above-mentioned object, the present invention forms a semiconductor layer (polysilicon layer) which becomes an operating layer of a TFT on a substrate such as a glass substrate, and a gate insulating film is formed on the surface thereof. After forming a film and further forming a gate electrode (including the gate line) on this gate insulating film, a protective film such as silicon oxide that becomes a weak barrier layer at the time of ion implantation is formed in relation to the ion implantation conditions. It is formed to a predetermined thickness that has been set, and is patterned so that its outer shape matches the boundary between the low-concentration region and the high-concentration region which are the source / drain regions of the LDD structure, and this is used as a mask. The semiconductor layer is ion-implanted with a predetermined energy.

According to the above-mentioned means, an LDD structure TFT having a low concentration source / drain region near the gate electrode and a high concentration source / drain region outside the gate electrode is formed by one-time ion implantation. be able to.

Further, the gate electrode and the gate line are
For example, it is desirable to have a multilayer structure in which a metal silicide layer is formed on a polysilicon layer. As a result, the resistance of the gate line can be reduced. And at this time,
Since the barrier layer covers the gate electrode and the gate line, it is possible to prevent the polysilicon layer forming the gate electrode and the gate line from being separated from the metal silicide layer.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

1 to 3 show a main part of a process to which the present invention is applied in the order of steps. 2 and 3 show a state before ion implantation and a state after ion implantation in a process of forming a polysilicon TFT by applying the present invention, respectively.

In FIG. 1, reference numeral 1 is a glass substrate. In this embodiment, first, a polysilicon layer 2 to be an operation layer of a TFT is formed on a glass substrate 1 by CVD or the like, for example, 10
It is formed to a thickness such as 00 angstrom. next,
By thermally oxidizing this, the surface of the polysilicon layer 2 is 700-1500 angstroms, preferably 12
A gate oxide film 3 having a thickness of about 50 angstroms is formed. As a result, the polysilicon layer 2 finally becomes 3
The thickness is about 50 to 450 angstroms.

Next, a second polysilicon layer 4a doped with phosphorus, for example, is formed on the gate insulating film 3, and a silicide layer 4b of a metal such as tungsten silicide (WSi) is formed thereon. Then, by patterning these, as shown in FIG. 1, the gate electrode 4 located substantially in the center of the polysilicon layer 2 is formed. Second polysilicon layer 4a constituting gate electrode 4
Is formed to a thickness of 1000 angstroms by, for example, the CVD method. The silicide layer (WSi) 4b thereover is formed to a thickness of, for example, 1000 angstroms by a sputtering method.

Next, after a silicon oxide film is formed by a CVD method or the like so as to cover the gate electrode 4 and the gate insulating film 3, patterning is performed so as to cover only the periphery of the gate electrode 4 and ion implantation is performed. The weak barrier layer 5 is formed. At this time, the width d of the step 5a at the end of the barrier layer 5 made of silicon oxide is 0.5 to 0.5 depending on the width of a low concentration source / drain region to be formed later.
The thickness is set to about 2.5 μm, more preferably about 1.5 μm.
The thickness of the silicon oxide film constituting the barrier layer 5 depends on its material, ion species used, ion implantation energy, material and thickness of the gate insulating film 3, low-concentration source / drain regions and high-concentration source / drain regions. It is determined by the relationship with the design concentration, etc.
A range of 1500 Angstroms is reasonable.

As an example, phosphorus ions are implanted with an energy of about 90 eV, and a low concentration source / drain region has a concentration of 1 × 10 ¹³ / cm ³ and a high concentration source / drain region has a concentration of 1 × 10 ¹⁵ / cm ^3. In this case, the barrier layer 5 has a thickness of about 1000 angstroms. Examples of ionic species other than phosphorus include arsenic. The implantation energy is not limited to 90 eV, and the thickness of the barrier layer 5, the material and thickness of the gate insulating film 3,
Low-concentration source / drain regions and high-concentration source / drain
It is determined in relation to the design concentration of the drain region and the like.

According to the above-described embodiment, since the gate electrode 4 is located under the central portion of the barrier layer 5, the implanted ions do not reach the polysilicon layer 2 and the step difference is formed at the end portion of the barrier layer 5. Since the portion 5a becomes a weak barrier layer and only a part of the phosphorus ions penetrate, a low concentration source / drain region 6a is formed in the polysilicon layer 2 below the step portion 5a as shown in FIG. . Further, since phosphorus ions are sufficiently implanted into the region outside the polysilicon layer 2 which is not covered with the barrier layer 5, the high concentration source / drain regions 6b are formed. As described above, according to the method of the embodiment, the LDD structure having the low-concentration source / drain regions 6a near the gate electrode and the high-concentration source / drain regions 6b outside thereof is formed by one ion implantation. A TFT can be formed.

In the above embodiment, the case where the barrier layer 5 is formed of silicon oxide has been described.
Is not limited to silicon oxide, and may be polysilicon or the like. The film thickness in that case is about 130
Although 0 angstrom is appropriate, it is not limited thereto, and the ion species to be used, ion implantation energy, material and thickness of the gate insulating film 3, source / drain regions of low concentration and source / drain regions of high concentration, etc. It may be decided in relation to.

In the above embodiment, the gate electrode 4 has a two-layer structure of the polysilicon layer 4a and the WSi layer 4b.
The present invention is not limited to this, and a three-layer structure in which a metal layer such as aluminum is further stacked may be used, or an alloy of silicon and a metal other than tungsten, such as tantalum, may be used as the silicide layer. By thus forming the gate electrode 4 in the multilayer structure of the polysilicon layer and the metal silicide layer, the resistance of the gate line can be reduced.
Moreover, at this time, since the barrier layer 5 covers at least the gate electrode 4, it is possible to prevent the polysilicon layer 4a and the silicide layer 4b forming the gate electrode from peeling off.

That is, if a heat treatment such as annealing is performed after the gate electrode is formed, the silicide is apt to undergo abnormal oxidation on the exposed surface, which is accompanied by rapid deposition expansion. As a result, a stress difference occurs between the silicide layer 4b and the lower polysilicon layer 4a, which causes film peeling. However, in the above embodiment, the barrier layer 5 is formed on the silicide layer 4b. It is possible to prevent the surface of the silicide layer 4b from coming into contact with oxygen in the atmosphere, so that the expansion of the deposition due to the oxidation of the silicide in the subsequent heat treatment can be suppressed and the peeling from the polysilicon layer 4a can be prevented.

FIG. 4 shows the polysilicon TFT of the above embodiment.
1 shows a cross-sectional structure of a liquid crystal panel substrate in which one pixel portion is completed in the state of FIG.

In FIG. 4, 7 is a first interlayer insulating film made of silicon oxide, 8 is a second interlayer insulating film made of BPSG (silicon oxide glass containing boron and phosphorus), and 9 is a conductive layer made of aluminum. Signal line consisting of 10
Is a pixel electrode made of an ITO film. The first interlayer insulating film 7 is formed to a thickness of 8000 angstrom by, for example, the CVD method. The second interlayer insulating film 8
A signal line 9 made of aluminum is formed on the first interlayer insulating film 7.
Is formed after forming. The signal line 9 is formed in the first interlayer insulating film 7 and the gate insulating film 3 by opening a contact hole 11, and is formed to a thickness of about 3500 Å by vapor deposition or the like, and is brought into contact with the polysilicon layer 2.

The pixel electrode 10 includes a gate insulating film 3 above the drain region of the polysilicon layer 2 and a first interlayer insulating film 7.
And a contact hole 12 extending over the second interlayer insulating film 8.
Is formed by dry etching, an ITO film is formed to a thickness of 1500 angstroms by sputtering, and is patterned by selective etching.

Further, an alignment film made of polyimide or the like is formed on the pixel electrode 10 and the second interlayer insulating film 8 to a thickness of about 2000 to 3000 angstroms, and rubbing (alignment treatment) is performed. This is a liquid crystal panel substrate.

FIG. 5 shows an example of a plane layout configuration of a pixel including the TFT of the above embodiment. In FIG. 5, the intersection of the gate line 4 and the signal line 9 indicated by hatching A is the channel portion of the TFT.

Although not particularly limited, in this embodiment, in order to increase the capacitance connected to the drain of the transistor (TFT), the first polysilicon layer 2 constituting the operation layer is formed as shown in FIG. Along with the signal line 9 and the second polysilicon layer forming the gate line 4 of the adjacent pixel (upper side in the figure), the gate line 4
A part of the second polysilicon layer constituting the above is extended along the signal line 9 like 4a.
Thereby, the first layer and the second layer formed below the signal line 9 are formed.
The capacitance between the polysilicon layers (the gate insulating film 3 is made of a dielectric material) is the drain (sometimes called a source) of the TFT that applies a voltage to each pixel electrode as a storage capacitance.
Will be connected to.

The substrate for a liquid crystal panel configured as described above has a common electrode (a color filter layer as necessary) made of a transparent conductive film (ITO) to which an LC common potential is applied on the surface side. Are placed at appropriate intervals, and a TN (Twisted Nematic) type liquid crystal or SH (Super Ho
meotropic) type liquid crystal is enclosed and configured as a liquid crystal panel. The present invention can be applied to a liquid crystal panel substrate that constitutes either a transmissive liquid crystal panel or a reflective liquid crystal panel. Furthermore, the present invention can be used for general thin film transistors that constitute circuits used for applications other than liquid crystal panel substrates.

FIG. 6 shows the TF of the liquid crystal panel of each of the above embodiments.
4 shows a system configuration example of a T-side substrate. In the figure, 90
Are pixels arranged corresponding to the intersections of the gate lines 2 and the signal lines 3 arranged so as to cross each other. Each pixel 90 has a pixel electrode 14 made of ITO or the like and a signal line connected to the pixel electrode 14. 3 that applies a voltage corresponding to the image signal on
FT91. The TFTs 91 on the same row (Y direction) have their gates connected to the same gate line 2 and their drains connected to the corresponding pixel electrodes 14. The TFTs 91 in the same column (X direction) have the same signal line 3 from the same source.
It is connected to the. In this embodiment, peripheral circuits (X, Y shift registers and sampling means) 50, 6
The transistor forming 0 is formed of a so-called polysilicon TFT having a polysilicon layer as an operation layer similarly to the pixel driving TFT, and the transistors forming the peripheral circuits 50 and 60 are formed by the same process as the pixel driving TFT. , Formed simultaneously.

In this embodiment, a shift register (hereinafter referred to as an X shift register) 51 for sequentially selecting the signal lines 3 is arranged on one side (upper side in the figure) of a pixel area (pixel matrix) 20. On the other side, a shift register (hereinafter referred to as a Y shift register) 61 for sequentially selecting and driving the gate lines 2 is provided. Further, a sampling switch (TFT) 52 is provided at the other end of each signal line 3 in which a buffer 63 is provided at the next stage of the Y shift register 61 if necessary, and these sampling switches 52 are provided. Image signals VID1 to VI input to external terminals 74, 75, 76
It is connected between the video lines 54, 55 and 56 for transmitting D3, and is configured to be turned on / off sequentially by the sampling pulse output from the X shift register 51. The X shift register 51 has terminals 72,
Clocks CLX1, C externally input via 73
LK2, all signal lines 3 during one horizontal scanning period.
Sampling pulse X for selecting
1, X2, X3, ... Xn are formed and supplied to the control terminal of the sampling switch 52. On the other hand, the Y shift register 61 is operated in synchronization with clocks CLY1 and CLY2 input from the outside via terminals 77 and 78, and sequentially drives the gate lines 2.

FIGS. 7A and 7B show a sectional structure and a planar layout structure of a liquid crystal panel 30 to which the liquid crystal panel substrate is applied. As shown in the figure, on the front surface side of the liquid crystal panel substrate 10, there is an incident side having a counter electrode 33 made of a transparent conductive film (ITO) to which an LC common potential is applied and a color filter layer (including a black matrix) 13. Glass substrates 35 are arranged at appropriate intervals, and the periphery thereof is
(Twisted Nematic) LCD or SH (Super Homeotro)
pic) type liquid crystal 37 and the like are filled to form a liquid crystal panel 30. Further, the upper portions of the peripheral circuits 50 and 60 are configured to be shielded from light by, for example, black matocox provided on the counter substrate 31. Reference numeral 38 is a liquid crystal injection port provided on the counter substrate 31 side.

The liquid crystal panel substrate of the above embodiment has a transparent conductive film (IT) to which an LC common potential is applied on the surface side.
The counter electrode made of O) and the color filter layer corresponding to the pixel electrode and the glass substrate on the incident side on which the black matrix surrounding the pixel electrode is formed are arranged at appropriate intervals, and the periphery is sealed with a sealing material. TN in the gap
(Twisted Nematic) type liquid crystal or SH (Super Homeotr)
opic) type liquid crystal etc. are filled and configured as a liquid crystal panel.

FIG. 8 shows a configuration example of a video projector as an example of a projection type display device to which the liquid crystal panel of the above embodiment is applied as a light valve.

In FIG. 8, 370 is a light source such as a halogen lamp, 371 is a parabolic mirror, 372 is a heat ray cut filter, 373, 375 and 376 are blue reflections, respectively.
Green reflection, red reflection dichroic mirror, 374
377 is a reflection mirror, 378, 379 and 380 are light valves composed of the liquid crystal panel of the above embodiment, and 383 is a dichroic prism.

In the video projector of this embodiment, the white light emitted from the light source 370 is condensed by the parabolic mirror 371 and passes through the heat ray cut filter 372 to block the heat rays in the infrared region, so that only visible light is emitted. It is incident on the dichroic mirror system. Then, first, blue light (wavelength of approximately 50 nm or less) is reflected by the blue reflecting dichroic mirror 373, and the other light (yellow light) is transmitted. The reflected blue light changes its direction by the reflection mirror 374 and enters the blue modulation light valve 378.

On the other hand, the light transmitted through the blue reflecting dichroic mirror 373 is reflected by the green reflecting dichroic mirror 3.
75, the green light (wavelength of about 500 to 600 nm) is reflected, and the other light, red light (about 600 nm)
(wavelengths above nm) are transmitted. Dichroic mirror 3
The green light reflected at 75 is a green modulated light valve 379
Incident on. The red light transmitted through the dichroic mirror 375 changes its direction by the reflection mirrors 376 and 377 and enters the red modulation light valve 380.

The light valves 378, 379, 380
Blue, green, supplied from a video signal processing circuit (not shown)
The lights that are respectively driven by the red primary color signals and enter the respective light valves are modulated by the respective light valves and then combined by the dichroic prism 383. The dichroic prism 383 is formed so that the red reflecting surface 381 and the blue reflecting surface 382 are orthogonal to each other. Then, the color image synthesized by the dichroic prism 383 is enlarged and projected on the screen by the projection lens 384 and displayed.

[0037]

As described above, according to the present invention, the semiconductor layer (polysilicon layer) which becomes the operation layer of the TFT is formed on the insulating substrate, and the gate insulating film is formed on the surface of the semiconductor layer. On top of gate electrode (including gate line)
Is formed, a protective film serving as a weak barrier layer at the time of ion implantation is formed to a predetermined thickness given in relation to ion implantation conditions, and the outer shape is formed as a source / drain region of an LDD structure. After patterning so as to match the boundary between the low-concentration region and the high-concentration region, the ion implantation is performed on the semiconductor layer with a predetermined energy using this as a mask. In addition, there is an effect that a TFT having an LDD structure having a low concentration source / drain region near the gate electrode and a high concentration source / drain region outside the gate electrode can be formed.

Further, the gate electrode and the gate line are
For example, a multilayer structure in which a metal silicide layer is formed on a polysilicon layer can reduce the resistance of the gate electrode and the gate line, and the barrier layer covers the gate electrode and the gate line. Therefore, there is an effect that it is possible to prevent the polysilicon layer forming the gate electrode and the gate line from being separated from the silicide layer.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a state after forming a gate electrode in a process of forming a polysilicon TFT on a liquid crystal panel substrate by applying the method of the present invention.

FIG. 2 is a cross-sectional view showing a state before ion implantation in a process of forming a polysilicon TFT on a liquid crystal panel substrate by applying the method of the present invention.

FIG. 3 is a cross-sectional view showing a state after ion implantation in a process of forming a polysilicon TFT on a liquid crystal panel substrate by applying the method of the present invention.

FIG. 4 is a sectional view showing the structure of a pixel having a polysilicon TFT formed by applying the method of the present invention.

FIG. 5 is a plan layout view of a pixel having a polysilicon TFT formed by applying the method of the present invention.

FIG. 6 is a block diagram showing a system configuration example of a liquid crystal panel substrate suitable for applying the present invention.

FIG. 7 is a cross-sectional view and a plan view illustrating a configuration example of a liquid crystal panel using the liquid crystal panel substrate according to the present invention.

FIG. 8 is a schematic configuration diagram of a video projector as an example of a projection display device in which an LCD using the liquid crystal panel substrate of the embodiment is applied as a light valve.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Glass substrate 2 Polysilicon layer (TFT operation layer) 3 Gate insulating film 4 Gate electrode (gate line) 5 Barrier layer 6a Low-concentration source / drain region 6b High-concentration source / drain region 7 First interlayer insulating film 8 Second Interlayer insulating film 9 Signal line 10 Pixel electrode 11, 12 Contact hole 20 Pixel region 30 Liquid crystal panel 31 Counter substrate 33 Counter electrode 36 Seal material 37 Liquid crystal 50, 60 Peripheral circuit 51 X shift register 52 Sampling switch 54-56 Video line 61 Y shift register 72 to 78 External terminal 90 Pixel 91 Pixel driving TFT 370 Lamp 373, 375, 376 Dichroic mirror 374, 377 Reflecting mirror 378, 379, 380 Light valve 383 Dichroic prism 384 Projection lens

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification code FI H01L 29/78 617J

Claims (10)

[Claims] 1. A pixel electrode is formed in a matrix on a substrate, and a thin film transistor is formed corresponding to each pixel electrode, and a voltage is applied to the pixel electrode via the thin film transistor. In a manufacturing process of a liquid crystal panel substrate, a step of forming a semiconductor layer to be an operation layer of a thin film transistor on the substrate, a step of forming a gate insulating film on a surface of the semiconductor layer, and a gate on the gate insulating film. A step of forming an electrode, a step of forming a barrier layer having a predetermined thickness to cover the gate electrode, and a step of ion-implanting impurities so as to reach the semiconductor layer after the barrier layer is formed. Manufacturing method of a thin film transistor. 2. The method according to claim 1, wherein the gate electrode and the gate line have a multilayer structure including at least a polysilicon layer and a metal silicide layer formed thereon. . 3. The gate electrode and the gate line have at least a polysilicon layer, and the impurities contained in the polysilicon layer and the impurities to be ion-implanted have the same or different conductivity types. The method of manufacturing a thin film transistor according to claim 1 or 2, characterized in that: 4. The barrier layer is made of silicon oxide,
The method of manufacturing a thin film transistor according to claim 1, 2 or 3, wherein the thickness is 500 to 1500 angstrom. 5. The semiconductor device according to claim 1, wherein said ion-implanted impurity is phosphorus or boron.
Or the method for manufacturing a thin film transistor according to 4. 6. A semiconductor layer serving as an operation layer of a transistor is formed on a substrate, and a gate electrode is formed on a surface of the semiconductor layer via a gate insulating film. A thin film transistor comprising a high concentration source / drain region and a high concentration source / drain region formed outside thereof. 7. A barrier layer having a predetermined thickness and patterned so as to match the boundary between the low-concentration region and the high-concentration region serving as the source / drain regions is formed on the gate electrode. The thin film transistor according to claim 6, which is formed by: 8. A liquid crystal panel substrate comprising pixel electrodes arrayed and formed in a matrix on a substrate, and a transistor for igniting a voltage is formed at each pixel electrode corresponding to each pixel electrode. Item 6. A substrate for a liquid crystal panel, comprising the thin film transistor according to item 6 or 7. 9. A liquid crystal panel substrate according to claim 8, wherein:
A liquid crystal panel, wherein a transparent substrate having a counter electrode is arranged at an appropriate interval, and liquid crystal is sealed in a gap between the liquid crystal panel substrate and the transparent substrate. 10. A light source, a liquid crystal panel configured to modulate and transmit or reflect light from the light source, and projection for condensing and modulating the light modulated by these liquid crystal panels. A projection display device comprising: an optical unit.