JPH10163398A - Lead frame - Google Patents
Lead frameInfo
- Publication number
- JPH10163398A JPH10163398A JP8317546A JP31754696A JPH10163398A JP H10163398 A JPH10163398 A JP H10163398A JP 8317546 A JP8317546 A JP 8317546A JP 31754696 A JP31754696 A JP 31754696A JP H10163398 A JPH10163398 A JP H10163398A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- lead frame
- gate
- flow
- partition plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、リードフレームの
構造に関し、特に、リードフレームの樹脂封入部の構造
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a lead frame, and more particularly, to a structure of a resin sealing portion of a lead frame.
【０００２】[0002]
【従来の技術】従来より、ＬＳＩ等の半導体チップは、
樹脂封止の工程を経てパッケージ化されてきた。樹脂封
止は、半導体チップ、配線等を水、埃等から保護し、ま
た人による取り扱いを容易とするために行われるもので
ある。2. Description of the Related Art Conventionally, semiconductor chips such as LSIs have been
It has been packaged through a resin sealing process. The resin sealing is performed to protect semiconductor chips, wirings, and the like from water, dust, and the like, and to facilitate handling by humans.
【０００３】図２は従来の樹脂封止を説明するための概
略図である。図２（ａ）は、リード３と半導体チップ１
とが配線１２によって電気的に接続された状態を示す概
略上面図であり、ここでは、ＬＯＣ（Ｌｅａｄ Ｏｎ
Ｃｈｉｐ）構造の半導体装置の例を示している。リード
は樹脂封止後に取り除かれるタイバ１１によって接続さ
れ、一連のリードフレームを形成している。リードフレ
ームは、樹脂封止後に取り除かれるリードフレーム枠７
を有している。このリードフレーム枠７には、樹脂封止
によりパッケージが形成される各チップの各々に対応し
て、樹脂封止用樹脂を注入するための樹脂封止用ゲート
１３が形成されている。すなわち、リードフレーム枠７
の一部分が、図２（ａ）に示すように、切除されてい
る。FIG. 2 is a schematic view for explaining a conventional resin sealing. FIG. 2A shows the leads 3 and the semiconductor chip 1.
FIG. 2 is a schematic top view showing a state in which LOC (Lead On) is electrically connected by a wiring 12.
2 shows an example of a semiconductor device having a (Chip) structure. The leads are connected by a tie bar 11 which is removed after resin sealing, forming a series of lead frames. The lead frame is a lead frame frame 7 that is removed after resin sealing.
have. In the lead frame frame 7, a resin sealing gate 13 for injecting a resin sealing resin is formed corresponding to each of the chips on which a package is formed by resin sealing. That is, the lead frame frame 7
Is cut off as shown in FIG.
【０００４】樹脂封止の際には、リードフレームの上下
から、図２（ａ）の状態の半導体チップ１を包み込むよ
うに樹脂封止用の型で挟み込む。図２（ａ）のＢ−Ｂ′
線断面において、前述の型で挟み込んだ状態を図２
（ｂ）に示す。樹脂注入用ゲート１３は前述の型により
完全に覆われる。そして、リードフレーム枠７の下部か
らエポキシ樹脂等の樹脂封止用樹脂が下ゲート９、樹脂
封入ゲート１３、上ゲート６を通って上キャビティ９、
下チャビティ８に注入される。上ゲート６は、上キャビ
ティ９、下キャビティ８の各々に均一に樹脂を注入する
ために設けられている構造である。At the time of resin sealing, the semiconductor chip 1 in the state shown in FIG. 2A is sandwiched from above and below the lead frame with a resin sealing mold. BB 'in FIG.
FIG. 2 shows a state of being sandwiched by the above-described mold in the line cross section.
(B). The resin injection gate 13 is completely covered by the above-mentioned mold. Then, from the lower part of the lead frame frame 7, a resin sealing resin such as an epoxy resin passes through the lower gate 9, the resin-encapsulated gate 13, the upper gate 6 and the upper cavity 9
Injected into lower chamber 8. The upper gate 6 has a structure provided to uniformly inject resin into each of the upper cavity 9 and the lower cavity 8.
【０００５】[0005]
【発明が解決しようとする課題】しかし、従来の構造で
は、すなわち、上ゲート６では、上キャビティ９、下キ
ャビティ８の各々に均一に樹脂を注入することが十分に
達成できなかった。However, in the conventional structure, that is, in the upper gate 6, it has not been possible to sufficiently achieve uniform injection of the resin into each of the upper cavity 9 and the lower cavity 8.
【０００６】すなわち、図２（ｂ）に示すように、樹脂
（矢印で樹脂の流れを示す）は、下ゲート９から流れ込
む。従って、樹脂の流れをリードフレームの平行方向に
変換すべく上ゲート６で樹脂の流れを緩和しても、樹脂
は下キャビティ８よりも上キャビティ９の方へ多く流れ
込む。このため、キャビティの上下で半導体チップ１お
よびリード３等に異なる圧力が加わることになり、従っ
て、半導体チップ１とリード３の位置がずれ、これによ
り配線１２が断線するという損傷が生じていた。That is, as shown in FIG. 2B, the resin (the flow of the resin is indicated by an arrow) flows from the lower gate 9. Therefore, even if the flow of the resin is reduced by the upper gate 6 so as to convert the flow of the resin in the parallel direction of the lead frame, the resin flows into the upper cavity 9 more than the lower cavity 8. For this reason, different pressures are applied to the semiconductor chip 1 and the leads 3 and the like above and below the cavity, so that the positions of the semiconductor chip 1 and the leads 3 are displaced, thereby causing damage such that the wiring 12 is disconnected.
【０００７】よって、本発明の目的は、かかる損傷を防
止し、半導体装置製造歩留まりの向上を可能とするリー
ドフレームを提供することにある。SUMMARY OF THE INVENTION It is an object of the present invention to provide a lead frame which can prevent such damage and improve the production yield of semiconductor devices.
【０００８】[0008]
【課題を解決するための手段】かかる目的のために、本
発明によるリードフレームは、樹脂注入用ゲートに樹脂
の流れを分流するための仕切板を設けたことを特徴とす
る。To this end, a lead frame according to the present invention is characterized in that a partition plate for diverting the flow of resin is provided at the gate for resin injection.
【０００９】本発明による半導体装置は、樹脂注入用ゲ
ートに仕切板を形成したことで樹脂封止時の樹脂の流れ
を制御でき、これにより半導体チップの位置ずれ、断線
等の損傷を防ぎ、ひいては製造歩留まりを向上させるこ
とができる。In the semiconductor device according to the present invention, the flow of the resin at the time of the resin sealing can be controlled by forming the partition plate on the resin injection gate, thereby preventing the semiconductor chip from being displaced and from being damaged such as disconnection, and furthermore, The manufacturing yield can be improved.
【００１０】[0010]
【発明の実施の形態】以下に、本発明について図１を参
照して説明する。図１（ａ）は樹脂封止時における半導
体装置の概略上面図、図１（ｂ）は樹脂封止用の型によ
りリードフレームを挟み込んだ後の図１（ａ）における
Ａ−Ａ′線における断面概略図である。図１では、従来
例を示す図２と同一構成の部分については、同一符号を
付し、説明を省略する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to FIG. FIG. 1A is a schematic top view of a semiconductor device at the time of resin sealing, and FIG. 1B is a view taken along line AA ′ in FIG. 1A after a lead frame is sandwiched by a resin sealing mold. FIG. In FIG. 1, parts having the same configuration as in FIG. 2 showing the conventional example are denoted by the same reference numerals, and description thereof will be omitted.
【００１１】本発明では、リードフレームの樹脂注入用
ゲート１３に、樹脂の流れを制御するための仕切板４を
設けたことを特徴としている。The present invention is characterized in that a partition plate 4 for controlling the flow of resin is provided in the resin injection gate 13 of the lead frame.
【００１２】このため、図１（ｂ）に示すように、下キ
ャビティ８へは仕切板４により流れを強制的に変化させ
られた樹脂が流れ込み、また上キャビティ９へは上ゲー
ト６を通って樹脂が流れ込む。図１に示す例では、仕切
板４の厚みはリードフレーム枠７の約半分の厚みとして
おり、よって樹脂の流れを滞らせることはない。また、
仕切板４の面積は、樹脂注入用ゲート１３の全面積の約
半分としているため、上キャビティ９、下キャビティ８
の各々に流れ込む樹脂の分量をほぼ等しく制御すること
ができる。従って、半導体チップ１等に上下キャビティ
の各々から異なる圧力が加わることはない。Therefore, as shown in FIG. 1B, the resin whose flow is forcibly changed by the partition plate 4 flows into the lower cavity 8 and the upper cavity 6 through the upper gate 6. The resin flows. In the example shown in FIG. 1, the thickness of the partition plate 4 is about half the thickness of the lead frame 7, so that the flow of the resin is not blocked. Also,
Since the area of the partition plate 4 is about half of the total area of the resin injection gate 13, the upper cavity 9 and the lower cavity 8
Can be controlled substantially equally. Therefore, different pressures are not applied to the semiconductor chip 1 and the like from each of the upper and lower cavities.
【００１３】また、図１（ｂ）においては、仕切板４は
リードフレームの面に平行に設けられているが、樹脂封
止する半導体装置の種類に応じて、適当な傾きを持たせ
てもよい。すなわち、上下キャビティに均等に樹脂を流
れ込ませるべく、予め仕切板４の傾きを計算してリード
フレームを製造すればよい。この場合には、仕切板４の
面積は、樹脂注入用ゲート１３の全面積の約半分にする
必要はなく、用途に応じて適当に変更することができ
る。仕切板４はリードフレームの製造段階で同時にプレ
ス加工もしくはエッチング加工することで、容易に製造
することができる。さらに、プレス加工もしくはエッチ
ング加工で製造する場合には、１種のリードフレームで
多種の半導体装置の樹脂封止に対応できるよう、仕切板
４とリードフレーム枠７との間にはスリットを設け、仕
切板４を適宜取りはずすようにしてもよい。In FIG. 1B, the partition plate 4 is provided parallel to the surface of the lead frame. However, the partition plate 4 may have an appropriate inclination depending on the type of the semiconductor device to be resin-sealed. Good. That is, in order to make the resin flow into the upper and lower cavities evenly, the inclination of the partition plate 4 may be calculated in advance to manufacture the lead frame. In this case, the area of the partition plate 4 does not need to be about half of the entire area of the gate 13 for resin injection, and can be appropriately changed depending on the application. The partition plate 4 can be easily manufactured by simultaneously pressing or etching the lead frame during the manufacturing process. Furthermore, when manufacturing by pressing or etching, a slit is provided between the partition plate 4 and the lead frame 7 so that one type of lead frame can cope with resin sealing of various types of semiconductor devices. The partition plate 4 may be appropriately removed.
【図１】（ａ）本発明の実施例を示す半導体装置の概略
平面図である。 （ｂ）本発明の実施例を示す半導体装置の概略断面図で
ある。FIG. 1A is a schematic plan view of a semiconductor device according to an embodiment of the present invention. (B) It is an outline sectional view of the semiconductor device showing the example of the present invention.
【図２】（ａ）本発明の従来例を示す半導体装置の概略
平面図である。 （ｂ）本発明の従来例を示す半導体装置の概略断面図で
ある。FIG. 2A is a schematic plan view of a semiconductor device showing a conventional example of the present invention. (B) is a schematic sectional view of a semiconductor device showing a conventional example of the present invention.
１ 半導体チップ ２ 絶縁膜 ３ リード ４ 仕切板 ５ 下ゲート ６ 上ゲート ７ リードフレーム枠 ８ 下キャビティ ９ 上キャビティ １０ アウタリード １１ タイバ １２ 配線 １３ 樹脂注入用ゲート REFERENCE SIGNS LIST 1 semiconductor chip 2 insulating film 3 lead 4 partition plate 5 lower gate 6 upper gate 7 lead frame frame 8 lower cavity 9 upper cavity 10 outer lead 11 tie bar 12 wiring 13 gate for resin injection
Claims (4)
注入用ゲートを備えたリードフレームにおいて、 前記樹脂注入用ゲートに前記樹脂の流れを分流するため
の仕切板を設けたことを特徴とするリードフレーム。1. A lead frame having a resin injection gate for injecting a resin at the time of resin sealing, wherein a partition plate for diverting the flow of the resin is provided in the resin injection gate. Lead frame to do.
ムの厚みより薄いことを特徴とする請求項１記載のリー
ドフレーム。2. The lead frame according to claim 1, wherein a thickness of said partition plate is smaller than a thickness of said lead frame.
一素材であり、前記リードフレームがプレス加工もしく
はエッチング加工により形成されると同時に前記プレス
加工もしくはエッチング加工により形成されることを特
徴とする請求項２記載のリードフレーム。3. The partition plate is made of the same material as the lead frame, and the lead frame is formed by pressing or etching at the same time as the lead frame is formed by pressing or etching. Item 4. The lead frame according to Item 2.
続部には、スリットを形成していることを特徴とする請
求項３記載のリードフレーム。4. The lead frame according to claim 3, wherein a slit is formed in a connecting portion between the partition plate and the lead frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8317546A JPH10163398A (en) | 1996-11-28 | 1996-11-28 | Lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8317546A JPH10163398A (en) | 1996-11-28 | 1996-11-28 | Lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10163398A true JPH10163398A (en) | 1998-06-19 |
Family
ID=18089469
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8317546A Pending JPH10163398A (en) | 1996-11-28 | 1996-11-28 | Lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10163398A (en) |
-
1996
- 1996-11-28 JP JP8317546A patent/JPH10163398A/en active Pending
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19990721 |